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111
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1 ;; Machine Description for Renesas RL78 processors
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2 ;; Copyright (C) 2011-2017 Free Software Foundation, Inc.
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3 ;; Contributed by Red Hat.
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4
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5 ;; This file is part of GCC.
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6
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7 ;; GCC is free software; you can redistribute it and/or modify
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8 ;; it under the terms of the GNU General Public License as published by
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9 ;; the Free Software Foundation; either version 3, or (at your option)
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10 ;; any later version.
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11
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12 ;; GCC is distributed in the hope that it will be useful,
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13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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15 ;; GNU General Public License for more details.
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16
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17 ;; You should have received a copy of the GNU General Public License
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18 ;; along with GCC; see the file COPYING3. If not see
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19 ;; <http://www.gnu.org/licenses/>.
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20
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21 ;; The insns in this file correspond to the actual opcodes the RL78
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22 ;; can issue with real registers. All insns in here should be
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23 ;; conditional on rl78_real_insns_ok() returning true, and should
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24 ;; allow virtual registers in their predicates - the reorg pass that
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25 ;; allocates physical registers uses the constraints to select
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26 ;; registers, but insns with virtual registers MUST match one of these
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27 ;; patterns - other than the constraints - so that the operand info is
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28 ;; properly set up for the alloc pass.
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29
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30 ;; This attribute reflects how the insn alters the Z flag,
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31 ;; based upon the value of the it's output. The default is NO
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32 ;; for no change, but other possibilities are UPDATE_Z if it changes
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33 ;; the Z flag and CLOBBER if the state of the flag is indeterminate.
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34 ;; The CY and AC flags are not set in the same way as the Z flag, so
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35 ;; their values are not tracked.
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36 (define_attr "update_Z" "no,update_Z,clobber" (const_string "no"))
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37
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38 ;;---------- Moving ------------------------
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39
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40 (define_insn "movqi_to_es"
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41 [(set (reg:QI ES_REG)
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42 (match_operand:QI 0 "register_operand" "a"))]
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43 ""
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44 "mov\tes, %0"
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45 )
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46
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47 (define_insn "movqi_from_es"
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48 [(set (match_operand:QI 0 "register_operand" "=a")
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49 (reg:QI ES_REG))]
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50 ""
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51 "mov\t%0, es"
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52 )
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53
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54 (define_insn "movqi_cs"
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55 [(set (reg:QI CS_REG)
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56 (match_operand:QI 0 "register_operand" "a"))]
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57 ""
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58 "mov\tcs, %0"
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59 )
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60
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61 (define_insn "*movqi_real"
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62 [(set (match_operand:QI 0 "rl78_nonimmediate_operand" "=Rv,RaxbcWab,RaxbcWab,a, bcx,R, WabWd2WhlWh1WhbWbcWs1v, bcx,WsaWsf")
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63 (match_operand 1 "rl78_general_operand" "0,K, M, RInt8sJvWabWdeWd2WhlWh1WhbWbcWs1,Wab,aInt8J,a, R, i"))]
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64 "rl78_real_insns_ok ()"
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65 "@
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66 ; mov\t%0, %1
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67 oneb\t%0
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68 clrb\t%0
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69 mov\t%0, %1
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70 mov\t%0, %1
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71 mov\t%0, %1
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72 mov\t%0, %1
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73 mov\t%0, %S1
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74 mov\t%0, %1"
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75 )
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76
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77 (define_insn "*movhi_real"
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78 [(set (match_operand:HI 0 "rl78_nonimmediate_operand" "=Rv,AB,AB,RSv,A,BDTvSWabWd2WdeWhlWh1WbcWs1, BDT,ABDT,v")
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79 (match_operand:HI 1 "rl78_general_operand" " 0,K, M, i, BDTvSWabWd2WdeWh1WhlWbcWs1,A, BDT,vS, ABDT"))]
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80 "rl78_real_insns_ok ()"
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81 "@
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82 ; movw\t%0, %1
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83 onew\t%0
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84 clrw\t%0
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85 movw\t%0, %1
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86 movw\t%0, %1
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87 movw\t%0, %1
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88 movw\t%0, %S1
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89 movw\t%0, %1
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90 movw\t%0, %1"
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91 )
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92
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93 ;;---------- Conversions ------------------------
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94
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95 (define_insn "*zero_extendqihi2_real"
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96 [(set (match_operand:HI 0 "nonimmediate_operand" "=Rv,A")
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97 (zero_extend:HI (match_operand:QI 1 "general_operand" "0,a")))]
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98 "rl78_real_insns_ok ()"
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99 "@
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100 mov\t%Q0, #0
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101 mov\tx, a \;mov\ta, #0"
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102 )
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103
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104 (define_insn "*extendqihi2_real"
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105 [(set (match_operand:HI 0 "nonimmediate_operand" "=A,A")
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106 (sign_extend:HI (match_operand:QI 1 "general_operand" "x,a")))]
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107 "rl78_real_insns_ok ()"
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108 "@
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109 shlw\t%0, 8 \;sarw\t%0, 8
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110 sarw\t%0, 8"
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111 )
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112
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113 ;;---------- Arithmetic ------------------------
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114
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115 (define_insn "*addqi3_real"
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116 [(set (match_operand:QI 0 "rl78_nonimmediate_operand" "=RvWabWhlWh1Wsa,RvWabWhlWh1Wsa,a,*bcdehl,Wsa")
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117 (plus:QI (match_operand:QI 1 "rl78_general_operand" "%0,0,0,0,0")
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118 (match_operand:QI 2 "rl78_general_operand" "K,L,RWhlWh1Wabi,a,i")))
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119 ]
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120 "rl78_real_insns_ok ()"
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121 "@
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122 inc\t%p0
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123 dec\t%p0
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124 add\t%0, %2
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125 add\t%0, %2
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126 add\t%0, %2"
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127 [(set (attr "update_Z") (const_string "update_Z"))]
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128 )
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129
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130 (define_insn "*addhi3_real"
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131 [(set (match_operand:HI 0 "rl78_nonimmediate_operand" "=vABDTWhlWh1WabWsa,vABDTWhlWh1WabWsa,v,v,A,S,S,A")
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132 (plus:HI (match_operand:HI 1 "rl78_general_operand" "%0,0,0,0,0,0,0,S")
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133 (match_operand:HI 2 "" "K,L,N,O,RWh1WhlWabiv,Int8Qs8,J,Ri")))
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134 ]
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135 "rl78_real_insns_ok ()"
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136 "@
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137 incw\t%p0
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138 decw\t%p0
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139 incw\t%0 \;incw\t%0
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140 decw\t%0 \;decw\t%0
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141 addw\t%0, %p2
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142 addw\t%0, %2
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143 subw\t%0, %m2
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144 movw\t%0, %1 \;addw\t%0, %2"
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145 [(set_attr "update_Z" "*,*,*,*,update_Z,update_Z,update_Z,update_Z")]
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146 )
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147
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148 (define_insn "*addqihi3a_real"
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149 [(set (match_operand:HI 0 "register_operand" "=R")
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150 (plus:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "R"))
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151 (match_operand:HI 2 "register_operand" "0")))
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152 ]
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153 "rl78_real_insns_ok ()"
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154 "add\t%q0, %q1 \;addc\t%Q0, #0"
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155 [(set (attr "update_Z") (const_string "update_Z"))]
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156 )
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157
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158 (define_insn "*subqi3_real"
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159 [(set (match_operand:QI 0 "nonimmediate_operand" "=a,R,v")
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160 (minus:QI (match_operand:QI 1 "general_operand" "0,0,0")
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161 (match_operand:QI 2 "rl78_general_operand" "RiWabWhbWh1Whl,a,i")))
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162 ]
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163 "rl78_real_insns_ok ()"
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164 "sub\t%0, %2"
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165 [(set (attr "update_Z") (const_string "update_Z"))]
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166 )
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167
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168 (define_insn "*subhi3_real"
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169 [(set (match_operand:HI 0 "nonimmediate_operand" "=A,S")
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170 (minus:HI (match_operand:HI 1 "general_operand" "0,0")
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171 (match_operand:HI 2 "rl78_general_operand" "iBDTWabWh1v,i")))
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172 ]
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173 "rl78_real_insns_ok ()"
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174 "subw\t%0, %2"
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175 [(set (attr "update_Z") (const_string "update_Z"))]
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176 )
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177
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178 (define_insn "*umulhi3_shift_real"
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179 [(set (match_operand:HI 0 "register_operand" "=A,A")
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180 (mult:HI (match_operand:HI 1 "rl78_nonfar_operand" "0,0")
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181 (match_operand:HI 2 "rl78_24_operand" "N,i")))]
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182 "rl78_real_insns_ok ()"
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183 "@
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184 shlw\t%0, 1
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185 shlw\t%0, 2"
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186 )
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187
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188 (define_insn "*umulqihi3_real"
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189 [(set (match_operand:HI 0 "nonimmediate_operand" "=A")
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190 (mult:HI (zero_extend:HI (match_operand:QI 1 "general_operand" "%a"))
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191 (zero_extend:HI (match_operand:QI 2 "general_operand" "x"))))]
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192 "rl78_real_insns_ok ()"
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193 "mulu\t%2"
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194 )
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195
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196 (define_insn "*andqi3_real"
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197 [(set (match_operand:QI 0 "rl78_nonimmediate_operand" "=WsfWsaWhlWab,A,R,vWsa")
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198 (and:QI (match_operand:QI 1 "rl78_general_operand" "%0,0,0,0")
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199 (match_operand:QI 2 "rl78_general_operand" "IBqi,iRvWabWhbWh1Whl,A,i")))
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200 ]
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201 "rl78_real_insns_ok ()"
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202 "@
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203 clr1\t%0.%B2
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204 and\t%0, %2
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205 and\t%0, %2
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206 and\t%0, %2"
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207 [(set_attr "update_Z" "*,update_Z,update_Z,update_Z")]
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208 )
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209
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210 (define_insn "*iorqi3_real"
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211 [(set (match_operand:QI 0 "rl78_nonimmediate_operand" "=WsfWsaWhlWab,A,R,vWsa")
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212 (ior:QI (match_operand:QI 1 "rl78_general_operand" "%0,0,0,0")
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213 (match_operand:QI 2 "rl78_general_operand" "Ibqi,iRvWabWhbWh1Whl,A,i")))
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214 ]
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215 "rl78_real_insns_ok ()"
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216 "@
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217 set1\t%0.%B2
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218 or\t%0, %2
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219 or\t%0, %2
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220 or\t%0, %2"
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221 [(set_attr "update_Z" "*,update_Z,update_Z,update_Z")]
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222 )
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223
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224 (define_insn "*xorqi3_real"
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225 [(set (match_operand:QI 0 "rl78_nonimmediate_operand" "=A,R,vWsa")
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226 (xor:QI (match_operand:QI 1 "rl78_general_operand" "%0,0,0")
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227 (match_operand 2 "rl78_general_operand" "iRvWabWhbWh1Whl,A,i")))
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228 ]
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229 "rl78_real_insns_ok ()"
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230 "xor\t%0, %2"
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231 [(set (attr "update_Z") (const_string "update_Z"))]
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232 )
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233
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234 ;;---------- Shifts ------------------------
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235
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236 (define_insn "*ashlqi3_real"
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237 [(set (match_operand:QI 0 "nonimmediate_operand" "=abc,a,a")
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238 (ashift:QI (match_operand:QI 1 "general_operand" "0,0,0")
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239 (match_operand:QI 2 "general_operand" "Int3,bc,dehl")))
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240 ]
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241 "rl78_real_insns_ok ()"
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242 "@
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243 shl\t%0, %u2
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244 cmp0 %2\; bz $2f\; 1: shl\t%0, 1 \;dec %2 \;bnz $1b\;2:
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245 inc %2\;dec %2\;bz $2f\;1: shl\t%0, 1 \;dec %2 \;bnz $1b\;2:"
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246 [(set_attr "update_Z" "*,clobber,clobber")]
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247 )
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248
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249 (define_insn "*ashlhi3_real"
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250 [(set (match_operand:HI 0 "nonimmediate_operand" "=AB,A,A")
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251 (ashift:HI (match_operand:HI 1 "general_operand" "0,0,0")
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252 (match_operand:QI 2 "general_operand" "P,bc,dehl")))
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253 ]
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254 "rl78_real_insns_ok ()"
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255 "@
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256 shlw\t%0, %u2
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257 cmp0 %2\; bz $2f\; 1: shlw\t%0, 1 \;dec %2 \;bnz $1b\;2:
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258 inc %2\;dec %2\;bz $2f\;1: shlw\t%0, 1 \;dec %2 \;bnz $1b\;2:"
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259 [(set_attr "update_Z" "*,clobber,clobber")]
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260 )
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261
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262 ;;----------
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263
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264 (define_insn "*ashrqi3_real"
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265 [(set (match_operand:QI 0 "nonimmediate_operand" "=abc,a,a")
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266 (ashiftrt:QI (match_operand:QI 1 "general_operand" "0,0,0")
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267 (match_operand:QI 2 "general_operand" "Int3,bc,dehl")))
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268 ]
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269 "rl78_real_insns_ok ()"
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270 "@
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271 sar\t%0, %u2
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272 cmp0 %2\; bz $2f\; 1: sar\t%0, 1 \;dec %2 \;bnz $1b\;2:
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273 inc %2\;dec %2\;bz $2f\;1: sar\t%0, 1\;dec %2 \;bnz $1b\;2:"
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274 [(set_attr "update_Z" "*,clobber,clobber")]
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275 )
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276
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277 (define_insn "*ashrhi3_real"
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278 [(set (match_operand:HI 0 "nonimmediate_operand" "=AB,A,A")
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279 (ashiftrt:HI (match_operand:HI 1 "general_operand" "0,0,0")
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280 (match_operand:QI 2 "general_operand" "P,bc,dehl")))
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281 ]
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282 "rl78_real_insns_ok ()"
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283 "@
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284 sarw\t%0, %u2
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285 cmp0 %2\; bz $2f\; 1: sarw\t%0, 1 \;dec %2 \;bnz $1b\;2:
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286 inc %2\;dec %2\;bz $2f\;1: sarw\t%0, 1\;dec %2\;bnz $1b\;2:"
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287 [(set_attr "update_Z" "*,clobber,clobber")]
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288 )
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289
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290 ;;----------
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291
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292 (define_insn "*lshrqi3_real"
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293 [(set (match_operand:QI 0 "nonimmediate_operand" "=abc,a,a")
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294 (lshiftrt:QI (match_operand:QI 1 "general_operand" "0,0,0")
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295 (match_operand:QI 2 "general_operand" "Int3,bc,dehl")))
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296 ]
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297 "rl78_real_insns_ok ()"
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298 "@
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299 shr\t%0, %u2
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300 cmp0 %2\; bz $2f\; 1: shr\t%0, 1 \;dec %2 \;bnz $1b\;2:
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301 inc %2\;dec %2\;bz $2f\;1: shr\t%0, 1\;dec %2\;bnz $1b\;2:"
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302 [(set_attr "update_Z" "*,clobber,clobber")]
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303 )
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304
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305 (define_insn "*lshrhi3_real"
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306 [(set (match_operand:HI 0 "nonimmediate_operand" "=AB,A,A")
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307 (lshiftrt:HI (match_operand:HI 1 "general_operand" "0,0,0")
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308 (match_operand:QI 2 "general_operand" "P,bc,dehl")))
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309 ]
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310 "rl78_real_insns_ok ()"
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311 "@
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312 shrw\t%0, %u2
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313 cmp0 %2\; bz $2f\; 1: shrw\t%0, 1 \;dec %2 \;bnz $1b\;2:
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314 inc %2\;dec %2\;bz $2f\;1: shrw\t%0, 1\;dec %2\;bnz $1b\;2:"
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315 [(set_attr "update_Z" "*,clobber,clobber")]
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316 )
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317
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318 ;;---------- Branching ------------------------
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319
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320 (define_insn "*indirect_jump_real"
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321 [(set (pc)
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322 (match_operand:HI 0 "nonimmediate_operand" "A"))]
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323 "rl78_real_insns_ok ()"
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324 "br\t%0"
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325 )
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326
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327 (define_insn "jump"
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328 [(set (pc)
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329 (label_ref (match_operand 0 "" "")))]
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330 ""
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331 ;; $rel8, $!rel16, !abs16, !!abs20
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332 "br\t!!%0"
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333 )
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334
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335 (define_insn "*call_real"
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336 [(call (match_operand:HI 0 "memory_operand" "Wab,Wca")
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337 (match_operand 1 "" ""))]
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338 "rl78_real_insns_ok ()"
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339 "@
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340 call\t!!%A0
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341 call\t%A0"
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342 [(set (attr "update_Z") (const_string "clobber"))]
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343 )
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344
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345 ;; Peephole to match:
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346 ;;
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347 ;; (set (reg1) (reg2))
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348 ;; (call (mem (reg1)))
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349 ;;
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350 ;; and replace it with:
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351 ;;
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352 ;; (call (mem (reg2)))
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353
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354 (define_peephole2
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355 [(set (match_operand:HI 0 "register_operand") (match_operand:HI 1 "register_operand"))
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356 (call (mem:HI (match_dup 0))(const_int 0))
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357 ]
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358 "peep2_regno_dead_p (2, REGNO (operands[0]))
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359 && REGNO (operands[1]) < 8"
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360 [(call (mem:HI (match_dup 1))(const_int 0))
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361 ]
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|
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362 )
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363
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364 (define_insn "*call_value_real"
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365 [(set (match_operand 0 "register_operand" "=v,v")
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366 (call (match_operand:HI 1 "memory_operand" "Wab,Wca")
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367 (match_operand 2 "" "")))]
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368 "rl78_real_insns_ok ()"
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369 "@
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370 call\t!!%A1
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371 call\t%A1"
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372 [(set (attr "update_Z") (const_string "clobber"))]
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373 )
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374
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375 ;; Peephole to match:
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376 ;;
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377 ;; (set (reg1) (reg2))
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378 ;; (set (reg3) (call (mem (reg1))))
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379 ;;
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380 ;; and replace it with:
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381 ;;
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382 ;; (set (reg3) (call (mem (reg2))))
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383
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384 (define_peephole2
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385 [(set (match_operand:HI 0 "register_operand") (match_operand:HI 1 "register_operand"))
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386 (set (match_operand:HI 2 "register_operand") (call (mem:HI (match_dup 0))(const_int 0)))
|
|
|
387 ]
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388 "peep2_regno_dead_p (2, REGNO (operands[0]))
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389 && REGNO (operands[1]) < 8"
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390 [(set (match_dup 2) (call (mem:HI (match_dup 1))(const_int 0)))
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|
|
391 ]
|
|
|
392 )
|
|
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393
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|
394 (define_insn "*cbranchqi4_real_signed"
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395 [(set (pc) (if_then_else
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396 (match_operator 0 "rl78_cmp_operator_signed"
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|
|
397 [(match_operand:QI 1 "general_operand" "A,A,A,A,Wsa")
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|
|
398 (match_operand:QI 2 "general_operand" "M,ISqi,i,v,i")])
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|
|
399 (label_ref (match_operand 3 "" ""))
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|
|
400 (pc)))]
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|
401 "rl78_real_insns_ok ()"
|
|
|
402 {
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|
|
403 gcc_assert (GET_CODE (operands[0]) != EQ && GET_CODE (operands[0]) != NE);
|
|
|
404
|
|
|
405 switch (which_alternative)
|
|
|
406 {
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|
|
407 case 0: return "cmp0\t%1\; xor1\tCY, %1.7\; sk%C0\; br\t!!%3";
|
|
|
408 case 1: return "cmp\t%1, %2\; xor1\tCY, %1.7\; not1\tCY\; sk%C0\; br\t!!%3";
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|
|
409 case 4:
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|
|
410 case 2: return "cmp\t%1, %2\; xor1\tCY, %1.7\; sk%C0\; br\t!!%3";
|
|
|
411 case 3: return "cmp\t%1, %2\; xor1\tCY, %1.7\; xor1\tCY, %2.7\; sk%C0\; br\t!!%3";
|
|
|
412 default: gcc_unreachable ();
|
|
|
413 }
|
|
|
414 }
|
|
|
415 [(set (attr "update_Z") (const_string "clobber"))] ;; FIXME: flags are set based on %1 vs %2
|
|
|
416 )
|
|
|
417
|
|
|
418 (define_insn "*cbranchqi4_real"
|
|
|
419 [(set (pc) (if_then_else
|
|
|
420 (match_operator 0 "rl78_cmp_operator_real"
|
|
|
421 [(match_operand:QI 1 "rl78_general_operand" "Wabvaxbc,a, vWsaWab,bcdehl")
|
|
|
422 (match_operand:QI 2 "rl78_general_operand" "M, iRvWabWhlWh1Whb,i,a")])
|
|
|
423 (label_ref (match_operand 3 "" ""))
|
|
|
424 (pc)))]
|
|
|
425 "rl78_real_insns_ok ()"
|
|
|
426 {
|
|
|
427 if (which_alternative == 0)
|
|
|
428 {
|
|
|
429 if (rl78_flags_already_set (operands[0], operands[1]))
|
|
|
430 return "sk%C0\; br\t!!%3\; # zero-comparison eliminated";
|
|
|
431 else
|
|
|
432 return "cmp0\t%1\; sk%C0\; br\t!!%3";
|
|
|
433 }
|
|
|
434 return "cmp\t%1, %2\; sk%C0\; br\t!!%3";
|
|
|
435 }
|
|
|
436 [(set (attr "update_Z") (const_string "clobber"))] ;; FIXME: alt 0: flags are set based on %1 vs %2
|
|
|
437 )
|
|
|
438
|
|
|
439 (define_insn "*cbranchhi4_real_signed"
|
|
|
440 [(set (pc) (if_then_else
|
|
|
441 (match_operator 0 "rl78_cmp_operator_signed"
|
|
|
442 [(match_operand:HI 1 "general_operand" "A,A,A,vR")
|
|
|
443 (match_operand:HI 2 "general_operand" "IShi,i,v,1")])
|
|
|
444 (label_ref (match_operand 3))
|
|
|
445 (pc)))]
|
|
|
446 "rl78_real_insns_ok ()"
|
|
|
447 "@
|
|
|
448 cmpw\t%1, %2\; xor1\tCY, %Q1.7\; not1\tCY\; sk%C0\; br\t!!%3
|
|
|
449 cmpw\t%1, %2\; xor1\tCY, %Q1.7\; sk%C0\; br\t!!%3
|
|
|
450 cmpw\t%1, %2\; xor1\tCY, %Q1.7\; xor1\tCY, %Q2.7\; sk%C0\; br\t!!%3
|
|
|
451 %z0\t!!%3"
|
|
|
452 [(set_attr "update_Z" "clobber,clobber,clobber,*")]
|
|
|
453 )
|
|
|
454
|
|
|
455 (define_insn "cbranchhi4_real"
|
|
|
456 [(set (pc) (if_then_else
|
|
|
457 (match_operator 0 "rl78_cmp_operator_real"
|
|
|
458 [(match_operand:HI 1 "general_operand" "A,A,vR")
|
|
|
459 (match_operand:HI 2 "rl78_general_operand" "M,iBDTvWabWhlWh1,1")])
|
|
|
460 (label_ref (match_operand 3 "" ""))
|
|
|
461 (pc)))]
|
|
|
462 "rl78_real_insns_ok ()"
|
|
|
463 {
|
|
|
464 switch (which_alternative)
|
|
|
465 {
|
|
|
466 case 0:
|
|
|
467 if (rl78_flags_already_set (operands[0], operands[1]))
|
|
|
468 return "sk%C0\; br\t!!%3\; # cmpw eliminated";
|
|
|
469 /* else fall through. */
|
|
|
470 case 1:
|
|
|
471 return "cmpw\t%1, %2\; sk%C0\; br\t!!%3";
|
|
|
472 case 2:
|
|
|
473 return "%z0\t!!%3";
|
|
|
474 default:
|
|
|
475 gcc_unreachable ();
|
|
|
476 }
|
|
|
477 }
|
|
|
478 [(set (attr "update_Z") (const_string "clobber"))] ;; FIXME: Z might be set based on %1 vs %2
|
|
|
479 )
|
|
|
480
|
|
|
481 (define_insn "cbranchhi4_real_inverted"
|
|
|
482 [(set (pc) (if_then_else
|
|
|
483 (match_operator 0 "rl78_cmp_operator_real"
|
|
|
484 [(match_operand:HI 1 "general_operand" "A,A")
|
|
|
485 (match_operand:HI 2 "rl78_general_operand" "M,iBDTvWabWhlWh1")])
|
|
|
486 (pc)
|
|
|
487 (label_ref (match_operand 3 "" ""))))]
|
|
|
488 "rl78_real_insns_ok ()"
|
|
|
489 {
|
|
|
490 if (which_alternative == 0 && rl78_flags_already_set (operands[0], operands[1]))
|
|
|
491 return "sk%C0\; br\t!!%3\; # inverted cmpw eliminated";
|
|
|
492 else
|
|
|
493 return "cmpw\t%1, %2\; sk%C0\; br\t!!%3";
|
|
|
494 }
|
|
|
495 [(set (attr "update_Z") (const_string "clobber"))] ;; FIXME: flags are set based on %1 vs %2
|
|
|
496 )
|
|
|
497
|
|
|
498 (define_insn "*cbranchsi4_real_lt"
|
|
|
499 [(set (pc) (if_then_else
|
|
|
500 (lt (match_operand:SI 0 "rl78_general_operand" "U,vWabWhlWh1")
|
|
|
501 (const_int 0))
|
|
|
502 (label_ref (match_operand 1 "" ""))
|
|
|
503 (pc)))
|
|
|
504 (clobber (reg:HI AX_REG))
|
|
|
505 ]
|
|
|
506 "rl78_real_insns_ok ()"
|
|
|
507 "@
|
|
|
508 mov\ta, %E0\; mov1\tCY, a.7\; sknc\; br\t!!%1
|
|
|
509 mov1\tCY, %E0.7\; sknc\; br\t!!%1"
|
|
|
510 )
|
|
|
511
|
|
|
512 (define_insn "*cbranchsi4_real_ge"
|
|
|
513 [(set (pc) (if_then_else
|
|
|
514 (ge (match_operand:SI 0 "rl78_general_operand" "U,vWabWhlWh1")
|
|
|
515 (const_int 0))
|
|
|
516 (label_ref (match_operand 1 "" ""))
|
|
|
517 (pc)))
|
|
|
518 (clobber (reg:HI AX_REG))
|
|
|
519 ]
|
|
|
520 "rl78_real_insns_ok ()"
|
|
|
521 "@
|
|
|
522 mov\ta, %E0\; mov1\tCY, a.7\; skc\; br\t!!%1
|
|
|
523 mov1\tCY, %E0.7\; skc\; br\t!!%1"
|
|
|
524 )
|
|
|
525
|
|
|
526 (define_insn "*cbranchsi4_real_signed"
|
|
|
527 [(set (pc) (if_then_else
|
|
|
528 (match_operator 0 "rl78_cmp_operator_signed"
|
|
|
529 [(match_operand:SI 1 "general_operand" "vU,vU,vU,i,i")
|
|
|
530 (match_operand:SI 2 "nonmemory_operand" "ISsi,i,v,S,v")])
|
|
|
531 (label_ref (match_operand 3 "" ""))
|
|
|
532 (pc)))
|
|
|
533 (clobber (reg:HI AX_REG))
|
|
|
534 ]
|
|
|
535 "rl78_real_insns_ok ()"
|
|
|
536 "@
|
|
|
537 movw\tax, %H1\; cmpw\tax, %H2\; xor1\tCY, a.7\; not1\tCY\; movw\tax, %h1\; sknz\; cmpw\tax, %h2\; sk%C0\; br\t!!%3
|
|
|
538 movw\tax, %H1\; cmpw\tax, %H2\; xor1\tCY, a.7\; movw\tax, %h1\; sknz\; cmpw\tax, %h2\; sk%C0\; br\t!!%3
|
|
|
539 movw\tax, %H1\; cmpw\tax, %H2\; xor1\tCY, a.7\; xor1\tCY, %E2.7\; movw\tax, %h1\; sknz\; cmpw\tax, %h2\; sk%C0\; br\t!!%3
|
|
|
540 movw\tax, %H1\; cmpw\tax, %H2\; xor1\tCY, a.7\; not1\tCY\; movw\tax, %h1\; sknz\; cmpw\tax, %h2\; sk%0\; br\t!!%3
|
|
|
541 movw\tax, %H1\; cmpw\tax, %H2\; xor1\tCY, a.7\; movw\tax, %h1\; sknz\; cmpw\tax, %h2\; sk%0\; br\t!!%3"
|
|
|
542 [(set (attr "update_Z") (const_string "clobber"))]
|
|
|
543 )
|
|
|
544
|
|
|
545 (define_insn "*cbranchsi4_real"
|
|
|
546 [(set (pc) (if_then_else
|
|
|
547 (match_operator 0 "rl78_cmp_operator_real"
|
|
|
548 [(match_operand:SI 1 "general_operand" "vUi")
|
|
|
549 (match_operand:SI 2 "general_operand" "iWhlWh1v")])
|
|
|
550 (label_ref (match_operand 3 "" ""))
|
|
|
551 (pc)))
|
|
|
552 (clobber (reg:HI AX_REG))
|
|
|
553 ]
|
|
|
554 "rl78_real_insns_ok ()"
|
|
|
555 "movw\tax, %H1\; cmpw\tax, %H2\; movw\tax, %h1\; sknz\; cmpw\tax, %h2\; sk%C0\; br\t!!%3"
|
|
|
556 [(set (attr "update_Z") (const_string "clobber"))]
|
|
|
557 )
|
|
|
558
|
|
|
559 ;; Peephole to match:
|
|
|
560 ;;
|
|
|
561 ;; (set (mem (sp)) (ax))
|
|
|
562 ;; (set (ax) (mem (sp)))
|
|
|
563 ;; or:
|
|
|
564 ;; (set (mem (plus (sp) (const)) (ax))
|
|
|
565 ;; (set (ax) (mem (plus (sp) (const))))
|
|
|
566 ;;
|
|
|
567 ;; which can be generated as the last instruction of the conversion
|
|
|
568 ;; of one virtual insn into a real insn and the first instruction of
|
|
|
569 ;; the conversion of the following virtual insn.
|
|
|
570
|
|
|
571 (define_peephole2
|
|
|
572 [(set (match_operand:HI 0 "rl78_stack_based_mem")
|
|
|
573 (reg:HI AX_REG))
|
|
|
574 (set (reg:HI AX_REG)
|
|
|
575 (match_dup 0))]
|
|
|
576 ""
|
|
|
577 [(set (match_dup 0) (reg:HI AX_REG))]
|
|
|
578 )
|
|
|
579
|
|
|
580 ;; Bit test and branch insns.
|
|
|
581
|
|
|
582 ;; NOTE: These patterns will work for bits in other places, not just A.
|
|
|
583
|
|
|
584 (define_insn "bf"
|
|
|
585 [(set (pc)
|
|
|
586 (if_then_else (eq (and (reg:QI A_REG)
|
|
|
587 (match_operand 0 "immediate_operand" "n"))
|
|
|
588 (const_int 0))
|
|
|
589 (label_ref (match_operand 1 "" ""))
|
|
|
590 (pc)))]
|
|
|
591 ""
|
|
|
592 "bt\tA.%B0, $1f\n\tbr !!%1\n\t1:"
|
|
|
593 [(set (attr "update_Z") (const_string "clobber"))]
|
|
|
594 )
|
|
|
595
|
|
|
596 (define_insn "bt"
|
|
|
597 [(set (pc)
|
|
|
598 (if_then_else (ne (and (reg:QI A_REG)
|
|
|
599 (match_operand 0 "immediate_operand" "n"))
|
|
|
600 (const_int 0))
|
|
|
601 (label_ref (match_operand 1 "" ""))
|
|
|
602 (pc)))]
|
|
|
603 ""
|
|
|
604 "bf\tA.%B0, $1f\n\tbr !!%1\n\t1:"
|
|
|
605 [(set (attr "update_Z") (const_string "clobber"))]
|
|
|
606 )
|
|
|
607
|
|
|
608 ;; NOTE: These peepholes are fragile. They rely upon GCC generating
|
|
|
609 ;; a specific sequence on insns, based upon examination of test code.
|
|
|
610 ;; Improvements to GCC or using code other than the test code can result
|
|
|
611 ;; in the peephole not matching and the optimization being missed.
|
|
|
612
|
|
|
613 (define_peephole2
|
|
|
614 [(set (match_operand:QI 0 "register_operand") (reg:QI A_REG))
|
|
|
615 (set (match_dup 0) (and:QI (match_dup 0) (match_operand 1 "immediate_operand")))
|
|
|
616 (set (pc) (if_then_else (eq (match_dup 0) (const_int 0))
|
|
|
617 (label_ref (match_operand 2 ""))
|
|
|
618 (pc)))]
|
|
|
619 "peep2_regno_dead_p (3, REGNO (operands[0]))
|
|
|
620 && exact_log2 (INTVAL (operands[1])) >= 0"
|
|
|
621 [(set (pc) (if_then_else (eq (and (reg:QI A_REG) (match_dup 1)) (const_int 0))
|
|
|
622 (label_ref (match_dup 2))
|
|
|
623 (pc)))]
|
|
|
624 )
|
|
|
625
|
|
|
626 (define_peephole2
|
|
|
627 [(set (match_operand:QI 0 "register_operand") (reg:QI A_REG))
|
|
|
628 (set (match_dup 0) (and:QI (match_dup 0) (match_operand 1 "immediate_operand")))
|
|
|
629 (set (pc) (if_then_else (ne (match_dup 0) (const_int 0))
|
|
|
630 (label_ref (match_operand 2 ""))
|
|
|
631 (pc)))]
|
|
|
632 "peep2_regno_dead_p (3, REGNO (operands[0]))
|
|
|
633 && exact_log2 (INTVAL (operands[1])) >= 0"
|
|
|
634 [(set (pc) (if_then_else (ne (and (reg:QI A_REG) (match_dup 1)) (const_int 0))
|
|
|
635 (label_ref (match_dup 2))
|
|
|
636 (pc)))]
|
|
|
637 )
|
|
|
638
|
|
|
639 ;; Eliminate needless register copies.
|
|
|
640 (define_peephole2
|
|
|
641 [(set (match_operand:HI 0 "register_operand") (match_operand:HI 1 "register_operand"))
|
|
|
642 (set (match_operand:HI 2 "register_operand") (match_dup 0))]
|
|
|
643 "peep2_regno_dead_p (2, REGNO (operands[0]))
|
|
|
644 && (REGNO (operands[1]) < 8 || REGNO (operands[2]) < 8)"
|
|
|
645 [(set (match_dup 2) (match_dup 1))]
|
|
|
646 )
|
|
|
647
|
|
|
648 ;; Eliminate needless register copying when performing bit manipulations.
|
|
|
649 (define_peephole2
|
|
|
650 [(set (match_operand:QI 0 "register_operand") (reg:QI A_REG))
|
|
|
651 (set (match_dup 0) (ior:QI (match_dup 0) (match_operand 1 "immediate_operand")))
|
|
|
652 (set (reg:QI A_REG) (match_dup 0))]
|
|
|
653 "peep2_regno_dead_p (3, REGNO (operands[0]))"
|
|
|
654 [(set (reg:QI A_REG) (ior:QI (reg:QI A_REG) (match_dup 1)))]
|
|
|
655 )
|
|
|
656
|
|
|
657 (define_peephole2
|
|
|
658 [(set (match_operand:QI 0 "register_operand") (reg:QI A_REG))
|
|
|
659 (set (match_dup 0) (xor:QI (match_dup 0) (match_operand 1 "immediate_operand")))
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660 (set (reg:QI A_REG) (match_dup 0))]
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661 "peep2_regno_dead_p (3, REGNO (operands[0]))"
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662 [(set (reg:QI A_REG) (xor:QI (reg:QI A_REG) (match_dup 1)))]
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663 )
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664
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665 (define_peephole2
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666 [(set (match_operand:QI 0 "register_operand") (reg:QI A_REG))
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667 (set (match_dup 0) (and:QI (match_dup 0) (match_operand 1 "immediate_operand")))
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668 (set (reg:QI A_REG) (match_dup 0))]
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669 "peep2_regno_dead_p (3, REGNO (operands[0]))"
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670 [(set (reg:QI A_REG) (and:QI (reg:QI A_REG) (match_dup 1)))]
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671 )
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672
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673 (define_insn "*negandhi3_real"
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674 [(set (match_operand:HI 0 "register_operand" "=A")
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675 (and:HI (neg:HI (match_operand:HI 1 "register_operand" "0"))
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676 (match_operand:HI 2 "immediate_operand" "n")))
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677 ]
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678 "rl78_real_insns_ok ()"
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679 "xor a, #0xff @ xch a, x @ xor a, #0xff @ xch a, x @ addw ax, #1 @ and a, %Q2 @ xch a, x @ and a, %q2 @ xch a, x"
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680 [(set (attr "update_Z") (const_string "clobber"))]
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681 )
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