111
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1 ;; Scheduling description for IBM POWER9 processor.
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2 ;; Copyright (C) 2016-2017 Free Software Foundation, Inc.
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3 ;;
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4 ;; Contributed by Pat Haugen (pthaugen@us.ibm.com).
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5
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6 ;; This file is part of GCC.
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7 ;;
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8 ;; GCC is free software; you can redistribute it and/or modify it
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9 ;; under the terms of the GNU General Public License as published
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10 ;; by the Free Software Foundation; either version 3, or (at your
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11 ;; option) any later version.
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12 ;;
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13 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
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14 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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15 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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16 ;; License for more details.
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17 ;;
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18 ;; You should have received a copy of the GNU General Public License
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19 ;; along with GCC; see the file COPYING3. If not see
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20 ;; <http://www.gnu.org/licenses/>.
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21
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22 (define_automaton "power9dsp,power9lsu,power9vsu,power9misc")
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23
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24 (define_cpu_unit "lsu0_power9,lsu1_power9,lsu2_power9,lsu3_power9" "power9lsu")
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25 (define_cpu_unit "vsu0_power9,vsu1_power9,vsu2_power9,vsu3_power9" "power9vsu")
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26 ; Two vector permute units, part of vsu
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27 (define_cpu_unit "prm0_power9,prm1_power9" "power9vsu")
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28 ; Two fixed point divide units, not pipelined
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29 (define_cpu_unit "fx_div0_power9,fx_div1_power9" "power9misc")
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30 (define_cpu_unit "bru_power9,cryptu_power9,dfu_power9" "power9misc")
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31
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32 (define_cpu_unit "x0_power9,x1_power9,xa0_power9,xa1_power9,
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33 x2_power9,x3_power9,xb0_power9,xb1_power9,
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34 br0_power9,br1_power9" "power9dsp")
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35
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36
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37 ; Dispatch port reservations
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38 ;
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39 ; Power9 can dispatch a maximum of 6 iops per cycle with the following
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40 ; general restrictions (other restrictions also apply):
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41 ; 1) At most 2 iops per execution slice
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42 ; 2) At most 2 iops to the branch unit
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43 ; Note that insn position in a dispatch group of 6 insns does not infer which
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44 ; execution slice the insn is routed to. The units are used to infer the
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45 ; conflicts that exist (i.e. an 'even' requirement will preclude dispatch
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46 ; with 2 insns with 'superslice' requirement).
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47
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48 ; The xa0/xa1 units really represent the 3rd dispatch port for a superslice but
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49 ; are listed as separate units to allow those insns that preclude its use to
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50 ; still be scheduled two to a superslice while reserving the 3rd slot. The
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51 ; same applies for xb0/xb1.
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52 (define_reservation "DU_xa_power9" "xa0_power9+xa1_power9")
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53 (define_reservation "DU_xb_power9" "xb0_power9+xb1_power9")
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54
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55 ; Any execution slice dispatch
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56 (define_reservation "DU_any_power9"
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57 "x0_power9|x1_power9|DU_xa_power9|x2_power9|x3_power9|
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58 DU_xb_power9")
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59
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60 ; Even slice, actually takes even/odd slots
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61 (define_reservation "DU_even_power9" "x0_power9+x1_power9|x2_power9+x3_power9")
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62
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63 ; Slice plus 3rd slot
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64 (define_reservation "DU_slice_3_power9"
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65 "x0_power9+xa0_power9|x1_power9+xa1_power9|
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66 x2_power9+xb0_power9|x3_power9+xb1_power9")
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67
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68 ; Superslice
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69 (define_reservation "DU_super_power9"
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70 "x0_power9+x1_power9|x2_power9+x3_power9")
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71
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72 ; 2-way cracked
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73 (define_reservation "DU_C2_power9" "x0_power9+x1_power9|
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74 x1_power9+DU_xa_power9|
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75 x1_power9+x2_power9|
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76 DU_xa_power9+x2_power9|
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77 x2_power9+x3_power9|
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78 x3_power9+DU_xb_power9")
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79
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80 ; 2-way cracked plus 3rd slot
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81 (define_reservation "DU_C2_3_power9" "x0_power9+x1_power9+xa0_power9|
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82 x1_power9+x2_power9+xa0_power9|
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83 x1_power9+x2_power9+xb0_power9|
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84 x2_power9+x3_power9+xb0_power9")
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85
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86 ; 3-way cracked (consumes whole decode/dispatch cycle)
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87 (define_reservation "DU_C3_power9"
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88 "x0_power9+x1_power9+xa0_power9+xa1_power9+x2_power9+
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89 x3_power9+xb0_power9+xb1_power9+br0_power9+br1_power9")
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90
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91 ; Branch ports
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92 (define_reservation "DU_branch_power9" "br0_power9|br1_power9")
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93
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94
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95 ; Execution unit reservations
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96 (define_reservation "LSU_power9"
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97 "lsu0_power9|lsu1_power9|lsu2_power9|lsu3_power9")
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98
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99 (define_reservation "LSU_pair_power9"
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100 "lsu0_power9+lsu1_power9|lsu1_power9+lsu2_power9|
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101 lsu2_power9+lsu3_power9|lsu3_power9+lsu0_power9")
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102
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103 (define_reservation "VSU_power9"
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104 "vsu0_power9|vsu1_power9|vsu2_power9|vsu3_power9")
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105
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106 (define_reservation "VSU_super_power9"
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107 "vsu0_power9+vsu1_power9|vsu2_power9+vsu3_power9")
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108
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109 (define_reservation "VSU_PRM_power9" "prm0_power9|prm1_power9")
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110
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111
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112 ; LS Unit
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113 (define_insn_reservation "power9-load" 4
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114 (and (eq_attr "type" "load")
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115 (eq_attr "sign_extend" "no")
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116 (eq_attr "update" "no")
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117 (eq_attr "cpu" "power9"))
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118 "DU_any_power9,LSU_power9")
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119
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120 (define_insn_reservation "power9-load-update" 4
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121 (and (eq_attr "type" "load")
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122 (eq_attr "sign_extend" "no")
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123 (eq_attr "update" "yes")
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124 (eq_attr "cpu" "power9"))
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125 "DU_C2_power9,LSU_power9+VSU_power9")
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126
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127 (define_insn_reservation "power9-load-ext" 6
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128 (and (eq_attr "type" "load")
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129 (eq_attr "sign_extend" "yes")
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130 (eq_attr "update" "no")
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131 (eq_attr "cpu" "power9"))
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132 "DU_C2_power9,LSU_power9")
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133
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134 (define_insn_reservation "power9-load-ext-update" 6
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135 (and (eq_attr "type" "load")
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136 (eq_attr "sign_extend" "yes")
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137 (eq_attr "update" "yes")
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138 (eq_attr "cpu" "power9"))
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139 "DU_C3_power9,LSU_power9+VSU_power9")
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140
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141 (define_insn_reservation "power9-fpload-double" 4
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142 (and (eq_attr "type" "fpload")
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143 (eq_attr "update" "no")
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144 (eq_attr "size" "64")
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145 (eq_attr "cpu" "power9"))
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146 "DU_slice_3_power9,LSU_power9")
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147
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148 (define_insn_reservation "power9-fpload-update-double" 4
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149 (and (eq_attr "type" "fpload")
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150 (eq_attr "update" "yes")
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151 (eq_attr "size" "64")
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152 (eq_attr "cpu" "power9"))
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153 "DU_C2_3_power9,LSU_power9+VSU_power9")
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154
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155 ; SFmode loads are cracked and have additional 2 cycles over DFmode
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156 (define_insn_reservation "power9-fpload-single" 6
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157 (and (eq_attr "type" "fpload")
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158 (eq_attr "update" "no")
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159 (eq_attr "size" "32")
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160 (eq_attr "cpu" "power9"))
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161 "DU_C2_3_power9,LSU_power9")
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162
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163 (define_insn_reservation "power9-fpload-update-single" 6
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164 (and (eq_attr "type" "fpload")
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165 (eq_attr "update" "yes")
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166 (eq_attr "size" "32")
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167 (eq_attr "cpu" "power9"))
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168 "DU_C3_power9,LSU_power9+VSU_power9")
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169
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170 (define_insn_reservation "power9-vecload" 5
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171 (and (eq_attr "type" "vecload")
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172 (eq_attr "cpu" "power9"))
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173 "DU_any_power9,LSU_pair_power9")
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174
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175 ; Store data can issue 2 cycles after AGEN issue, 3 cycles for vector store
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176 (define_insn_reservation "power9-store" 0
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177 (and (eq_attr "type" "store")
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178 (eq_attr "update" "no")
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179 (eq_attr "indexed" "no")
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180 (eq_attr "cpu" "power9"))
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181 "DU_slice_3_power9,LSU_power9")
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182
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183 (define_insn_reservation "power9-store-indexed" 0
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184 (and (eq_attr "type" "store")
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185 (eq_attr "update" "no")
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186 (eq_attr "indexed" "yes")
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187 (eq_attr "cpu" "power9"))
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188 "DU_slice_3_power9,LSU_power9")
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189
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190 ; Update forms have 2 cycle latency for updated addr reg
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191 (define_insn_reservation "power9-store-update" 2
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192 (and (eq_attr "type" "store")
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193 (eq_attr "update" "yes")
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194 (eq_attr "indexed" "no")
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195 (eq_attr "cpu" "power9"))
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196 "DU_C2_3_power9,LSU_power9+VSU_power9")
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197
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198 ; Update forms have 2 cycle latency for updated addr reg
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199 (define_insn_reservation "power9-store-update-indexed" 2
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200 (and (eq_attr "type" "store")
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201 (eq_attr "update" "yes")
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202 (eq_attr "indexed" "yes")
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203 (eq_attr "cpu" "power9"))
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204 "DU_C2_3_power9,LSU_power9+VSU_power9")
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205
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206 (define_insn_reservation "power9-fpstore" 0
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207 (and (eq_attr "type" "fpstore")
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208 (eq_attr "update" "no")
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209 (eq_attr "cpu" "power9"))
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210 "DU_slice_3_power9,LSU_power9")
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211
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212 ; Update forms have 2 cycle latency for updated addr reg
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213 (define_insn_reservation "power9-fpstore-update" 2
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214 (and (eq_attr "type" "fpstore")
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215 (eq_attr "update" "yes")
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216 (eq_attr "cpu" "power9"))
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217 "DU_C2_3_power9,LSU_power9+VSU_power9")
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218
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219 (define_insn_reservation "power9-vecstore" 0
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220 (and (eq_attr "type" "vecstore")
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221 (eq_attr "cpu" "power9"))
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222 "DU_super_power9,LSU_pair_power9")
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223
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224 (define_insn_reservation "power9-larx" 4
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225 (and (eq_attr "type" "load_l")
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226 (eq_attr "cpu" "power9"))
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227 "DU_any_power9,LSU_power9")
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228
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229 (define_insn_reservation "power9-stcx" 2
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230 (and (eq_attr "type" "store_c")
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231 (eq_attr "cpu" "power9"))
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232 "DU_C2_3_power9,LSU_power9+VSU_power9")
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233
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234 (define_insn_reservation "power9-sync" 4
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235 (and (eq_attr "type" "sync,isync")
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236 (eq_attr "cpu" "power9"))
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237 "DU_any_power9,LSU_power9")
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238
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239
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240 ; VSU Execution Unit
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241
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242 ; Fixed point ops
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243
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244 ; Most ALU insns are simple 2 cycle, including record form
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245 (define_insn_reservation "power9-alu" 2
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246 (and (ior (eq_attr "type" "add,exts,integer,logical,isel")
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247 (and (eq_attr "type" "insert,shift")
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248 (eq_attr "dot" "no")))
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249 (eq_attr "cpu" "power9"))
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250 "DU_any_power9,VSU_power9")
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251 ; 5 cycle CR latency
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252 (define_bypass 5 "power9-alu"
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253 "power9-crlogical,power9-mfcr,power9-mfcrf")
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254
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255 ; Record form rotate/shift are cracked
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256 (define_insn_reservation "power9-cracked-alu" 2
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257 (and (eq_attr "type" "insert,shift")
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258 (eq_attr "dot" "yes")
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259 (eq_attr "cpu" "power9"))
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260 "DU_C2_power9,VSU_power9")
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261 ; 7 cycle CR latency
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262 (define_bypass 7 "power9-cracked-alu"
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263 "power9-crlogical,power9-mfcr,power9-mfcrf")
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264
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265 (define_insn_reservation "power9-alu2" 3
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266 (and (eq_attr "type" "cntlz,popcnt,trap")
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267 (eq_attr "cpu" "power9"))
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268 "DU_any_power9,VSU_power9")
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269 ; 6 cycle CR latency
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270 (define_bypass 6 "power9-alu2"
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271 "power9-crlogical,power9-mfcr,power9-mfcrf")
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272
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273 (define_insn_reservation "power9-cmp" 2
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274 (and (eq_attr "type" "cmp")
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275 (eq_attr "cpu" "power9"))
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276 "DU_any_power9,VSU_power9")
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277
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278
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279 ; Treat 'two' and 'three' types as 2 or 3 way cracked
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280 (define_insn_reservation "power9-two" 4
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281 (and (eq_attr "type" "two")
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282 (eq_attr "cpu" "power9"))
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283 "DU_C2_power9,VSU_power9")
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284
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285 (define_insn_reservation "power9-three" 6
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286 (and (eq_attr "type" "three")
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287 (eq_attr "cpu" "power9"))
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288 "DU_C3_power9,VSU_power9")
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289
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290 (define_insn_reservation "power9-mul" 5
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291 (and (eq_attr "type" "mul")
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292 (eq_attr "dot" "no")
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293 (eq_attr "cpu" "power9"))
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294 "DU_any_power9,VSU_power9")
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295
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296 (define_insn_reservation "power9-mul-compare" 5
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297 (and (eq_attr "type" "mul")
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298 (eq_attr "dot" "yes")
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299 (eq_attr "cpu" "power9"))
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300 "DU_C2_power9,VSU_power9")
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301 ; 10 cycle CR latency
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302 (define_bypass 10 "power9-mul-compare"
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303 "power9-crlogical,power9-mfcr,power9-mfcrf")
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304
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305 ; Fixed point divides reserve the divide units for a minimum of 8 cycles
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306 (define_insn_reservation "power9-idiv" 16
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307 (and (eq_attr "type" "div")
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308 (eq_attr "size" "32")
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309 (eq_attr "cpu" "power9"))
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310 "DU_even_power9,fx_div0_power9*8|fx_div1_power9*8")
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311
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312 (define_insn_reservation "power9-ldiv" 24
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313 (and (eq_attr "type" "div")
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314 (eq_attr "size" "64")
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315 (eq_attr "cpu" "power9"))
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316 "DU_even_power9,fx_div0_power9*8|fx_div1_power9*8")
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317
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318 (define_insn_reservation "power9-crlogical" 2
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319 (and (eq_attr "type" "cr_logical,delayed_cr")
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320 (eq_attr "cpu" "power9"))
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321 "DU_any_power9,VSU_power9")
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322
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323 (define_insn_reservation "power9-mfcrf" 2
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324 (and (eq_attr "type" "mfcrf")
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325 (eq_attr "cpu" "power9"))
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326 "DU_any_power9,VSU_power9")
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327
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328 (define_insn_reservation "power9-mfcr" 6
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329 (and (eq_attr "type" "mfcr")
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330 (eq_attr "cpu" "power9"))
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331 "DU_C3_power9,VSU_power9")
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332
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333 ; Should differentiate between 1 cr field and > 1 since target of > 1 cr
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334 ; is cracked
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335 (define_insn_reservation "power9-mtcr" 2
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336 (and (eq_attr "type" "mtcr")
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337 (eq_attr "cpu" "power9"))
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338 "DU_any_power9,VSU_power9")
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339
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340 ; Move to LR/CTR are executed in VSU
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341 (define_insn_reservation "power9-mtjmpr" 5
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342 (and (eq_attr "type" "mtjmpr")
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343 (eq_attr "cpu" "power9"))
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344 "DU_any_power9,VSU_power9")
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345
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346 ; Floating point/Vector ops
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347 (define_insn_reservation "power9-fpsimple" 2
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348 (and (eq_attr "type" "fpsimple")
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349 (eq_attr "cpu" "power9"))
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350 "DU_slice_3_power9,VSU_power9")
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351
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352 (define_insn_reservation "power9-fp" 7
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353 (and (eq_attr "type" "fp,dmul")
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354 (eq_attr "cpu" "power9"))
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355 "DU_slice_3_power9,VSU_power9")
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356
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357 (define_insn_reservation "power9-fpcompare" 3
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358 (and (eq_attr "type" "fpcompare")
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359 (eq_attr "cpu" "power9"))
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360 "DU_slice_3_power9,VSU_power9")
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361
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362 ; FP div/sqrt are executed in the VSU slices. They are not pipelined wrt other
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363 ; divide insns, but for the most part do not block pipelined ops.
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364 (define_insn_reservation "power9-sdiv" 22
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365 (and (eq_attr "type" "sdiv")
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366 (eq_attr "cpu" "power9"))
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367 "DU_slice_3_power9,VSU_power9")
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368
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369 (define_insn_reservation "power9-ddiv" 33
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370 (and (eq_attr "type" "ddiv")
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371 (eq_attr "cpu" "power9"))
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372 "DU_slice_3_power9,VSU_power9")
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373
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374 (define_insn_reservation "power9-sqrt" 26
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375 (and (eq_attr "type" "ssqrt")
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376 (eq_attr "cpu" "power9"))
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377 "DU_slice_3_power9,VSU_power9")
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378
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379 (define_insn_reservation "power9-dsqrt" 36
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380 (and (eq_attr "type" "dsqrt")
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381 (eq_attr "cpu" "power9"))
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382 "DU_slice_3_power9,VSU_power9")
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383
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384 (define_insn_reservation "power9-vec-2cyc" 2
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385 (and (eq_attr "type" "vecmove,veclogical,vecexts,veccmpfx")
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386 (eq_attr "cpu" "power9"))
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387 "DU_super_power9,VSU_super_power9")
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388
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389 (define_insn_reservation "power9-veccmp" 3
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390 (and (eq_attr "type" "veccmp")
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391 (eq_attr "cpu" "power9"))
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392 "DU_super_power9,VSU_super_power9")
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393
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394 (define_insn_reservation "power9-vecsimple" 3
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395 (and (eq_attr "type" "vecsimple")
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396 (eq_attr "cpu" "power9"))
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397 "DU_super_power9,VSU_super_power9")
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398
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399 (define_insn_reservation "power9-vecnormal" 7
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400 (and (eq_attr "type" "vecfloat,vecdouble")
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401 (eq_attr "size" "!128")
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402 (eq_attr "cpu" "power9"))
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403 "DU_super_power9,VSU_super_power9")
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404
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405 ; Quad-precision FP ops, execute in DFU
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406 (define_insn_reservation "power9-qp" 12
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407 (and (eq_attr "type" "vecfloat,vecdouble")
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408 (eq_attr "size" "128")
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409 (eq_attr "cpu" "power9"))
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410 "DU_super_power9,dfu_power9")
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411
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412 (define_insn_reservation "power9-vecperm" 3
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413 (and (eq_attr "type" "vecperm")
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414 (eq_attr "cpu" "power9"))
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415 "DU_super_power9,VSU_PRM_power9")
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416
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417 (define_insn_reservation "power9-veccomplex" 7
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418 (and (eq_attr "type" "veccomplex")
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419 (eq_attr "cpu" "power9"))
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420 "DU_super_power9,VSU_super_power9")
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421
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422 (define_insn_reservation "power9-vecfdiv" 28
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423 (and (eq_attr "type" "vecfdiv")
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424 (eq_attr "cpu" "power9"))
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425 "DU_super_power9,VSU_super_power9")
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426
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427 (define_insn_reservation "power9-vecdiv" 32
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428 (and (eq_attr "type" "vecdiv")
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429 (eq_attr "size" "!128")
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430 (eq_attr "cpu" "power9"))
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431 "DU_super_power9,VSU_super_power9")
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432
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433 (define_insn_reservation "power9-qpdiv" 56
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434 (and (eq_attr "type" "vecdiv")
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435 (eq_attr "size" "128")
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|
436 (eq_attr "cpu" "power9"))
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|
437 "DU_super_power9,dfu_power9")
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438
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439 (define_insn_reservation "power9-mffgpr" 2
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440 (and (eq_attr "type" "mffgpr")
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441 (eq_attr "cpu" "power9"))
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|
442 "DU_slice_3_power9,VSU_power9")
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443
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444 (define_insn_reservation "power9-mftgpr" 2
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445 (and (eq_attr "type" "mftgpr")
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446 (eq_attr "cpu" "power9"))
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|
447 "DU_slice_3_power9,VSU_power9")
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448
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449
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450 ; Branch Unit
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451 ; Move from LR/CTR are executed in BRU but consume a writeback port from an
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452 ; execution slice.
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|
453 (define_insn_reservation "power9-mfjmpr" 6
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454 (and (eq_attr "type" "mfjmpr")
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455 (eq_attr "cpu" "power9"))
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|
456 "DU_branch_power9,bru_power9+VSU_power9")
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457
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458 ; Branch is 2 cycles
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|
459 (define_insn_reservation "power9-branch" 2
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|
460 (and (eq_attr "type" "jmpreg,branch")
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|
461 (eq_attr "cpu" "power9"))
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|
462 "DU_branch_power9,bru_power9")
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|
463
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464
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|
465 ; Crypto Unit
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|
466 (define_insn_reservation "power9-crypto" 6
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|
467 (and (eq_attr "type" "crypto")
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|
468 (eq_attr "cpu" "power9"))
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|
469 "DU_super_power9,cryptu_power9")
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|
470
|
|
471
|
|
472 ; HTM Unit
|
|
473 (define_insn_reservation "power9-htm" 4
|
|
474 (and (eq_attr "type" "htm")
|
|
475 (eq_attr "cpu" "power9"))
|
|
476 "DU_C2_power9,LSU_power9")
|
|
477
|
|
478 (define_insn_reservation "power9-htm-simple" 2
|
|
479 (and (eq_attr "type" "htmsimple")
|
|
480 (eq_attr "cpu" "power9"))
|
|
481 "DU_any_power9,VSU_power9")
|
|
482
|
|
483
|
|
484 ; DFP Unit
|
|
485 (define_insn_reservation "power9-dfp" 12
|
|
486 (and (eq_attr "type" "dfp")
|
|
487 (eq_attr "cpu" "power9"))
|
|
488 "DU_even_power9,dfu_power9")
|
|
489
|