Mercurial > hg > CbC > CbC_gcc
annotate gcc/config/rs6000/rs6000.h @ 111:04ced10e8804
gcc 7
| author | kono |
|---|---|
| date | Fri, 27 Oct 2017 22:46:09 +0900 |
| parents | f6334be47118 |
| children | 84e7813d76e9 |
| rev | line source |
|---|---|
| 0 | 1 /* Definitions of target machine for GNU compiler, for IBM RS/6000. |
| 111 | 2 Copyright (C) 1992-2017 Free Software Foundation, Inc. |
| 0 | 3 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) |
| 4 | |
| 5 This file is part of GCC. | |
| 6 | |
| 7 GCC is free software; you can redistribute it and/or modify it | |
| 8 under the terms of the GNU General Public License as published | |
| 9 by the Free Software Foundation; either version 3, or (at your | |
| 10 option) any later version. | |
| 11 | |
| 12 GCC is distributed in the hope that it will be useful, but WITHOUT | |
| 13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
| 14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
| 15 License for more details. | |
| 16 | |
| 17 Under Section 7 of GPL version 3, you are granted additional | |
| 18 permissions described in the GCC Runtime Library Exception, version | |
| 19 3.1, as published by the Free Software Foundation. | |
| 20 | |
| 21 You should have received a copy of the GNU General Public License and | |
| 22 a copy of the GCC Runtime Library Exception along with this program; | |
| 23 see the files COPYING3 and COPYING.RUNTIME respectively. If not, see | |
| 24 <http://www.gnu.org/licenses/>. */ | |
| 25 | |
| 26 /* Note that some other tm.h files include this one and then override | |
| 27 many of the definitions. */ | |
| 28 | |
|
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29 #ifndef RS6000_OPTS_H |
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30 #include "config/rs6000/rs6000-opts.h" |
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31 #endif |
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32 |
| 0 | 33 /* Definitions for the object file format. These are set at |
| 34 compile-time. */ | |
| 35 | |
| 36 #define OBJECT_XCOFF 1 | |
| 37 #define OBJECT_ELF 2 | |
| 38 #define OBJECT_PEF 3 | |
| 39 #define OBJECT_MACHO 4 | |
| 40 | |
| 41 #define TARGET_ELF (TARGET_OBJECT_FORMAT == OBJECT_ELF) | |
| 42 #define TARGET_XCOFF (TARGET_OBJECT_FORMAT == OBJECT_XCOFF) | |
| 43 #define TARGET_MACOS (TARGET_OBJECT_FORMAT == OBJECT_PEF) | |
| 44 #define TARGET_MACHO (TARGET_OBJECT_FORMAT == OBJECT_MACHO) | |
| 45 | |
| 46 #ifndef TARGET_AIX | |
| 47 #define TARGET_AIX 0 | |
| 48 #endif | |
| 49 | |
|
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50 #ifndef TARGET_AIX_OS |
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51 #define TARGET_AIX_OS 0 |
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52 #endif |
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53 |
| 0 | 54 /* Control whether function entry points use a "dot" symbol when |
| 55 ABI_AIX. */ | |
| 56 #define DOT_SYMBOLS 1 | |
| 57 | |
| 58 /* Default string to use for cpu if not specified. */ | |
| 59 #ifndef TARGET_CPU_DEFAULT | |
| 60 #define TARGET_CPU_DEFAULT ((char *)0) | |
| 61 #endif | |
| 62 | |
| 63 /* If configured for PPC405, support PPC405CR Erratum77. */ | |
| 64 #ifdef CONFIG_PPC405CR | |
| 65 #define PPC405_ERRATUM77 (rs6000_cpu == PROCESSOR_PPC405) | |
| 66 #else | |
| 67 #define PPC405_ERRATUM77 0 | |
| 68 #endif | |
| 69 | |
| 70 #ifndef TARGET_PAIRED_FLOAT | |
| 71 #define TARGET_PAIRED_FLOAT 0 | |
| 72 #endif | |
| 73 | |
| 74 #ifdef HAVE_AS_POPCNTB | |
| 75 #define ASM_CPU_POWER5_SPEC "-mpower5" | |
| 76 #else | |
| 77 #define ASM_CPU_POWER5_SPEC "-mpower4" | |
| 78 #endif | |
| 79 | |
| 80 #ifdef HAVE_AS_DFP | |
| 81 #define ASM_CPU_POWER6_SPEC "-mpower6 -maltivec" | |
| 82 #else | |
| 83 #define ASM_CPU_POWER6_SPEC "-mpower4 -maltivec" | |
| 84 #endif | |
| 85 | |
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86 #ifdef HAVE_AS_POPCNTD |
| 0 | 87 #define ASM_CPU_POWER7_SPEC "-mpower7" |
| 88 #else | |
| 89 #define ASM_CPU_POWER7_SPEC "-mpower4 -maltivec" | |
| 90 #endif | |
| 91 | |
| 111 | 92 #ifdef HAVE_AS_POWER8 |
| 93 #define ASM_CPU_POWER8_SPEC "-mpower8" | |
| 94 #else | |
| 95 #define ASM_CPU_POWER8_SPEC ASM_CPU_POWER7_SPEC | |
| 96 #endif | |
| 97 | |
| 98 #ifdef HAVE_AS_POWER9 | |
| 99 #define ASM_CPU_POWER9_SPEC "-mpower9" | |
| 100 #else | |
| 101 #define ASM_CPU_POWER9_SPEC ASM_CPU_POWER8_SPEC | |
| 102 #endif | |
| 103 | |
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104 #ifdef HAVE_AS_DCI |
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105 #define ASM_CPU_476_SPEC "-m476" |
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106 #else |
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107 #define ASM_CPU_476_SPEC "-mpower4" |
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108 #endif |
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109 |
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110 /* Common ASM definitions used by ASM_SPEC among the various targets for |
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111 handling -mcpu=xxx switches. There is a parallel list in driver-rs6000.c to |
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112 provide the default assembler options if the user uses -mcpu=native, so if |
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113 you make changes here, make them also there. */ |
| 0 | 114 #define ASM_CPU_SPEC \ |
| 115 "%{!mcpu*: \ | |
| 116 %{mpowerpc64*: -mppc64} \ | |
| 111 | 117 %{!mpowerpc64*: %(asm_default)}} \ |
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118 %{mcpu=native: %(asm_cpu_native)} \ |
| 0 | 119 %{mcpu=cell: -mcell} \ |
| 120 %{mcpu=power3: -mppc64} \ | |
| 121 %{mcpu=power4: -mpower4} \ | |
| 122 %{mcpu=power5: %(asm_cpu_power5)} \ | |
| 123 %{mcpu=power5+: %(asm_cpu_power5)} \ | |
| 124 %{mcpu=power6: %(asm_cpu_power6) -maltivec} \ | |
| 125 %{mcpu=power6x: %(asm_cpu_power6) -maltivec} \ | |
| 126 %{mcpu=power7: %(asm_cpu_power7)} \ | |
| 111 | 127 %{mcpu=power8: %(asm_cpu_power8)} \ |
| 128 %{mcpu=power9: %(asm_cpu_power9)} \ | |
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129 %{mcpu=a2: -ma2} \ |
| 0 | 130 %{mcpu=powerpc: -mppc} \ |
| 111 | 131 %{mcpu=powerpc64le: %(asm_cpu_power8)} \ |
| 0 | 132 %{mcpu=rs64a: -mppc64} \ |
| 133 %{mcpu=401: -mppc} \ | |
| 134 %{mcpu=403: -m403} \ | |
| 135 %{mcpu=405: -m405} \ | |
| 136 %{mcpu=405fp: -m405} \ | |
| 137 %{mcpu=440: -m440} \ | |
| 138 %{mcpu=440fp: -m440} \ | |
| 139 %{mcpu=464: -m440} \ | |
| 140 %{mcpu=464fp: -m440} \ | |
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141 %{mcpu=476: %(asm_cpu_476)} \ |
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142 %{mcpu=476fp: %(asm_cpu_476)} \ |
| 0 | 143 %{mcpu=505: -mppc} \ |
| 144 %{mcpu=601: -m601} \ | |
| 145 %{mcpu=602: -mppc} \ | |
| 146 %{mcpu=603: -mppc} \ | |
| 147 %{mcpu=603e: -mppc} \ | |
| 148 %{mcpu=ec603e: -mppc} \ | |
| 149 %{mcpu=604: -mppc} \ | |
| 150 %{mcpu=604e: -mppc} \ | |
| 151 %{mcpu=620: -mppc64} \ | |
| 152 %{mcpu=630: -mppc64} \ | |
| 153 %{mcpu=740: -mppc} \ | |
| 154 %{mcpu=750: -mppc} \ | |
| 155 %{mcpu=G3: -mppc} \ | |
| 156 %{mcpu=7400: -mppc -maltivec} \ | |
| 157 %{mcpu=7450: -mppc -maltivec} \ | |
| 158 %{mcpu=G4: -mppc -maltivec} \ | |
| 159 %{mcpu=801: -mppc} \ | |
| 160 %{mcpu=821: -mppc} \ | |
| 161 %{mcpu=823: -mppc} \ | |
| 162 %{mcpu=860: -mppc} \ | |
| 163 %{mcpu=970: -mpower4 -maltivec} \ | |
| 164 %{mcpu=G5: -mpower4 -maltivec} \ | |
| 165 %{mcpu=8540: -me500} \ | |
| 166 %{mcpu=8548: -me500} \ | |
| 167 %{mcpu=e300c2: -me300} \ | |
| 168 %{mcpu=e300c3: -me300} \ | |
| 169 %{mcpu=e500mc: -me500mc} \ | |
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170 %{mcpu=e500mc64: -me500mc64} \ |
| 111 | 171 %{mcpu=e5500: -me5500} \ |
| 172 %{mcpu=e6500: -me6500} \ | |
| 0 | 173 %{maltivec: -maltivec} \ |
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174 %{mvsx: -mvsx %{!maltivec: -maltivec} %{!mcpu*: %(asm_cpu_power7)}} \ |
| 111 | 175 %{mpower8-vector|mcrypto|mdirect-move|mhtm: %{!mcpu*: %(asm_cpu_power8)}} \ |
| 0 | 176 -many" |
| 177 | |
| 178 #define CPP_DEFAULT_SPEC "" | |
| 179 | |
| 180 #define ASM_DEFAULT_SPEC "" | |
| 181 | |
| 182 /* This macro defines names of additional specifications to put in the specs | |
| 183 that can be used in various specifications like CC1_SPEC. Its definition | |
| 184 is an initializer with a subgrouping for each command option. | |
| 185 | |
| 186 Each subgrouping contains a string constant, that defines the | |
| 187 specification name, and a string constant that used by the GCC driver | |
| 188 program. | |
| 189 | |
| 190 Do not define this macro if it does not need to do anything. */ | |
| 191 | |
| 192 #define SUBTARGET_EXTRA_SPECS | |
| 193 | |
| 194 #define EXTRA_SPECS \ | |
| 195 { "cpp_default", CPP_DEFAULT_SPEC }, \ | |
| 196 { "asm_cpu", ASM_CPU_SPEC }, \ | |
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197 { "asm_cpu_native", ASM_CPU_NATIVE_SPEC }, \ |
| 0 | 198 { "asm_default", ASM_DEFAULT_SPEC }, \ |
| 199 { "cc1_cpu", CC1_CPU_SPEC }, \ | |
| 200 { "asm_cpu_power5", ASM_CPU_POWER5_SPEC }, \ | |
| 201 { "asm_cpu_power6", ASM_CPU_POWER6_SPEC }, \ | |
| 202 { "asm_cpu_power7", ASM_CPU_POWER7_SPEC }, \ | |
| 111 | 203 { "asm_cpu_power8", ASM_CPU_POWER8_SPEC }, \ |
| 204 { "asm_cpu_power9", ASM_CPU_POWER9_SPEC }, \ | |
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205 { "asm_cpu_476", ASM_CPU_476_SPEC }, \ |
| 0 | 206 SUBTARGET_EXTRA_SPECS |
| 207 | |
| 208 /* -mcpu=native handling only makes sense with compiler running on | |
| 209 an PowerPC chip. If changing this condition, also change | |
| 210 the condition in driver-rs6000.c. */ | |
| 211 #if defined(__powerpc__) || defined(__POWERPC__) || defined(_AIX) | |
| 212 /* In driver-rs6000.c. */ | |
| 213 extern const char *host_detect_local_cpu (int argc, const char **argv); | |
| 214 #define EXTRA_SPEC_FUNCTIONS \ | |
| 215 { "local_cpu_detect", host_detect_local_cpu }, | |
| 216 #define HAVE_LOCAL_CPU_DETECT | |
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217 #define ASM_CPU_NATIVE_SPEC "%:local_cpu_detect(asm)" |
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218 |
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219 #else |
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220 #define ASM_CPU_NATIVE_SPEC "%(asm_default)" |
| 0 | 221 #endif |
| 222 | |
| 223 #ifndef CC1_CPU_SPEC | |
| 224 #ifdef HAVE_LOCAL_CPU_DETECT | |
| 225 #define CC1_CPU_SPEC \ | |
| 226 "%{mcpu=native:%<mcpu=native %:local_cpu_detect(cpu)} \ | |
| 227 %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}" | |
| 228 #else | |
| 229 #define CC1_CPU_SPEC "" | |
| 230 #endif | |
| 231 #endif | |
| 232 | |
| 233 /* Architecture type. */ | |
| 234 | |
| 235 /* Define TARGET_MFCRF if the target assembler does not support the | |
| 236 optional field operand for mfcr. */ | |
| 237 | |
| 238 #ifndef HAVE_AS_MFCRF | |
| 239 #undef TARGET_MFCRF | |
| 240 #define TARGET_MFCRF 0 | |
| 241 #endif | |
| 242 | |
| 243 /* Define TARGET_POPCNTB if the target assembler does not support the | |
| 244 popcount byte instruction. */ | |
| 245 | |
| 246 #ifndef HAVE_AS_POPCNTB | |
| 247 #undef TARGET_POPCNTB | |
| 248 #define TARGET_POPCNTB 0 | |
| 249 #endif | |
| 250 | |
| 251 /* Define TARGET_FPRND if the target assembler does not support the | |
| 252 fp rounding instructions. */ | |
| 253 | |
| 254 #ifndef HAVE_AS_FPRND | |
| 255 #undef TARGET_FPRND | |
| 256 #define TARGET_FPRND 0 | |
| 257 #endif | |
| 258 | |
| 259 /* Define TARGET_CMPB if the target assembler does not support the | |
| 260 cmpb instruction. */ | |
| 261 | |
| 262 #ifndef HAVE_AS_CMPB | |
| 263 #undef TARGET_CMPB | |
| 264 #define TARGET_CMPB 0 | |
| 265 #endif | |
| 266 | |
| 267 /* Define TARGET_MFPGPR if the target assembler does not support the | |
| 268 mffpr and mftgpr instructions. */ | |
| 269 | |
| 270 #ifndef HAVE_AS_MFPGPR | |
| 271 #undef TARGET_MFPGPR | |
| 272 #define TARGET_MFPGPR 0 | |
| 273 #endif | |
| 274 | |
| 275 /* Define TARGET_DFP if the target assembler does not support decimal | |
| 276 floating point instructions. */ | |
| 277 #ifndef HAVE_AS_DFP | |
| 278 #undef TARGET_DFP | |
| 279 #define TARGET_DFP 0 | |
| 280 #endif | |
| 281 | |
|
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282 /* Define TARGET_POPCNTD if the target assembler does not support the |
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283 popcount word and double word instructions. */ |
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284 |
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285 #ifndef HAVE_AS_POPCNTD |
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286 #undef TARGET_POPCNTD |
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287 #define TARGET_POPCNTD 0 |
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288 #endif |
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289 |
| 111 | 290 /* Define the ISA 2.07 flags as 0 if the target assembler does not support the |
| 291 waitasecond instruction. Allow -mpower8-fusion, since it does not add new | |
| 292 instructions. */ | |
| 293 | |
| 294 #ifndef HAVE_AS_POWER8 | |
| 295 #undef TARGET_DIRECT_MOVE | |
| 296 #undef TARGET_CRYPTO | |
| 297 #undef TARGET_HTM | |
| 298 #undef TARGET_P8_VECTOR | |
| 299 #define TARGET_DIRECT_MOVE 0 | |
| 300 #define TARGET_CRYPTO 0 | |
| 301 #define TARGET_HTM 0 | |
| 302 #define TARGET_P8_VECTOR 0 | |
| 303 #endif | |
| 304 | |
| 305 /* Define the ISA 3.0 flags as 0 if the target assembler does not support | |
| 306 Power9 instructions. Allow -mpower9-fusion, since it does not add new | |
| 307 instructions. Allow -misel, since it predates ISA 3.0 and does | |
| 308 not require any Power9 features. */ | |
| 309 | |
| 310 #ifndef HAVE_AS_POWER9 | |
| 311 #undef TARGET_FLOAT128_HW | |
| 312 #undef TARGET_MODULO | |
| 313 #undef TARGET_P9_VECTOR | |
| 314 #undef TARGET_P9_MINMAX | |
| 315 #undef TARGET_P9_MISC | |
| 316 #define TARGET_FLOAT128_HW 0 | |
| 317 #define TARGET_MODULO 0 | |
| 318 #define TARGET_P9_VECTOR 0 | |
| 319 #define TARGET_P9_MINMAX 0 | |
| 320 #define TARGET_P9_MISC 0 | |
| 321 #endif | |
| 322 | |
|
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323 /* Define TARGET_LWSYNC_INSTRUCTION if the assembler knows about lwsync. If |
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324 not, generate the lwsync code as an integer constant. */ |
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325 #ifdef HAVE_AS_LWSYNC |
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326 #define TARGET_LWSYNC_INSTRUCTION 1 |
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327 #else |
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328 #define TARGET_LWSYNC_INSTRUCTION 0 |
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329 #endif |
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330 |
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331 /* Define TARGET_TLS_MARKERS if the target assembler does not support |
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332 arg markers for __tls_get_addr calls. */ |
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333 #ifndef HAVE_AS_TLS_MARKERS |
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334 #undef TARGET_TLS_MARKERS |
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335 #define TARGET_TLS_MARKERS 0 |
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336 #else |
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337 #define TARGET_TLS_MARKERS tls_markers |
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338 #endif |
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339 |
| 0 | 340 #ifndef TARGET_SECURE_PLT |
| 341 #define TARGET_SECURE_PLT 0 | |
| 342 #endif | |
| 343 | |
|
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344 #ifndef TARGET_CMODEL |
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345 #define TARGET_CMODEL CMODEL_SMALL |
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346 #endif |
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347 |
| 0 | 348 #define TARGET_32BIT (! TARGET_64BIT) |
| 349 | |
| 350 #ifndef HAVE_AS_TLS | |
| 351 #define HAVE_AS_TLS 0 | |
| 352 #endif | |
| 353 | |
| 111 | 354 #ifndef TARGET_LINK_STACK |
| 355 #define TARGET_LINK_STACK 0 | |
| 356 #endif | |
| 357 | |
| 358 #ifndef SET_TARGET_LINK_STACK | |
| 359 #define SET_TARGET_LINK_STACK(X) do { } while (0) | |
| 360 #endif | |
| 361 | |
| 362 #ifndef TARGET_FLOAT128_ENABLE_TYPE | |
| 363 #define TARGET_FLOAT128_ENABLE_TYPE 0 | |
| 364 #endif | |
| 365 | |
| 0 | 366 /* Return 1 for a symbol ref for a thread-local storage symbol. */ |
| 367 #define RS6000_SYMBOL_REF_TLS_P(RTX) \ | |
| 368 (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0) | |
| 369 | |
| 370 #ifdef IN_LIBGCC2 | |
| 371 /* For libgcc2 we make sure this is a compile time constant */ | |
| 372 #if defined (__64BIT__) || defined (__powerpc64__) || defined (__ppc64__) | |
| 373 #undef TARGET_POWERPC64 | |
| 374 #define TARGET_POWERPC64 1 | |
| 375 #else | |
| 376 #undef TARGET_POWERPC64 | |
| 377 #define TARGET_POWERPC64 0 | |
| 378 #endif | |
| 379 #else | |
| 380 /* The option machinery will define this. */ | |
| 381 #endif | |
| 382 | |
| 111 | 383 #define TARGET_DEFAULT (MASK_MULTIPLE | MASK_STRING) |
| 0 | 384 |
| 385 /* FPU operations supported. | |
| 386 Each use of TARGET_SINGLE_FLOAT or TARGET_DOUBLE_FLOAT must | |
| 387 also test TARGET_HARD_FLOAT. */ | |
| 388 #define TARGET_SINGLE_FLOAT 1 | |
| 389 #define TARGET_DOUBLE_FLOAT 1 | |
| 390 #define TARGET_SINGLE_FPU 0 | |
| 391 #define TARGET_SIMPLE_FPU 0 | |
| 392 #define TARGET_XILINX_FPU 0 | |
| 393 | |
| 394 /* Recast the processor type to the cpu attribute. */ | |
| 395 #define rs6000_cpu_attr ((enum attr_cpu)rs6000_cpu) | |
| 396 | |
| 397 /* Define generic processor types based upon current deployment. */ | |
| 398 #define PROCESSOR_COMMON PROCESSOR_PPC601 | |
| 399 #define PROCESSOR_POWERPC PROCESSOR_PPC604 | |
| 400 #define PROCESSOR_POWERPC64 PROCESSOR_RS64A | |
| 401 | |
| 402 /* Define the default processor. This is overridden by other tm.h files. */ | |
| 111 | 403 #define PROCESSOR_DEFAULT PROCESSOR_PPC603 |
| 0 | 404 #define PROCESSOR_DEFAULT64 PROCESSOR_RS64A |
| 405 | |
| 111 | 406 /* Specify the dialect of assembler to use. Only new mnemonics are supported |
| 407 starting with GCC 4.8, i.e. just one dialect, but for backwards | |
| 408 compatibility with older inline asm ASSEMBLER_DIALECT needs to be | |
| 409 defined. */ | |
| 410 #define ASSEMBLER_DIALECT 1 | |
| 0 | 411 |
| 412 /* Debug support */ | |
|
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413 #define MASK_DEBUG_STACK 0x01 /* debug stack applications */ |
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414 #define MASK_DEBUG_ARG 0x02 /* debug argument handling */ |
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415 #define MASK_DEBUG_REG 0x04 /* debug register handling */ |
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416 #define MASK_DEBUG_ADDR 0x08 /* debug memory addressing */ |
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417 #define MASK_DEBUG_COST 0x10 /* debug rtx codes */ |
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418 #define MASK_DEBUG_TARGET 0x20 /* debug target attribute/pragma */ |
| 111 | 419 #define MASK_DEBUG_BUILTIN 0x40 /* debug builtins */ |
|
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420 #define MASK_DEBUG_ALL (MASK_DEBUG_STACK \ |
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421 | MASK_DEBUG_ARG \ |
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422 | MASK_DEBUG_REG \ |
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423 | MASK_DEBUG_ADDR \ |
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424 | MASK_DEBUG_COST \ |
| 111 | 425 | MASK_DEBUG_TARGET \ |
| 426 | MASK_DEBUG_BUILTIN) | |
|
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427 |
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428 #define TARGET_DEBUG_STACK (rs6000_debug & MASK_DEBUG_STACK) |
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429 #define TARGET_DEBUG_ARG (rs6000_debug & MASK_DEBUG_ARG) |
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430 #define TARGET_DEBUG_REG (rs6000_debug & MASK_DEBUG_REG) |
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431 #define TARGET_DEBUG_ADDR (rs6000_debug & MASK_DEBUG_ADDR) |
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432 #define TARGET_DEBUG_COST (rs6000_debug & MASK_DEBUG_COST) |
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433 #define TARGET_DEBUG_TARGET (rs6000_debug & MASK_DEBUG_TARGET) |
| 111 | 434 #define TARGET_DEBUG_BUILTIN (rs6000_debug & MASK_DEBUG_BUILTIN) |
| 435 | |
| 436 /* Helper macros for TFmode. Quad floating point (TFmode) can be either IBM | |
| 437 long double format that uses a pair of doubles, or IEEE 128-bit floating | |
| 438 point. KFmode was added as a way to represent IEEE 128-bit floating point, | |
| 439 even if the default for long double is the IBM long double format. | |
| 440 Similarly IFmode is the IBM long double format even if the default is IEEE | |
| 441 128-bit. Don't allow IFmode if -msoft-float. */ | |
| 442 #define FLOAT128_IEEE_P(MODE) \ | |
| 443 ((TARGET_IEEEQUAD && ((MODE) == TFmode || (MODE) == TCmode)) \ | |
| 444 || ((MODE) == KFmode) || ((MODE) == KCmode)) | |
| 445 | |
| 446 #define FLOAT128_IBM_P(MODE) \ | |
| 447 ((!TARGET_IEEEQUAD && ((MODE) == TFmode || (MODE) == TCmode)) \ | |
| 448 || (TARGET_HARD_FLOAT && ((MODE) == IFmode || (MODE) == ICmode))) | |
| 449 | |
| 450 /* Helper macros to say whether a 128-bit floating point type can go in a | |
| 451 single vector register, or whether it needs paired scalar values. */ | |
| 452 #define FLOAT128_VECTOR_P(MODE) (TARGET_FLOAT128_TYPE && FLOAT128_IEEE_P (MODE)) | |
| 453 | |
| 454 #define FLOAT128_2REG_P(MODE) \ | |
| 455 (FLOAT128_IBM_P (MODE) \ | |
| 456 || ((MODE) == TDmode) \ | |
| 457 || (!TARGET_FLOAT128_TYPE && FLOAT128_IEEE_P (MODE))) | |
| 458 | |
| 459 /* Return true for floating point that does not use a vector register. */ | |
| 460 #define SCALAR_FLOAT_MODE_NOT_VECTOR_P(MODE) \ | |
| 461 (SCALAR_FLOAT_MODE_P (MODE) && !FLOAT128_VECTOR_P (MODE)) | |
| 462 | |
| 463 /* Describe the vector unit used for arithmetic operations. */ | |
|
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464 extern enum rs6000_vector rs6000_vector_unit[]; |
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465 |
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466 #define VECTOR_UNIT_NONE_P(MODE) \ |
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467 (rs6000_vector_unit[(MODE)] == VECTOR_NONE) |
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468 |
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469 #define VECTOR_UNIT_VSX_P(MODE) \ |
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470 (rs6000_vector_unit[(MODE)] == VECTOR_VSX) |
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471 |
| 111 | 472 #define VECTOR_UNIT_P8_VECTOR_P(MODE) \ |
| 473 (rs6000_vector_unit[(MODE)] == VECTOR_P8_VECTOR) | |
| 474 | |
|
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475 #define VECTOR_UNIT_ALTIVEC_P(MODE) \ |
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476 (rs6000_vector_unit[(MODE)] == VECTOR_ALTIVEC) |
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477 |
| 111 | 478 #define VECTOR_UNIT_VSX_OR_P8_VECTOR_P(MODE) \ |
| 479 (IN_RANGE ((int)rs6000_vector_unit[(MODE)], \ | |
| 480 (int)VECTOR_VSX, \ | |
| 481 (int)VECTOR_P8_VECTOR)) | |
| 482 | |
| 483 /* VECTOR_UNIT_ALTIVEC_OR_VSX_P is used in places where we are using either | |
| 484 altivec (VMX) or VSX vector instructions. P8 vector support is upwards | |
| 485 compatible, so allow it as well, rather than changing all of the uses of the | |
| 486 macro. */ | |
|
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487 #define VECTOR_UNIT_ALTIVEC_OR_VSX_P(MODE) \ |
| 111 | 488 (IN_RANGE ((int)rs6000_vector_unit[(MODE)], \ |
| 489 (int)VECTOR_ALTIVEC, \ | |
| 490 (int)VECTOR_P8_VECTOR)) | |
|
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491 |
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492 /* Describe whether to use VSX loads or Altivec loads. For now, just use the |
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493 same unit as the vector unit we are using, but we may want to migrate to |
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494 using VSX style loads even for types handled by altivec. */ |
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495 extern enum rs6000_vector rs6000_vector_mem[]; |
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496 |
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497 #define VECTOR_MEM_NONE_P(MODE) \ |
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498 (rs6000_vector_mem[(MODE)] == VECTOR_NONE) |
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499 |
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500 #define VECTOR_MEM_VSX_P(MODE) \ |
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501 (rs6000_vector_mem[(MODE)] == VECTOR_VSX) |
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502 |
| 111 | 503 #define VECTOR_MEM_P8_VECTOR_P(MODE) \ |
| 504 (rs6000_vector_mem[(MODE)] == VECTOR_VSX) | |
| 505 | |
|
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506 #define VECTOR_MEM_ALTIVEC_P(MODE) \ |
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507 (rs6000_vector_mem[(MODE)] == VECTOR_ALTIVEC) |
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508 |
| 111 | 509 #define VECTOR_MEM_VSX_OR_P8_VECTOR_P(MODE) \ |
| 510 (IN_RANGE ((int)rs6000_vector_mem[(MODE)], \ | |
| 511 (int)VECTOR_VSX, \ | |
| 512 (int)VECTOR_P8_VECTOR)) | |
| 513 | |
|
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514 #define VECTOR_MEM_ALTIVEC_OR_VSX_P(MODE) \ |
| 111 | 515 (IN_RANGE ((int)rs6000_vector_mem[(MODE)], \ |
| 516 (int)VECTOR_ALTIVEC, \ | |
| 517 (int)VECTOR_P8_VECTOR)) | |
|
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518 |
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519 /* Return the alignment of a given vector type, which is set based on the |
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520 vector unit use. VSX for instance can load 32 or 64 bit aligned words |
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521 without problems, while Altivec requires 128-bit aligned vectors. */ |
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522 extern int rs6000_vector_align[]; |
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523 |
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524 #define VECTOR_ALIGN(MODE) \ |
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525 ((rs6000_vector_align[(MODE)] != 0) \ |
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526 ? rs6000_vector_align[(MODE)] \ |
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527 : (int)GET_MODE_BITSIZE ((MODE))) |
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528 |
| 111 | 529 /* Determine the element order to use for vector instructions. By |
| 530 default we use big-endian element order when targeting big-endian, | |
| 531 and little-endian element order when targeting little-endian. For | |
| 532 programs being ported from BE Power to LE Power, it can sometimes | |
| 533 be useful to use big-endian element order when targeting little-endian. | |
| 534 This is set via -maltivec=be, for example. */ | |
| 535 #define VECTOR_ELT_ORDER_BIG \ | |
| 536 (BYTES_BIG_ENDIAN || (rs6000_altivec_element_order == 2)) | |
| 537 | |
| 538 /* Element number of the 64-bit value in a 128-bit vector that can be accessed | |
| 539 with scalar instructions. */ | |
| 540 #define VECTOR_ELEMENT_SCALAR_64BIT ((BYTES_BIG_ENDIAN) ? 0 : 1) | |
| 541 | |
| 542 /* Element number of the 64-bit value in a 128-bit vector that can be accessed | |
| 543 with the ISA 3.0 MFVSRLD instructions. */ | |
| 544 #define VECTOR_ELEMENT_MFVSRLD_64BIT ((BYTES_BIG_ENDIAN) ? 1 : 0) | |
| 545 | |
| 0 | 546 /* Alignment options for fields in structures for sub-targets following |
| 547 AIX-like ABI. | |
| 548 ALIGN_POWER word-aligns FP doubles (default AIX ABI). | |
| 549 ALIGN_NATURAL doubleword-aligns FP doubles (align to object size). | |
| 550 | |
| 551 Override the macro definitions when compiling libobjc to avoid undefined | |
| 552 reference to rs6000_alignment_flags due to library's use of GCC alignment | |
| 553 macros which use the macros below. */ | |
| 554 | |
| 555 #ifndef IN_TARGET_LIBS | |
| 556 #define MASK_ALIGN_POWER 0x00000000 | |
| 557 #define MASK_ALIGN_NATURAL 0x00000001 | |
| 558 #define TARGET_ALIGN_NATURAL (rs6000_alignment_flags & MASK_ALIGN_NATURAL) | |
| 559 #else | |
| 560 #define TARGET_ALIGN_NATURAL 0 | |
| 561 #endif | |
| 562 | |
| 563 #define TARGET_LONG_DOUBLE_128 (rs6000_long_double_type_size == 128) | |
| 564 #define TARGET_IEEEQUAD rs6000_ieeequad | |
| 565 #define TARGET_ALTIVEC_ABI rs6000_altivec_abi | |
|
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566 #define TARGET_LDBRX (TARGET_POPCNTD || rs6000_cpu == PROCESSOR_CELL) |
| 0 | 567 |
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568 /* ISA 2.01 allowed FCFID to be done in 32-bit, previously it was 64-bit only. |
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569 Enable 32-bit fcfid's on any of the switches for newer ISA machines or |
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570 XILINX. */ |
| 111 | 571 #define TARGET_FCFID (TARGET_POWERPC64 \ |
| 572 || TARGET_PPC_GPOPT /* 970/power4 */ \ | |
| 573 || TARGET_POPCNTB /* ISA 2.02 */ \ | |
| 574 || TARGET_CMPB /* ISA 2.05 */ \ | |
| 575 || TARGET_POPCNTD /* ISA 2.06 */ \ | |
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576 || TARGET_XILINX_FPU) |
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577 |
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578 #define TARGET_FCTIDZ TARGET_FCFID |
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579 #define TARGET_STFIWX TARGET_PPC_GFXOPT |
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580 #define TARGET_LFIWAX TARGET_CMPB |
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581 #define TARGET_LFIWZX TARGET_POPCNTD |
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582 #define TARGET_FCFIDS TARGET_POPCNTD |
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583 #define TARGET_FCFIDU TARGET_POPCNTD |
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584 #define TARGET_FCFIDUS TARGET_POPCNTD |
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585 #define TARGET_FCTIDUZ TARGET_POPCNTD |
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586 #define TARGET_FCTIWUZ TARGET_POPCNTD |
| 111 | 587 #define TARGET_CTZ TARGET_MODULO |
| 588 #define TARGET_EXTSWSLI (TARGET_MODULO && TARGET_POWERPC64) | |
| 589 #define TARGET_MADDLD (TARGET_MODULO && TARGET_POWERPC64) | |
| 590 | |
| 591 #define TARGET_XSCVDPSPN (TARGET_DIRECT_MOVE || TARGET_P8_VECTOR) | |
| 592 #define TARGET_XSCVSPDPN (TARGET_DIRECT_MOVE || TARGET_P8_VECTOR) | |
| 593 #define TARGET_VADDUQM (TARGET_P8_VECTOR && TARGET_POWERPC64) | |
| 594 #define TARGET_DIRECT_MOVE_128 (TARGET_P9_VECTOR && TARGET_DIRECT_MOVE \ | |
| 595 && TARGET_POWERPC64) | |
| 596 #define TARGET_VEXTRACTUB (TARGET_P9_VECTOR && TARGET_DIRECT_MOVE \ | |
| 597 && TARGET_POWERPC64) | |
| 598 | |
| 599 /* Whether we should avoid (SUBREG:SI (REG:SF) and (SUBREG:SF (REG:SI). */ | |
| 600 #define TARGET_NO_SF_SUBREG TARGET_DIRECT_MOVE_64BIT | |
| 601 #define TARGET_ALLOW_SF_SUBREG (!TARGET_DIRECT_MOVE_64BIT) | |
| 602 | |
| 603 /* This wants to be set for p8 and newer. On p7, overlapping unaligned | |
| 604 loads are slow. */ | |
| 605 #define TARGET_EFFICIENT_OVERLAPPING_UNALIGNED TARGET_EFFICIENT_UNALIGNED_VSX | |
| 606 | |
| 607 /* Byte/char syncs were added as phased in for ISA 2.06B, but are not present | |
| 608 in power7, so conditionalize them on p8 features. TImode syncs need quad | |
| 609 memory support. */ | |
| 610 #define TARGET_SYNC_HI_QI (TARGET_QUAD_MEMORY \ | |
| 611 || TARGET_QUAD_MEMORY_ATOMIC \ | |
| 612 || TARGET_DIRECT_MOVE) | |
| 613 | |
| 614 #define TARGET_SYNC_TI TARGET_QUAD_MEMORY_ATOMIC | |
| 615 | |
| 616 /* Power7 has both 32-bit load and store integer for the FPRs, so we don't need | |
| 617 to allocate the SDmode stack slot to get the value into the proper location | |
| 618 in the register. */ | |
| 619 #define TARGET_NO_SDMODE_STACK (TARGET_LFIWZX && TARGET_STFIWX && TARGET_DFP) | |
| 620 | |
| 621 /* ISA 3.0 has new min/max functions that don't need fast math that are being | |
| 622 phased in. Min/max using FSEL or XSMAXDP/XSMINDP do not return the correct | |
| 623 answers if the arguments are not in the normal range. */ | |
| 624 #define TARGET_MINMAX_SF (TARGET_SF_FPR && TARGET_PPC_GFXOPT \ | |
| 625 && (TARGET_P9_MINMAX || !flag_trapping_math)) | |
| 626 | |
| 627 #define TARGET_MINMAX_DF (TARGET_DF_FPR && TARGET_PPC_GFXOPT \ | |
| 628 && (TARGET_P9_MINMAX || !flag_trapping_math)) | |
| 629 | |
| 630 /* In switching from using target_flags to using rs6000_isa_flags, the options | |
| 631 machinery creates OPTION_MASK_<xxx> instead of MASK_<xxx>. For now map | |
| 632 OPTION_MASK_<xxx> back into MASK_<xxx>. */ | |
| 633 #define MASK_ALTIVEC OPTION_MASK_ALTIVEC | |
| 634 #define MASK_CMPB OPTION_MASK_CMPB | |
| 635 #define MASK_CRYPTO OPTION_MASK_CRYPTO | |
| 636 #define MASK_DFP OPTION_MASK_DFP | |
| 637 #define MASK_DIRECT_MOVE OPTION_MASK_DIRECT_MOVE | |
| 638 #define MASK_DLMZB OPTION_MASK_DLMZB | |
| 639 #define MASK_EABI OPTION_MASK_EABI | |
| 640 #define MASK_FLOAT128_KEYWORD OPTION_MASK_FLOAT128_KEYWORD | |
| 641 #define MASK_FLOAT128_HW OPTION_MASK_FLOAT128_HW | |
| 642 #define MASK_FPRND OPTION_MASK_FPRND | |
| 643 #define MASK_P8_FUSION OPTION_MASK_P8_FUSION | |
| 644 #define MASK_HARD_FLOAT OPTION_MASK_HARD_FLOAT | |
| 645 #define MASK_HTM OPTION_MASK_HTM | |
| 646 #define MASK_ISEL OPTION_MASK_ISEL | |
| 647 #define MASK_MFCRF OPTION_MASK_MFCRF | |
| 648 #define MASK_MFPGPR OPTION_MASK_MFPGPR | |
| 649 #define MASK_MULHW OPTION_MASK_MULHW | |
| 650 #define MASK_MULTIPLE OPTION_MASK_MULTIPLE | |
| 651 #define MASK_NO_UPDATE OPTION_MASK_NO_UPDATE | |
| 652 #define MASK_P8_VECTOR OPTION_MASK_P8_VECTOR | |
| 653 #define MASK_P9_VECTOR OPTION_MASK_P9_VECTOR | |
| 654 #define MASK_P9_MISC OPTION_MASK_P9_MISC | |
| 655 #define MASK_POPCNTB OPTION_MASK_POPCNTB | |
| 656 #define MASK_POPCNTD OPTION_MASK_POPCNTD | |
| 657 #define MASK_PPC_GFXOPT OPTION_MASK_PPC_GFXOPT | |
| 658 #define MASK_PPC_GPOPT OPTION_MASK_PPC_GPOPT | |
| 659 #define MASK_RECIP_PRECISION OPTION_MASK_RECIP_PRECISION | |
| 660 #define MASK_SOFT_FLOAT OPTION_MASK_SOFT_FLOAT | |
| 661 #define MASK_STRICT_ALIGN OPTION_MASK_STRICT_ALIGN | |
| 662 #define MASK_STRING OPTION_MASK_STRING | |
| 663 #define MASK_UPDATE OPTION_MASK_UPDATE | |
| 664 #define MASK_VSX OPTION_MASK_VSX | |
| 665 | |
| 666 #ifndef IN_LIBGCC2 | |
| 667 #define MASK_POWERPC64 OPTION_MASK_POWERPC64 | |
| 668 #endif | |
| 669 | |
| 670 #ifdef TARGET_64BIT | |
| 671 #define MASK_64BIT OPTION_MASK_64BIT | |
| 672 #endif | |
| 673 | |
| 674 #ifdef TARGET_LITTLE_ENDIAN | |
| 675 #define MASK_LITTLE_ENDIAN OPTION_MASK_LITTLE_ENDIAN | |
| 676 #endif | |
| 677 | |
| 678 #ifdef TARGET_REGNAMES | |
| 679 #define MASK_REGNAMES OPTION_MASK_REGNAMES | |
| 680 #endif | |
| 681 | |
| 682 #ifdef TARGET_PROTOTYPE | |
| 683 #define MASK_PROTOTYPE OPTION_MASK_PROTOTYPE | |
| 684 #endif | |
| 685 | |
| 686 #ifdef TARGET_MODULO | |
| 687 #define RS6000_BTM_MODULO OPTION_MASK_MODULO | |
| 688 #endif | |
| 689 | |
| 690 | |
| 691 /* For power systems, we want to enable Altivec and VSX builtins even if the | |
| 692 user did not use -maltivec or -mvsx to allow the builtins to be used inside | |
| 693 of #pragma GCC target or the target attribute to change the code level for a | |
| 694 given system. The Paired builtins are only enabled if you configure the | |
| 695 compiler for those builtins, and those machines don't support altivec or | |
| 696 VSX. */ | |
| 697 | |
| 698 #define TARGET_EXTRA_BUILTINS (!TARGET_PAIRED_FLOAT \ | |
| 699 && ((TARGET_POWERPC64 \ | |
| 700 || TARGET_PPC_GPOPT /* 970/power4 */ \ | |
| 701 || TARGET_POPCNTB /* ISA 2.02 */ \ | |
| 702 || TARGET_CMPB /* ISA 2.05 */ \ | |
| 703 || TARGET_POPCNTD /* ISA 2.06 */ \ | |
| 704 || TARGET_ALTIVEC \ | |
| 705 || TARGET_VSX \ | |
| 706 || TARGET_HARD_FLOAT))) | |
| 707 | |
| 708 /* E500 cores only support plain "sync", not lwsync. */ | |
| 709 #define TARGET_NO_LWSYNC (rs6000_cpu == PROCESSOR_PPC8540 \ | |
| 710 || rs6000_cpu == PROCESSOR_PPC8548) | |
| 711 | |
| 712 | |
| 713 /* Whether SF/DF operations are supported by the normal floating point unit | |
| 714 (or the vector/scalar unit). */ | |
| 715 #define TARGET_SF_FPR (TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT) | |
| 716 #define TARGET_DF_FPR (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT) | |
| 717 | |
| 718 /* Whether SF/DF operations are supported by any hardware. */ | |
| 719 #define TARGET_SF_INSN TARGET_SF_FPR | |
| 720 #define TARGET_DF_INSN TARGET_DF_FPR | |
| 0 | 721 |
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722 /* Which machine supports the various reciprocal estimate instructions. */ |
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723 #define TARGET_FRES (TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT \ |
| 111 | 724 && TARGET_SINGLE_FLOAT) |
| 725 | |
| 726 #define TARGET_FRE (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT \ | |
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727 && (TARGET_POPCNTB || VECTOR_UNIT_VSX_P (DFmode))) |
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728 |
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729 #define TARGET_FRSQRTES (TARGET_HARD_FLOAT && TARGET_POPCNTB \ |
| 111 | 730 && TARGET_PPC_GFXOPT && TARGET_SINGLE_FLOAT) |
| 731 | |
| 732 #define TARGET_FRSQRTE (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT \ | |
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733 && (TARGET_PPC_GFXOPT || VECTOR_UNIT_VSX_P (DFmode))) |
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734 |
| 111 | 735 /* Conditions to allow TOC fusion for loading/storing integers. */ |
| 736 #define TARGET_TOC_FUSION_INT (TARGET_P8_FUSION \ | |
| 737 && TARGET_TOC_FUSION \ | |
| 738 && (TARGET_CMODEL != CMODEL_SMALL) \ | |
| 739 && TARGET_POWERPC64) | |
| 740 | |
| 741 /* Conditions to allow TOC fusion for loading/storing floating point. */ | |
| 742 #define TARGET_TOC_FUSION_FP (TARGET_P9_FUSION \ | |
| 743 && TARGET_TOC_FUSION \ | |
| 744 && (TARGET_CMODEL != CMODEL_SMALL) \ | |
| 745 && TARGET_POWERPC64 \ | |
| 746 && TARGET_HARD_FLOAT \ | |
| 747 && TARGET_SINGLE_FLOAT \ | |
| 748 && TARGET_DOUBLE_FLOAT) | |
| 749 | |
| 750 /* Macro to say whether we can do optimizations where we need to do parts of | |
| 751 the calculation in 64-bit GPRs and then is transfered to the vector | |
| 752 registers. Do not allow -maltivec=be for these optimizations, because it | |
| 753 adds to the complexity of the code. */ | |
| 754 #define TARGET_DIRECT_MOVE_64BIT (TARGET_DIRECT_MOVE \ | |
| 755 && TARGET_P8_VECTOR \ | |
| 756 && TARGET_POWERPC64 \ | |
| 757 && (rs6000_altivec_element_order != 2)) | |
| 758 | |
|
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759 /* Whether the various reciprocal divide/square root estimate instructions |
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760 exist, and whether we should automatically generate code for the instruction |
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761 by default. */ |
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762 #define RS6000_RECIP_MASK_HAVE_RE 0x1 /* have RE instruction. */ |
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763 #define RS6000_RECIP_MASK_AUTO_RE 0x2 /* generate RE by default. */ |
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764 #define RS6000_RECIP_MASK_HAVE_RSQRTE 0x4 /* have RSQRTE instruction. */ |
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765 #define RS6000_RECIP_MASK_AUTO_RSQRTE 0x8 /* gen. RSQRTE by default. */ |
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766 |
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767 extern unsigned char rs6000_recip_bits[]; |
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768 |
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769 #define RS6000_RECIP_HAVE_RE_P(MODE) \ |
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770 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_HAVE_RE) |
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771 |
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772 #define RS6000_RECIP_AUTO_RE_P(MODE) \ |
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773 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_AUTO_RE) |
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774 |
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775 #define RS6000_RECIP_HAVE_RSQRTE_P(MODE) \ |
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776 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_HAVE_RSQRTE) |
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777 |
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778 #define RS6000_RECIP_AUTO_RSQRTE_P(MODE) \ |
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779 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_AUTO_RSQRTE) |
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780 |
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781 /* The default CPU for TARGET_OPTION_OVERRIDE. */ |
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782 #define OPTION_TARGET_CPU_DEFAULT TARGET_CPU_DEFAULT |
| 0 | 783 |
| 784 /* Target pragma. */ | |
| 785 #define REGISTER_TARGET_PRAGMAS() do { \ | |
| 786 c_register_pragma (0, "longcall", rs6000_pragma_longcall); \ | |
|
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787 targetm.target_option.pragma_parse = rs6000_pragma_target_parse; \ |
| 0 | 788 targetm.resolve_overloaded_builtin = altivec_resolve_overloaded_builtin; \ |
| 111 | 789 rs6000_target_modify_macros_ptr = rs6000_target_modify_macros; \ |
| 0 | 790 } while (0) |
| 791 | |
| 792 /* Target #defines. */ | |
| 793 #define TARGET_CPU_CPP_BUILTINS() \ | |
| 794 rs6000_cpu_cpp_builtins (pfile) | |
| 795 | |
| 796 /* This is used by rs6000_cpu_cpp_builtins to indicate the byte order | |
| 797 we're compiling for. Some configurations may need to override it. */ | |
| 798 #define RS6000_CPU_CPP_ENDIAN_BUILTINS() \ | |
| 799 do \ | |
| 800 { \ | |
| 801 if (BYTES_BIG_ENDIAN) \ | |
| 802 { \ | |
| 803 builtin_define ("__BIG_ENDIAN__"); \ | |
| 804 builtin_define ("_BIG_ENDIAN"); \ | |
| 805 builtin_assert ("machine=bigendian"); \ | |
| 806 } \ | |
| 807 else \ | |
| 808 { \ | |
| 809 builtin_define ("__LITTLE_ENDIAN__"); \ | |
| 810 builtin_define ("_LITTLE_ENDIAN"); \ | |
| 811 builtin_assert ("machine=littleendian"); \ | |
| 812 } \ | |
| 813 } \ | |
| 814 while (0) | |
| 815 | |
| 816 /* Target machine storage layout. */ | |
| 817 | |
| 818 /* Define this macro if it is advisable to hold scalars in registers | |
| 819 in a wider mode than that declared by the program. In such cases, | |
| 820 the value is constrained to be within the bounds of the declared | |
| 821 type, but kept valid in the wider mode. The signedness of the | |
| 822 extension may differ from that of the type. */ | |
| 823 | |
| 824 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \ | |
| 825 if (GET_MODE_CLASS (MODE) == MODE_INT \ | |
| 111 | 826 && GET_MODE_SIZE (MODE) < (TARGET_32BIT ? 4 : 8)) \ |
| 0 | 827 (MODE) = TARGET_32BIT ? SImode : DImode; |
| 828 | |
| 829 /* Define this if most significant bit is lowest numbered | |
| 830 in instructions that operate on numbered bit-fields. */ | |
| 831 /* That is true on RS/6000. */ | |
| 832 #define BITS_BIG_ENDIAN 1 | |
| 833 | |
| 834 /* Define this if most significant byte of a word is the lowest numbered. */ | |
| 835 /* That is true on RS/6000. */ | |
| 836 #define BYTES_BIG_ENDIAN 1 | |
| 837 | |
| 838 /* Define this if most significant word of a multiword number is lowest | |
| 839 numbered. | |
| 840 | |
| 841 For RS/6000 we can decide arbitrarily since there are no machine | |
| 842 instructions for them. Might as well be consistent with bits and bytes. */ | |
| 843 #define WORDS_BIG_ENDIAN 1 | |
| 844 | |
| 111 | 845 /* This says that for the IBM long double the larger magnitude double |
| 846 comes first. It's really a two element double array, and arrays | |
| 847 don't index differently between little- and big-endian. */ | |
| 848 #define LONG_DOUBLE_LARGE_FIRST 1 | |
| 849 | |
| 0 | 850 #define MAX_BITS_PER_WORD 64 |
| 851 | |
| 852 /* Width of a word, in units (bytes). */ | |
| 853 #define UNITS_PER_WORD (! TARGET_POWERPC64 ? 4 : 8) | |
| 854 #ifdef IN_LIBGCC2 | |
| 855 #define MIN_UNITS_PER_WORD UNITS_PER_WORD | |
| 856 #else | |
| 857 #define MIN_UNITS_PER_WORD 4 | |
| 858 #endif | |
| 859 #define UNITS_PER_FP_WORD 8 | |
| 860 #define UNITS_PER_ALTIVEC_WORD 16 | |
|
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861 #define UNITS_PER_VSX_WORD 16 |
| 0 | 862 #define UNITS_PER_PAIRED_WORD 8 |
| 863 | |
| 864 /* Type used for ptrdiff_t, as a string used in a declaration. */ | |
| 865 #define PTRDIFF_TYPE "int" | |
| 866 | |
| 867 /* Type used for size_t, as a string used in a declaration. */ | |
| 868 #define SIZE_TYPE "long unsigned int" | |
| 869 | |
| 870 /* Type used for wchar_t, as a string used in a declaration. */ | |
| 871 #define WCHAR_TYPE "short unsigned int" | |
| 872 | |
| 873 /* Width of wchar_t in bits. */ | |
| 874 #define WCHAR_TYPE_SIZE 16 | |
| 875 | |
| 876 /* A C expression for the size in bits of the type `short' on the | |
| 877 target machine. If you don't define this, the default is half a | |
| 878 word. (If this would be less than one storage unit, it is | |
| 879 rounded up to one unit.) */ | |
| 880 #define SHORT_TYPE_SIZE 16 | |
| 881 | |
| 882 /* A C expression for the size in bits of the type `int' on the | |
| 883 target machine. If you don't define this, the default is one | |
| 884 word. */ | |
| 885 #define INT_TYPE_SIZE 32 | |
| 886 | |
| 887 /* A C expression for the size in bits of the type `long' on the | |
| 888 target machine. If you don't define this, the default is one | |
| 889 word. */ | |
| 890 #define LONG_TYPE_SIZE (TARGET_32BIT ? 32 : 64) | |
| 891 | |
| 892 /* A C expression for the size in bits of the type `long long' on the | |
| 893 target machine. If you don't define this, the default is two | |
| 894 words. */ | |
| 895 #define LONG_LONG_TYPE_SIZE 64 | |
| 896 | |
| 897 /* A C expression for the size in bits of the type `float' on the | |
| 898 target machine. If you don't define this, the default is one | |
| 899 word. */ | |
| 900 #define FLOAT_TYPE_SIZE 32 | |
| 901 | |
| 902 /* A C expression for the size in bits of the type `double' on the | |
| 903 target machine. If you don't define this, the default is two | |
| 904 words. */ | |
| 905 #define DOUBLE_TYPE_SIZE 64 | |
| 906 | |
| 907 /* A C expression for the size in bits of the type `long double' on | |
| 908 the target machine. If you don't define this, the default is two | |
| 909 words. */ | |
| 910 #define LONG_DOUBLE_TYPE_SIZE rs6000_long_double_type_size | |
| 911 | |
| 912 /* Work around rs6000_long_double_type_size dependency in ada/targtyps.c. */ | |
| 913 #define WIDEST_HARDWARE_FP_SIZE 64 | |
| 914 | |
| 915 /* Width in bits of a pointer. | |
| 916 See also the macro `Pmode' defined below. */ | |
|
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917 extern unsigned rs6000_pointer_size; |
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918 #define POINTER_SIZE rs6000_pointer_size |
| 0 | 919 |
| 920 /* Allocation boundary (in *bits*) for storing arguments in argument list. */ | |
| 921 #define PARM_BOUNDARY (TARGET_32BIT ? 32 : 64) | |
| 922 | |
| 923 /* Boundary (in *bits*) on which stack pointer should be aligned. */ | |
|
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924 #define STACK_BOUNDARY \ |
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925 ((TARGET_32BIT && !TARGET_ALTIVEC && !TARGET_ALTIVEC_ABI && !TARGET_VSX) \ |
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926 ? 64 : 128) |
| 0 | 927 |
| 928 /* Allocation boundary (in *bits*) for the code of a function. */ | |
| 929 #define FUNCTION_BOUNDARY 32 | |
| 930 | |
| 931 /* No data type wants to be aligned rounder than this. */ | |
| 932 #define BIGGEST_ALIGNMENT 128 | |
| 933 | |
| 934 /* Alignment of field after `int : 0' in a structure. */ | |
| 935 #define EMPTY_FIELD_BOUNDARY 32 | |
| 936 | |
| 937 /* Every structure's size must be a multiple of this. */ | |
| 938 #define STRUCTURE_SIZE_BOUNDARY 8 | |
| 939 | |
| 940 /* A bit-field declared as `int' forces `int' alignment for the struct. */ | |
| 941 #define PCC_BITFIELD_TYPE_MATTERS 1 | |
| 942 | |
| 111 | 943 enum data_align { align_abi, align_opt, align_both }; |
| 944 | |
| 945 /* A C expression to compute the alignment for a variables in the | |
| 946 local store. TYPE is the data type, and ALIGN is the alignment | |
| 947 that the object would ordinarily have. */ | |
| 948 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \ | |
| 949 rs6000_data_alignment (TYPE, ALIGN, align_both) | |
| 950 | |
| 951 /* Make arrays of chars word-aligned for the same reasons. */ | |
| 952 #define DATA_ALIGNMENT(TYPE, ALIGN) \ | |
| 953 rs6000_data_alignment (TYPE, ALIGN, align_opt) | |
| 954 | |
| 955 /* Align vectors to 128 bits. */ | |
| 956 #define DATA_ABI_ALIGNMENT(TYPE, ALIGN) \ | |
| 957 rs6000_data_alignment (TYPE, ALIGN, align_abi) | |
| 0 | 958 |
| 959 /* Nonzero if move instructions will actually fail to work | |
| 960 when given unaligned data. */ | |
| 961 #define STRICT_ALIGNMENT 0 | |
| 962 | |
| 963 /* Standard register usage. */ | |
| 964 | |
| 965 /* Number of actual hardware registers. | |
| 966 The hardware registers are assigned numbers for the compiler | |
| 967 from 0 to just below FIRST_PSEUDO_REGISTER. | |
| 968 All registers that the compiler knows about must be given numbers, | |
| 969 even those that are not normally considered general registers. | |
| 970 | |
| 971 RS/6000 has 32 fixed-point registers, 32 floating-point registers, | |
| 111 | 972 a count register, a link register, and 8 condition register fields, |
| 973 which we view here as separate registers. AltiVec adds 32 vector | |
| 974 registers and a VRsave register. | |
| 0 | 975 |
| 976 In addition, the difference between the frame and argument pointers is | |
| 977 a function of the number of registers saved, so we need to have a | |
| 978 register for AP that will later be eliminated in favor of SP or FP. | |
| 979 This is a normal register, but it is fixed. | |
| 980 | |
| 981 We also create a pseudo register for float/int conversions, that will | |
| 982 really represent the memory location used. It is represented here as | |
| 983 a register, in order to work around problems in allocating stack storage | |
| 984 in inline functions. | |
| 985 | |
| 986 Another pseudo (not included in DWARF_FRAME_REGISTERS) is soft frame | |
| 111 | 987 pointer, which is eventually eliminated in favor of SP or FP. |
| 988 | |
| 989 The 3 HTM registers aren't also included in DWARF_FRAME_REGISTERS. */ | |
| 990 | |
| 991 #define FIRST_PSEUDO_REGISTER 115 | |
| 0 | 992 |
| 993 /* This must be included for pre gcc 3.0 glibc compatibility. */ | |
| 994 #define PRE_GCC3_DWARF_FRAME_REGISTERS 77 | |
| 995 | |
| 111 | 996 /* The sfp register and 3 HTM registers |
| 997 aren't included in DWARF_FRAME_REGISTERS. */ | |
| 998 #define DWARF_FRAME_REGISTERS (FIRST_PSEUDO_REGISTER - 4) | |
| 0 | 999 |
| 1000 /* Use standard DWARF numbering for DWARF debugging information. */ | |
| 111 | 1001 #define DBX_REGISTER_NUMBER(REGNO) rs6000_dbx_register_number ((REGNO), 0) |
| 0 | 1002 |
| 1003 /* Use gcc hard register numbering for eh_frame. */ | |
| 1004 #define DWARF_FRAME_REGNUM(REGNO) (REGNO) | |
| 1005 | |
| 1006 /* Map register numbers held in the call frame info that gcc has | |
| 1007 collected using DWARF_FRAME_REGNUM to those that should be output in | |
| 111 | 1008 .debug_frame and .eh_frame. */ |
| 1009 #define DWARF2_FRAME_REG_OUT(REGNO, FOR_EH) \ | |
| 1010 rs6000_dbx_register_number ((REGNO), (FOR_EH)? 2 : 1) | |
| 0 | 1011 |
| 1012 /* 1 for registers that have pervasive standard uses | |
| 1013 and are not available for the register allocator. | |
| 1014 | |
| 1015 On RS/6000, r1 is used for the stack. On Darwin, r2 is available | |
| 1016 as a local register; for all other OS's r2 is the TOC pointer. | |
| 1017 | |
| 1018 On System V implementations, r13 is fixed and not available for use. */ | |
| 1019 | |
| 1020 #define FIXED_REGISTERS \ | |
| 1021 {0, 1, FIXED_R2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, FIXED_R13, 0, 0, \ | |
| 1022 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
| 1023 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
| 1024 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
| 111 | 1025 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ |
| 0 | 1026 /* AltiVec registers. */ \ |
| 1027 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
| 1028 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
| 1029 1, 1 \ | |
| 111 | 1030 , 1, 1, 1, 1 \ |
| 0 | 1031 } |
| 1032 | |
| 1033 /* 1 for registers not available across function calls. | |
| 1034 These must include the FIXED_REGISTERS and also any | |
| 1035 registers that can be used without being saved. | |
| 1036 The latter must include the registers where values are returned | |
| 1037 and the register where structure-value addresses are passed. | |
| 1038 Aside from that, you can include as many other registers as you like. */ | |
| 1039 | |
| 1040 #define CALL_USED_REGISTERS \ | |
| 1041 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \ | |
| 1042 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
| 1043 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \ | |
| 1044 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
| 1045 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \ | |
| 1046 /* AltiVec registers. */ \ | |
| 1047 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
| 1048 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
| 1049 1, 1 \ | |
| 111 | 1050 , 1, 1, 1, 1 \ |
| 0 | 1051 } |
| 1052 | |
| 1053 /* Like `CALL_USED_REGISTERS' except this macro doesn't require that | |
| 1054 the entire set of `FIXED_REGISTERS' be included. | |
| 1055 (`CALL_USED_REGISTERS' must be a superset of `FIXED_REGISTERS'). | |
| 1056 This macro is optional. If not specified, it defaults to the value | |
| 1057 of `CALL_USED_REGISTERS'. */ | |
| 1058 | |
| 1059 #define CALL_REALLY_USED_REGISTERS \ | |
| 1060 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \ | |
| 1061 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
| 1062 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \ | |
| 1063 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
| 111 | 1064 0, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \ |
| 0 | 1065 /* AltiVec registers. */ \ |
| 1066 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
| 1067 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
| 1068 0, 0 \ | |
| 111 | 1069 , 0, 0, 0, 0 \ |
| 0 | 1070 } |
| 1071 | |
| 1072 #define TOTAL_ALTIVEC_REGS (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1) | |
| 1073 | |
| 1074 #define FIRST_SAVED_ALTIVEC_REGNO (FIRST_ALTIVEC_REGNO+20) | |
| 111 | 1075 #define FIRST_SAVED_FP_REGNO (14+32) |
| 1076 #define FIRST_SAVED_GP_REGNO (FIXED_R13 ? 14 : 13) | |
| 0 | 1077 |
| 1078 /* List the order in which to allocate registers. Each register must be | |
| 1079 listed once, even those in FIXED_REGISTERS. | |
| 1080 | |
| 1081 We allocate in the following order: | |
| 1082 fp0 (not saved or used for anything) | |
| 1083 fp13 - fp2 (not saved; incoming fp arg registers) | |
| 1084 fp1 (not saved; return value) | |
| 1085 fp31 - fp14 (saved; order given to save least number) | |
| 111 | 1086 cr7, cr5 (not saved or special) |
| 1087 cr6 (not saved, but used for vector operations) | |
| 0 | 1088 cr1 (not saved, but used for FP operations) |
| 1089 cr0 (not saved, but used for arithmetic operations) | |
| 1090 cr4, cr3, cr2 (saved) | |
| 111 | 1091 r9 (not saved; best for TImode) |
| 1092 r10, r8-r4 (not saved; highest first for less conflict with params) | |
| 1093 r3 (not saved; return value register) | |
| 1094 r11 (not saved; later alloc to help shrink-wrap) | |
| 0 | 1095 r0 (not saved; cannot be base reg) |
| 1096 r31 - r13 (saved; order given to save least number) | |
| 1097 r12 (not saved; if used for DImode or DFmode would use r13) | |
| 1098 ctr (not saved; when we have the choice ctr is better) | |
| 1099 lr (saved) | |
| 111 | 1100 r1, r2, ap, ca (fixed) |
| 0 | 1101 v0 - v1 (not saved or used for anything) |
| 1102 v13 - v3 (not saved; incoming vector arg registers) | |
| 1103 v2 (not saved; incoming vector arg reg; return value) | |
| 1104 v19 - v14 (not saved or used for anything) | |
| 1105 v31 - v20 (saved; order given to save least number) | |
| 1106 vrsave, vscr (fixed) | |
| 1107 sfp (fixed) | |
| 111 | 1108 tfhar (fixed) |
| 1109 tfiar (fixed) | |
| 1110 texasr (fixed) | |
| 0 | 1111 */ |
| 1112 | |
| 1113 #if FIXED_R2 == 1 | |
| 1114 #define MAYBE_R2_AVAILABLE | |
| 1115 #define MAYBE_R2_FIXED 2, | |
| 1116 #else | |
| 1117 #define MAYBE_R2_AVAILABLE 2, | |
| 1118 #define MAYBE_R2_FIXED | |
| 1119 #endif | |
| 1120 | |
| 111 | 1121 #if FIXED_R13 == 1 |
| 1122 #define EARLY_R12 12, | |
| 1123 #define LATE_R12 | |
| 1124 #else | |
| 1125 #define EARLY_R12 | |
| 1126 #define LATE_R12 12, | |
| 1127 #endif | |
| 1128 | |
| 0 | 1129 #define REG_ALLOC_ORDER \ |
| 1130 {32, \ | |
| 111 | 1131 /* move fr13 (ie 45) later, so if we need TFmode, it does */ \ |
| 1132 /* not use fr14 which is a saved register. */ \ | |
| 1133 44, 43, 42, 41, 40, 39, 38, 37, 36, 35, 34, 45, \ | |
| 0 | 1134 33, \ |
| 1135 63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, \ | |
| 1136 50, 49, 48, 47, 46, \ | |
| 111 | 1137 75, 73, 74, 69, 68, 72, 71, 70, \ |
| 1138 MAYBE_R2_AVAILABLE \ | |
| 1139 9, 10, 8, 7, 6, 5, 4, \ | |
| 1140 3, EARLY_R12 11, 0, \ | |
| 0 | 1141 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, \ |
| 111 | 1142 18, 17, 16, 15, 14, 13, LATE_R12 \ |
| 1143 66, 65, \ | |
| 1144 1, MAYBE_R2_FIXED 67, 76, \ | |
| 0 | 1145 /* AltiVec registers. */ \ |
| 1146 77, 78, \ | |
| 1147 90, 89, 88, 87, 86, 85, 84, 83, 82, 81, 80, \ | |
| 1148 79, \ | |
| 1149 96, 95, 94, 93, 92, 91, \ | |
| 1150 108, 107, 106, 105, 104, 103, 102, 101, 100, 99, 98, 97, \ | |
| 1151 109, 110, \ | |
| 111 | 1152 111, 112, 113, 114 \ |
| 0 | 1153 } |
| 1154 | |
| 1155 /* True if register is floating-point. */ | |
| 1156 #define FP_REGNO_P(N) ((N) >= 32 && (N) <= 63) | |
| 1157 | |
| 1158 /* True if register is a condition register. */ | |
| 1159 #define CR_REGNO_P(N) ((N) >= CR0_REGNO && (N) <= CR7_REGNO) | |
| 1160 | |
| 1161 /* True if register is a condition register, but not cr0. */ | |
| 1162 #define CR_REGNO_NOT_CR0_P(N) ((N) >= CR1_REGNO && (N) <= CR7_REGNO) | |
| 1163 | |
| 1164 /* True if register is an integer register. */ | |
| 1165 #define INT_REGNO_P(N) \ | |
| 1166 ((N) <= 31 || (N) == ARG_POINTER_REGNUM || (N) == FRAME_POINTER_REGNUM) | |
| 1167 | |
| 1168 /* PAIRED SIMD registers are just the FPRs. */ | |
| 1169 #define PAIRED_SIMD_REGNO_P(N) ((N) >= 32 && (N) <= 63) | |
| 1170 | |
|
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1171 /* True if register is the CA register. */ |
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1172 #define CA_REGNO_P(N) ((N) == CA_REGNO) |
| 0 | 1173 |
| 1174 /* True if register is an AltiVec register. */ | |
| 1175 #define ALTIVEC_REGNO_P(N) ((N) >= FIRST_ALTIVEC_REGNO && (N) <= LAST_ALTIVEC_REGNO) | |
| 1176 | |
|
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1177 /* True if register is a VSX register. */ |
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1178 #define VSX_REGNO_P(N) (FP_REGNO_P (N) || ALTIVEC_REGNO_P (N)) |
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1179 |
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1180 /* Alternate name for any vector register supporting floating point, no matter |
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1181 which instruction set(s) are available. */ |
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1182 #define VFLOAT_REGNO_P(N) \ |
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1183 (ALTIVEC_REGNO_P (N) || (TARGET_VSX && FP_REGNO_P (N))) |
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1184 |
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1185 /* Alternate name for any vector register supporting integer, no matter which |
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1186 instruction set(s) are available. */ |
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1187 #define VINT_REGNO_P(N) ALTIVEC_REGNO_P (N) |
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1188 |
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1189 /* Alternate name for any vector register supporting logical operations, no |
| 111 | 1190 matter which instruction set(s) are available. Allow GPRs as well as the |
| 1191 vector registers. */ | |
| 1192 #define VLOGICAL_REGNO_P(N) \ | |
| 1193 (INT_REGNO_P (N) || ALTIVEC_REGNO_P (N) \ | |
| 1194 || (TARGET_VSX && FP_REGNO_P (N))) \ | |
|
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1195 |
|
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1196 /* When setting up caller-save slots (MODE == VOIDmode) ensure we allocate |
| 111 | 1197 enough space to account for vectors in FP regs. However, TFmode/TDmode |
| 1198 should not use VSX instructions to do a caller save. */ | |
| 1199 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ | |
| 1200 ((NREGS) <= rs6000_hard_regno_nregs[MODE][REGNO] \ | |
| 1201 ? (MODE) \ | |
| 1202 : TARGET_VSX \ | |
| 1203 && ((MODE) == VOIDmode || ALTIVEC_OR_VSX_VECTOR_MODE (MODE)) \ | |
| 1204 && FP_REGNO_P (REGNO) \ | |
| 1205 ? V2DFmode \ | |
| 1206 : FLOAT128_IBM_P (MODE) && FP_REGNO_P (REGNO) \ | |
| 1207 ? DFmode \ | |
| 1208 : (MODE) == TDmode && FP_REGNO_P (REGNO) \ | |
| 1209 ? DImode \ | |
|
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1210 : choose_hard_reg_mode ((REGNO), (NREGS), false)) |
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1211 |
|
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1212 #define VSX_VECTOR_MODE(MODE) \ |
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1213 ((MODE) == V4SFmode \ |
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1214 || (MODE) == V2DFmode) \ |
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1215 |
| 111 | 1216 /* Note KFmode and possibly TFmode (i.e. IEEE 128-bit floating point) are not |
| 1217 really a vector, but we want to treat it as a vector for moves, and | |
| 1218 such. */ | |
| 1219 | |
| 1220 #define ALTIVEC_VECTOR_MODE(MODE) \ | |
| 1221 ((MODE) == V16QImode \ | |
| 1222 || (MODE) == V8HImode \ | |
| 1223 || (MODE) == V4SFmode \ | |
| 1224 || (MODE) == V4SImode \ | |
| 1225 || FLOAT128_VECTOR_P (MODE)) | |
| 1226 | |
| 1227 #define ALTIVEC_OR_VSX_VECTOR_MODE(MODE) \ | |
| 1228 (ALTIVEC_VECTOR_MODE (MODE) || VSX_VECTOR_MODE (MODE) \ | |
| 1229 || (MODE) == V2DImode || (MODE) == V1TImode) | |
| 0 | 1230 |
| 1231 #define PAIRED_VECTOR_MODE(MODE) \ | |
| 1232 ((MODE) == V2SFmode) | |
| 1233 | |
| 1234 /* Post-reload, we can't use any new AltiVec registers, as we already | |
| 1235 emitted the vrsave mask. */ | |
| 1236 | |
| 1237 #define HARD_REGNO_RENAME_OK(SRC, DST) \ | |
| 1238 (! ALTIVEC_REGNO_P (DST) || df_regs_ever_live_p (DST)) | |
| 1239 | |
| 1240 /* Specify the cost of a branch insn; roughly the number of extra insns that | |
| 1241 should be added to avoid a branch. | |
| 1242 | |
| 1243 Set this to 3 on the RS/6000 since that is roughly the average cost of an | |
| 1244 unscheduled conditional branch. */ | |
| 1245 | |
| 1246 #define BRANCH_COST(speed_p, predictable_p) 3 | |
| 1247 | |
| 1248 /* Override BRANCH_COST heuristic which empirically produces worse | |
| 1249 performance for removing short circuiting from the logical ops. */ | |
| 1250 | |
| 1251 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0 | |
| 1252 | |
| 1253 /* Specify the registers used for certain standard purposes. | |
| 1254 The values of these macros are register numbers. */ | |
| 1255 | |
| 1256 /* RS/6000 pc isn't overloaded on a register that the compiler knows about. */ | |
| 1257 /* #define PC_REGNUM */ | |
| 1258 | |
| 1259 /* Register to use for pushing function arguments. */ | |
| 1260 #define STACK_POINTER_REGNUM 1 | |
| 1261 | |
| 1262 /* Base register for access to local variables of the function. */ | |
| 1263 #define HARD_FRAME_POINTER_REGNUM 31 | |
| 1264 | |
| 1265 /* Base register for access to local variables of the function. */ | |
| 111 | 1266 #define FRAME_POINTER_REGNUM 111 |
| 0 | 1267 |
| 1268 /* Base register for access to arguments of the function. */ | |
| 1269 #define ARG_POINTER_REGNUM 67 | |
| 1270 | |
| 1271 /* Place to put static chain when calling a function that requires it. */ | |
| 1272 #define STATIC_CHAIN_REGNUM 11 | |
| 1273 | |
| 111 | 1274 /* Base register for access to thread local storage variables. */ |
| 1275 #define TLS_REGNUM ((TARGET_64BIT) ? 13 : 2) | |
| 1276 | |
| 0 | 1277 |
| 1278 /* Define the classes of registers for register constraints in the | |
| 1279 machine description. Also define ranges of constants. | |
| 1280 | |
| 1281 One of the classes must always be named ALL_REGS and include all hard regs. | |
| 1282 If there is more than one class, another class must be named NO_REGS | |
| 1283 and contain no registers. | |
| 1284 | |
| 1285 The name GENERAL_REGS must be the name of a class (or an alias for | |
| 1286 another name such as ALL_REGS). This is the class of registers | |
| 1287 that is allowed by "g" or "r" in a register constraint. | |
| 1288 Also, registers outside this class are allocated only when | |
| 1289 instructions express preferences for them. | |
| 1290 | |
| 1291 The classes must be numbered in nondecreasing order; that is, | |
| 1292 a larger-numbered class must never be contained completely | |
| 1293 in a smaller-numbered class. | |
| 1294 | |
| 1295 For any two classes, it is very desirable that there be another | |
| 1296 class that represents their union. */ | |
| 1297 | |
|
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1298 /* The RS/6000 has three types of registers, fixed-point, floating-point, and |
| 111 | 1299 condition registers, plus three special registers, CTR, and the link |
|
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1300 register. AltiVec adds a vector register class. VSX registers overlap the |
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1301 FPR registers and the Altivec registers. |
| 0 | 1302 |
| 1303 However, r0 is special in that it cannot be used as a base register. | |
| 1304 So make a class for registers valid as base registers. | |
| 1305 | |
| 1306 Also, cr0 is the only condition code register that can be used in | |
| 1307 arithmetic insns, so make a separate class for it. */ | |
| 1308 | |
| 1309 enum reg_class | |
| 1310 { | |
| 1311 NO_REGS, | |
| 1312 BASE_REGS, | |
| 1313 GENERAL_REGS, | |
| 1314 FLOAT_REGS, | |
| 1315 ALTIVEC_REGS, | |
|
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1316 VSX_REGS, |
| 0 | 1317 VRSAVE_REGS, |
| 1318 VSCR_REGS, | |
| 111 | 1319 SPR_REGS, |
| 0 | 1320 NON_SPECIAL_REGS, |
| 1321 LINK_REGS, | |
| 1322 CTR_REGS, | |
| 1323 LINK_OR_CTR_REGS, | |
| 1324 SPECIAL_REGS, | |
| 1325 SPEC_OR_GEN_REGS, | |
| 1326 CR0_REGS, | |
| 1327 CR_REGS, | |
| 1328 NON_FLOAT_REGS, | |
|
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1329 CA_REGS, |
| 0 | 1330 ALL_REGS, |
| 1331 LIM_REG_CLASSES | |
| 1332 }; | |
| 1333 | |
| 1334 #define N_REG_CLASSES (int) LIM_REG_CLASSES | |
| 1335 | |
| 1336 /* Give names of register classes as strings for dump file. */ | |
| 1337 | |
| 1338 #define REG_CLASS_NAMES \ | |
| 1339 { \ | |
| 1340 "NO_REGS", \ | |
| 1341 "BASE_REGS", \ | |
| 1342 "GENERAL_REGS", \ | |
| 1343 "FLOAT_REGS", \ | |
| 1344 "ALTIVEC_REGS", \ | |
|
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1345 "VSX_REGS", \ |
| 0 | 1346 "VRSAVE_REGS", \ |
| 1347 "VSCR_REGS", \ | |
| 111 | 1348 "SPR_REGS", \ |
| 0 | 1349 "NON_SPECIAL_REGS", \ |
| 1350 "LINK_REGS", \ | |
| 1351 "CTR_REGS", \ | |
| 1352 "LINK_OR_CTR_REGS", \ | |
| 1353 "SPECIAL_REGS", \ | |
| 1354 "SPEC_OR_GEN_REGS", \ | |
| 1355 "CR0_REGS", \ | |
| 1356 "CR_REGS", \ | |
| 1357 "NON_FLOAT_REGS", \ | |
|
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1358 "CA_REGS", \ |
| 0 | 1359 "ALL_REGS" \ |
| 1360 } | |
| 1361 | |
| 1362 /* Define which registers fit in which classes. | |
| 1363 This is an initializer for a vector of HARD_REG_SET | |
| 1364 of length N_REG_CLASSES. */ | |
| 1365 | |
| 111 | 1366 #define REG_CLASS_CONTENTS \ |
| 1367 { \ | |
| 1368 /* NO_REGS. */ \ | |
| 1369 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \ | |
| 1370 /* BASE_REGS. */ \ | |
| 1371 { 0xfffffffe, 0x00000000, 0x00000008, 0x00008000 }, \ | |
| 1372 /* GENERAL_REGS. */ \ | |
| 1373 { 0xffffffff, 0x00000000, 0x00000008, 0x00008000 }, \ | |
| 1374 /* FLOAT_REGS. */ \ | |
| 1375 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000 }, \ | |
| 1376 /* ALTIVEC_REGS. */ \ | |
| 1377 { 0x00000000, 0x00000000, 0xffffe000, 0x00001fff }, \ | |
| 1378 /* VSX_REGS. */ \ | |
| 1379 { 0x00000000, 0xffffffff, 0xffffe000, 0x00001fff }, \ | |
| 1380 /* VRSAVE_REGS. */ \ | |
| 1381 { 0x00000000, 0x00000000, 0x00000000, 0x00002000 }, \ | |
| 1382 /* VSCR_REGS. */ \ | |
| 1383 { 0x00000000, 0x00000000, 0x00000000, 0x00004000 }, \ | |
| 1384 /* SPR_REGS. */ \ | |
| 1385 { 0x00000000, 0x00000000, 0x00000000, 0x00010000 }, \ | |
| 1386 /* NON_SPECIAL_REGS. */ \ | |
| 1387 { 0xffffffff, 0xffffffff, 0x00000008, 0x00008000 }, \ | |
| 1388 /* LINK_REGS. */ \ | |
| 1389 { 0x00000000, 0x00000000, 0x00000002, 0x00000000 }, \ | |
| 1390 /* CTR_REGS. */ \ | |
| 1391 { 0x00000000, 0x00000000, 0x00000004, 0x00000000 }, \ | |
| 1392 /* LINK_OR_CTR_REGS. */ \ | |
| 1393 { 0x00000000, 0x00000000, 0x00000006, 0x00000000 }, \ | |
| 1394 /* SPECIAL_REGS. */ \ | |
| 1395 { 0x00000000, 0x00000000, 0x00000006, 0x00002000 }, \ | |
| 1396 /* SPEC_OR_GEN_REGS. */ \ | |
| 1397 { 0xffffffff, 0x00000000, 0x0000000e, 0x0000a000 }, \ | |
| 1398 /* CR0_REGS. */ \ | |
| 1399 { 0x00000000, 0x00000000, 0x00000010, 0x00000000 }, \ | |
| 1400 /* CR_REGS. */ \ | |
| 1401 { 0x00000000, 0x00000000, 0x00000ff0, 0x00000000 }, \ | |
| 1402 /* NON_FLOAT_REGS. */ \ | |
| 1403 { 0xffffffff, 0x00000000, 0x00000ffe, 0x00008000 }, \ | |
| 1404 /* CA_REGS. */ \ | |
| 1405 { 0x00000000, 0x00000000, 0x00001000, 0x00000000 }, \ | |
| 1406 /* ALL_REGS. */ \ | |
| 1407 { 0xffffffff, 0xffffffff, 0xfffffffe, 0x0001ffff } \ | |
| 0 | 1408 } |
| 1409 | |
| 1410 /* The same information, inverted: | |
| 1411 Return the class number of the smallest class containing | |
| 1412 reg number REGNO. This could be a conditional expression | |
| 1413 or could index an array. */ | |
| 1414 | |
|
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1415 extern enum reg_class rs6000_regno_regclass[FIRST_PSEUDO_REGISTER]; |
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1416 |
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1417 #define REGNO_REG_CLASS(REGNO) \ |
| 111 | 1418 (gcc_checking_assert (IN_RANGE ((REGNO), 0, FIRST_PSEUDO_REGISTER-1)),\ |
|
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1419 rs6000_regno_regclass[(REGNO)]) |
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1420 |
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1421 /* Register classes for various constraints that are based on the target |
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1422 switches. */ |
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1423 enum r6000_reg_class_enum { |
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1424 RS6000_CONSTRAINT_d, /* fpr registers for double values */ |
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1425 RS6000_CONSTRAINT_f, /* fpr registers for single values */ |
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1426 RS6000_CONSTRAINT_v, /* Altivec registers */ |
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1427 RS6000_CONSTRAINT_wa, /* Any VSX register */ |
| 111 | 1428 RS6000_CONSTRAINT_wb, /* Altivec register if ISA 3.0 vector. */ |
|
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1429 RS6000_CONSTRAINT_wd, /* VSX register for V2DF */ |
| 111 | 1430 RS6000_CONSTRAINT_we, /* VSX register if ISA 3.0 vector. */ |
|
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1431 RS6000_CONSTRAINT_wf, /* VSX register for V4SF */ |
| 111 | 1432 RS6000_CONSTRAINT_wg, /* FPR register for -mmfpgpr */ |
| 1433 RS6000_CONSTRAINT_wh, /* FPR register for direct moves. */ | |
| 1434 RS6000_CONSTRAINT_wi, /* FPR/VSX register to hold DImode */ | |
| 1435 RS6000_CONSTRAINT_wj, /* FPR/VSX register for DImode direct moves. */ | |
| 1436 RS6000_CONSTRAINT_wk, /* FPR/VSX register for DFmode direct moves. */ | |
| 1437 RS6000_CONSTRAINT_wl, /* FPR register for LFIWAX */ | |
| 1438 RS6000_CONSTRAINT_wm, /* VSX register for direct move */ | |
| 1439 RS6000_CONSTRAINT_wo, /* VSX register for power9 vector. */ | |
| 1440 RS6000_CONSTRAINT_wp, /* VSX reg for IEEE 128-bit fp TFmode. */ | |
| 1441 RS6000_CONSTRAINT_wq, /* VSX reg for IEEE 128-bit fp KFmode. */ | |
| 1442 RS6000_CONSTRAINT_wr, /* GPR register if 64-bit */ | |
|
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1443 RS6000_CONSTRAINT_ws, /* VSX register for DF */ |
| 111 | 1444 RS6000_CONSTRAINT_wt, /* VSX register for TImode */ |
| 1445 RS6000_CONSTRAINT_wu, /* Altivec register for float load/stores. */ | |
| 1446 RS6000_CONSTRAINT_wv, /* Altivec register for double load/stores. */ | |
| 1447 RS6000_CONSTRAINT_ww, /* FP or VSX register for vsx float ops. */ | |
| 1448 RS6000_CONSTRAINT_wx, /* FPR register for STFIWX */ | |
| 1449 RS6000_CONSTRAINT_wy, /* VSX register for SF */ | |
| 1450 RS6000_CONSTRAINT_wz, /* FPR register for LFIWZX */ | |
| 1451 RS6000_CONSTRAINT_wA, /* BASE_REGS if 64-bit. */ | |
| 1452 RS6000_CONSTRAINT_wH, /* Altivec register for 32-bit integers. */ | |
| 1453 RS6000_CONSTRAINT_wI, /* VSX register for 32-bit integers. */ | |
| 1454 RS6000_CONSTRAINT_wJ, /* VSX register for 8/16-bit integers. */ | |
| 1455 RS6000_CONSTRAINT_wK, /* Altivec register for 16/32-bit integers. */ | |
|
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1456 RS6000_CONSTRAINT_MAX |
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1457 }; |
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1458 |
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1459 extern enum reg_class rs6000_constraints[RS6000_CONSTRAINT_MAX]; |
| 0 | 1460 |
| 1461 /* The class value for index registers, and the one for base regs. */ | |
| 1462 #define INDEX_REG_CLASS GENERAL_REGS | |
| 1463 #define BASE_REG_CLASS BASE_REGS | |
| 1464 | |
|
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1465 /* Return whether a given register class can hold VSX objects. */ |
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1466 #define VSX_REG_CLASS_P(CLASS) \ |
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1467 ((CLASS) == VSX_REGS || (CLASS) == FLOAT_REGS || (CLASS) == ALTIVEC_REGS) |
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1468 |
| 111 | 1469 /* Return whether a given register class targets general purpose registers. */ |
| 1470 #define GPR_REG_CLASS_P(CLASS) ((CLASS) == GENERAL_REGS || (CLASS) == BASE_REGS) | |
| 1471 | |
| 0 | 1472 /* Given an rtx X being reloaded into a reg required to be |
| 1473 in class CLASS, return the class of reg to actually use. | |
| 1474 In general this is just CLASS; but on some machines | |
| 1475 in some cases it is preferable to use a more restrictive class. | |
| 1476 | |
| 1477 On the RS/6000, we have to return NO_REGS when we want to reload a | |
| 1478 floating-point CONST_DOUBLE to force it to be copied to memory. | |
| 1479 | |
| 1480 We also don't want to reload integer values into floating-point | |
| 1481 registers if we can at all help it. In fact, this can | |
| 1482 cause reload to die, if it tries to generate a reload of CTR | |
| 1483 into a FP register and discovers it doesn't have the memory location | |
| 1484 required. | |
| 1485 | |
| 1486 ??? Would it be a good idea to have reload do the converse, that is | |
| 1487 try to reload floating modes into FP registers if possible? | |
| 1488 */ | |
| 1489 | |
| 1490 #define PREFERRED_RELOAD_CLASS(X,CLASS) \ | |
|
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1491 rs6000_preferred_reload_class_ptr (X, CLASS) |
| 0 | 1492 |
| 1493 /* Return the register class of a scratch register needed to copy IN into | |
| 1494 or out of a register in CLASS in MODE. If it can be done directly, | |
| 1495 NO_REGS is returned. */ | |
| 1496 | |
| 1497 #define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \ | |
|
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1498 rs6000_secondary_reload_class_ptr (CLASS, MODE, IN) |
| 0 | 1499 |
| 1500 /* Return the maximum number of consecutive registers | |
| 1501 needed to represent mode MODE in a register of class CLASS. | |
| 1502 | |
|
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1503 On RS/6000, this is the size of MODE in words, except in the FP regs, where |
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1504 a single reg is enough for two words, unless we have VSX, where the FP |
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1505 registers can hold 128 bits. */ |
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1506 #define CLASS_MAX_NREGS(CLASS, MODE) rs6000_class_max_nregs[(MODE)][(CLASS)] |
| 0 | 1507 |
| 1508 /* Stack layout; function entry, exit and calling. */ | |
| 1509 | |
| 1510 /* Define this if pushing a word on the stack | |
| 1511 makes the stack pointer a smaller address. */ | |
| 111 | 1512 #define STACK_GROWS_DOWNWARD 1 |
| 0 | 1513 |
| 1514 /* Offsets recorded in opcodes are a multiple of this alignment factor. */ | |
| 1515 #define DWARF_CIE_DATA_ALIGNMENT (-((int) (TARGET_32BIT ? 4 : 8))) | |
| 1516 | |
| 1517 /* Define this to nonzero if the nominal address of the stack frame | |
| 1518 is at the high-address end of the local variables; | |
| 1519 that is, each additional local variable allocated | |
| 1520 goes at a more negative offset in the frame. | |
| 1521 | |
| 1522 On the RS/6000, we grow upwards, from the area after the outgoing | |
| 1523 arguments. */ | |
| 111 | 1524 #define FRAME_GROWS_DOWNWARD (flag_stack_protect != 0 \ |
| 1525 || (flag_sanitize & SANITIZE_ADDRESS) != 0) | |
| 0 | 1526 |
| 1527 /* Size of the fixed area on the stack */ | |
| 1528 #define RS6000_SAVE_AREA \ | |
| 111 | 1529 ((DEFAULT_ABI == ABI_V4 ? 8 : DEFAULT_ABI == ABI_ELFv2 ? 16 : 24) \ |
| 0 | 1530 << (TARGET_64BIT ? 1 : 0)) |
| 1531 | |
| 111 | 1532 /* Stack offset for toc save slot. */ |
| 1533 #define RS6000_TOC_SAVE_SLOT \ | |
| 1534 ((DEFAULT_ABI == ABI_ELFv2 ? 12 : 20) << (TARGET_64BIT ? 1 : 0)) | |
| 0 | 1535 |
| 1536 /* Align an address */ | |
| 111 | 1537 #define RS6000_ALIGN(n,a) ROUND_UP ((n), (a)) |
| 0 | 1538 |
| 1539 /* Offset within stack frame to start allocating local variables at. | |
| 1540 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the | |
| 1541 first local allocated. Otherwise, it is the offset to the BEGINNING | |
| 1542 of the first local allocated. | |
| 1543 | |
| 1544 On the RS/6000, the frame pointer is the same as the stack pointer, | |
| 1545 except for dynamic allocations. So we start after the fixed area and | |
| 111 | 1546 outgoing parameter area. |
| 1547 | |
| 1548 If the function uses dynamic stack space (CALLS_ALLOCA is set), that | |
| 1549 space needs to be aligned to STACK_BOUNDARY, i.e. the sum of the | |
| 1550 sizes of the fixed area and the parameter area must be a multiple of | |
| 1551 STACK_BOUNDARY. */ | |
| 1552 | |
| 1553 #define RS6000_STARTING_FRAME_OFFSET \ | |
| 1554 (cfun->calls_alloca \ | |
| 1555 ? (RS6000_ALIGN (crtl->outgoing_args_size + RS6000_SAVE_AREA, \ | |
| 1556 (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8 )) \ | |
|
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1557 : (RS6000_ALIGN (crtl->outgoing_args_size, \ |
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1558 (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8) \ |
| 0 | 1559 + RS6000_SAVE_AREA)) |
| 1560 | |
| 1561 /* Offset from the stack pointer register to an item dynamically | |
| 1562 allocated on the stack, e.g., by `alloca'. | |
| 1563 | |
| 1564 The default value for this macro is `STACK_POINTER_OFFSET' plus the | |
| 1565 length of the outgoing arguments. The default is correct for most | |
| 111 | 1566 machines. See `function.c' for details. |
| 1567 | |
| 1568 This value must be a multiple of STACK_BOUNDARY (hard coded in | |
| 1569 `emit-rtl.c'). */ | |
| 0 | 1570 #define STACK_DYNAMIC_OFFSET(FUNDECL) \ |
| 111 | 1571 RS6000_ALIGN (crtl->outgoing_args_size + STACK_POINTER_OFFSET, \ |
| 1572 (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8) | |
| 0 | 1573 |
| 1574 /* If we generate an insn to push BYTES bytes, | |
| 1575 this says how many the stack pointer really advances by. | |
| 1576 On RS/6000, don't define this because there are no push insns. */ | |
| 1577 /* #define PUSH_ROUNDING(BYTES) */ | |
| 1578 | |
| 1579 /* Offset of first parameter from the argument pointer register value. | |
| 1580 On the RS/6000, we define the argument pointer to the start of the fixed | |
| 1581 area. */ | |
| 1582 #define FIRST_PARM_OFFSET(FNDECL) RS6000_SAVE_AREA | |
| 1583 | |
| 1584 /* Offset from the argument pointer register value to the top of | |
| 1585 stack. This is different from FIRST_PARM_OFFSET because of the | |
| 1586 register save area. */ | |
| 1587 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0 | |
| 1588 | |
| 1589 /* Define this if stack space is still allocated for a parameter passed | |
| 1590 in a register. The value is the number of bytes allocated to this | |
| 1591 area. */ | |
| 111 | 1592 #define REG_PARM_STACK_SPACE(FNDECL) \ |
| 1593 rs6000_reg_parm_stack_space ((FNDECL), false) | |
| 1594 | |
| 1595 /* Define this macro if space guaranteed when compiling a function body | |
| 1596 is different to space required when making a call, a situation that | |
| 1597 can arise with K&R style function definitions. */ | |
| 1598 #define INCOMING_REG_PARM_STACK_SPACE(FNDECL) \ | |
| 1599 rs6000_reg_parm_stack_space ((FNDECL), true) | |
| 0 | 1600 |
| 1601 /* Define this if the above stack space is to be considered part of the | |
| 1602 space allocated by the caller. */ | |
| 1603 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1 | |
| 1604 | |
| 1605 /* This is the difference between the logical top of stack and the actual sp. | |
| 1606 | |
| 1607 For the RS/6000, sp points past the fixed area. */ | |
| 1608 #define STACK_POINTER_OFFSET RS6000_SAVE_AREA | |
| 1609 | |
| 1610 /* Define this if the maximum size of all the outgoing args is to be | |
| 1611 accumulated and pushed during the prologue. The amount can be | |
| 1612 found in the variable crtl->outgoing_args_size. */ | |
| 1613 #define ACCUMULATE_OUTGOING_ARGS 1 | |
| 1614 | |
| 1615 /* Define how to find the value returned by a library function | |
| 1616 assuming the value has mode MODE. */ | |
| 1617 | |
| 1618 #define LIBCALL_VALUE(MODE) rs6000_libcall_value ((MODE)) | |
| 1619 | |
| 1620 /* DRAFT_V4_STRUCT_RET defaults off. */ | |
| 1621 #define DRAFT_V4_STRUCT_RET 0 | |
| 1622 | |
| 1623 /* Let TARGET_RETURN_IN_MEMORY control what happens. */ | |
| 1624 #define DEFAULT_PCC_STRUCT_RETURN 0 | |
| 1625 | |
| 1626 /* Mode of stack savearea. | |
| 1627 FUNCTION is VOIDmode because calling convention maintains SP. | |
| 1628 BLOCK needs Pmode for SP. | |
| 1629 NONLOCAL needs twice Pmode to maintain both backchain and SP. */ | |
| 1630 #define STACK_SAVEAREA_MODE(LEVEL) \ | |
| 1631 (LEVEL == SAVE_FUNCTION ? VOIDmode \ | |
| 111 | 1632 : LEVEL == SAVE_NONLOCAL ? (TARGET_32BIT ? DImode : PTImode) : Pmode) |
| 0 | 1633 |
| 1634 /* Minimum and maximum general purpose registers used to hold arguments. */ | |
| 1635 #define GP_ARG_MIN_REG 3 | |
| 1636 #define GP_ARG_MAX_REG 10 | |
| 1637 #define GP_ARG_NUM_REG (GP_ARG_MAX_REG - GP_ARG_MIN_REG + 1) | |
| 1638 | |
| 1639 /* Minimum and maximum floating point registers used to hold arguments. */ | |
| 1640 #define FP_ARG_MIN_REG 33 | |
| 1641 #define FP_ARG_AIX_MAX_REG 45 | |
| 1642 #define FP_ARG_V4_MAX_REG 40 | |
| 111 | 1643 #define FP_ARG_MAX_REG (DEFAULT_ABI == ABI_V4 \ |
| 1644 ? FP_ARG_V4_MAX_REG : FP_ARG_AIX_MAX_REG) | |
| 0 | 1645 #define FP_ARG_NUM_REG (FP_ARG_MAX_REG - FP_ARG_MIN_REG + 1) |
| 1646 | |
| 1647 /* Minimum and maximum AltiVec registers used to hold arguments. */ | |
| 1648 #define ALTIVEC_ARG_MIN_REG (FIRST_ALTIVEC_REGNO + 2) | |
| 1649 #define ALTIVEC_ARG_MAX_REG (ALTIVEC_ARG_MIN_REG + 11) | |
| 1650 #define ALTIVEC_ARG_NUM_REG (ALTIVEC_ARG_MAX_REG - ALTIVEC_ARG_MIN_REG + 1) | |
| 1651 | |
| 111 | 1652 /* Maximum number of registers per ELFv2 homogeneous aggregate argument. */ |
| 1653 #define AGGR_ARG_NUM_REG 8 | |
| 1654 | |
| 0 | 1655 /* Return registers */ |
| 1656 #define GP_ARG_RETURN GP_ARG_MIN_REG | |
| 1657 #define FP_ARG_RETURN FP_ARG_MIN_REG | |
| 1658 #define ALTIVEC_ARG_RETURN (FIRST_ALTIVEC_REGNO + 2) | |
| 111 | 1659 #define FP_ARG_MAX_RETURN (DEFAULT_ABI != ABI_ELFv2 ? FP_ARG_RETURN \ |
| 1660 : (FP_ARG_RETURN + AGGR_ARG_NUM_REG - 1)) | |
| 1661 #define ALTIVEC_ARG_MAX_RETURN (DEFAULT_ABI != ABI_ELFv2 \ | |
| 1662 ? (ALTIVEC_ARG_RETURN \ | |
| 1663 + (TARGET_FLOAT128_TYPE ? 1 : 0)) \ | |
| 1664 : (ALTIVEC_ARG_RETURN + AGGR_ARG_NUM_REG - 1)) | |
| 0 | 1665 |
| 1666 /* Flags for the call/call_value rtl operations set up by function_arg */ | |
| 1667 #define CALL_NORMAL 0x00000000 /* no special processing */ | |
| 1668 /* Bits in 0x00000001 are unused. */ | |
| 1669 #define CALL_V4_CLEAR_FP_ARGS 0x00000002 /* V.4, no FP args passed */ | |
| 1670 #define CALL_V4_SET_FP_ARGS 0x00000004 /* V.4, FP args were passed */ | |
| 1671 #define CALL_LONG 0x00000008 /* always call indirect */ | |
| 1672 #define CALL_LIBCALL 0x00000010 /* libcall */ | |
| 1673 | |
| 1674 /* We don't have prologue and epilogue functions to save/restore | |
| 1675 everything for most ABIs. */ | |
| 1676 #define WORLD_SAVE_P(INFO) 0 | |
| 1677 | |
| 1678 /* 1 if N is a possible register number for a function value | |
| 1679 as seen by the caller. | |
| 1680 | |
| 1681 On RS/6000, this is r3, fp1, and v2 (for AltiVec). */ | |
| 1682 #define FUNCTION_VALUE_REGNO_P(N) \ | |
| 1683 ((N) == GP_ARG_RETURN \ | |
| 111 | 1684 || (IN_RANGE ((N), FP_ARG_RETURN, FP_ARG_MAX_RETURN) \ |
| 1685 && TARGET_HARD_FLOAT) \ | |
| 1686 || (IN_RANGE ((N), ALTIVEC_ARG_RETURN, ALTIVEC_ARG_MAX_RETURN) \ | |
| 1687 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI)) | |
| 0 | 1688 |
| 1689 /* 1 if N is a possible register number for function argument passing. | |
| 1690 On RS/6000, these are r3-r10 and fp1-fp13. | |
| 1691 On AltiVec, v2 - v13 are used for passing vectors. */ | |
| 1692 #define FUNCTION_ARG_REGNO_P(N) \ | |
| 111 | 1693 (IN_RANGE ((N), GP_ARG_MIN_REG, GP_ARG_MAX_REG) \ |
| 1694 || (IN_RANGE ((N), ALTIVEC_ARG_MIN_REG, ALTIVEC_ARG_MAX_REG) \ | |
| 0 | 1695 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI) \ |
| 111 | 1696 || (IN_RANGE ((N), FP_ARG_MIN_REG, FP_ARG_MAX_REG) \ |
| 1697 && TARGET_HARD_FLOAT)) | |
| 0 | 1698 |
| 1699 /* Define a data type for recording info about an argument list | |
| 1700 during the scan of that argument list. This data type should | |
| 1701 hold all necessary information about the function itself | |
| 1702 and about the args processed so far, enough to enable macros | |
| 1703 such as FUNCTION_ARG to determine where the next arg should go. | |
| 1704 | |
| 1705 On the RS/6000, this is a structure. The first element is the number of | |
| 1706 total argument words, the second is used to store the next | |
| 1707 floating-point register number, and the third says how many more args we | |
| 1708 have prototype types for. | |
| 1709 | |
| 1710 For ABI_V4, we treat these slightly differently -- `sysv_gregno' is | |
| 1711 the next available GP register, `fregno' is the next available FP | |
| 1712 register, and `words' is the number of words used on the stack. | |
| 1713 | |
| 1714 The varargs/stdarg support requires that this structure's size | |
| 1715 be a multiple of sizeof(int). */ | |
| 1716 | |
| 1717 typedef struct rs6000_args | |
| 1718 { | |
| 1719 int words; /* # words used for passing GP registers */ | |
| 1720 int fregno; /* next available FP register */ | |
| 1721 int vregno; /* next available AltiVec register */ | |
| 1722 int nargs_prototype; /* # args left in the current prototype */ | |
| 1723 int prototype; /* Whether a prototype was defined */ | |
| 1724 int stdarg; /* Whether function is a stdarg function. */ | |
| 1725 int call_cookie; /* Do special things for this call */ | |
| 1726 int sysv_gregno; /* next available GP register */ | |
| 1727 int intoffset; /* running offset in struct (darwin64) */ | |
| 1728 int use_stack; /* any part of struct on stack (darwin64) */ | |
|
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1729 int floats_in_gpr; /* count of SFmode floats taking up |
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1730 GPR space (darwin64) */ |
| 0 | 1731 int named; /* false for varargs params */ |
|
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1732 int escapes; /* if function visible outside tu */ |
| 111 | 1733 int libcall; /* If this is a compiler generated call. */ |
| 0 | 1734 } CUMULATIVE_ARGS; |
| 1735 | |
| 1736 /* Initialize a variable CUM of type CUMULATIVE_ARGS | |
| 1737 for a call to a function whose data type is FNTYPE. | |
| 1738 For a library call, FNTYPE is 0. */ | |
| 1739 | |
|
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1740 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ |
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1741 init_cumulative_args (&CUM, FNTYPE, LIBNAME, FALSE, FALSE, \ |
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1742 N_NAMED_ARGS, FNDECL, VOIDmode) |
| 0 | 1743 |
| 1744 /* Similar, but when scanning the definition of a procedure. We always | |
| 1745 set NARGS_PROTOTYPE large so we never return an EXPR_LIST. */ | |
| 1746 | |
| 1747 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \ | |
|
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1748 init_cumulative_args (&CUM, FNTYPE, LIBNAME, TRUE, FALSE, \ |
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1749 1000, current_function_decl, VOIDmode) |
| 0 | 1750 |
| 1751 /* Like INIT_CUMULATIVE_ARGS' but only used for outgoing libcalls. */ | |
| 1752 | |
| 1753 #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \ | |
|
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1754 init_cumulative_args (&CUM, NULL_TREE, LIBNAME, FALSE, TRUE, \ |
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1755 0, NULL_TREE, MODE) |
| 0 | 1756 |
| 1757 #define PAD_VARARGS_DOWN \ | |
| 111 | 1758 (targetm.calls.function_arg_padding (TYPE_MODE (type), type) == PAD_DOWNWARD) |
| 0 | 1759 |
| 1760 /* Output assembler code to FILE to increment profiler label # LABELNO | |
| 1761 for profiling a function entry. */ | |
| 1762 | |
| 1763 #define FUNCTION_PROFILER(FILE, LABELNO) \ | |
| 1764 output_function_profiler ((FILE), (LABELNO)); | |
| 1765 | |
| 1766 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, | |
| 1767 the stack pointer does not matter. No definition is equivalent to | |
| 1768 always zero. | |
| 1769 | |
| 1770 On the RS/6000, this is nonzero because we can restore the stack from | |
| 1771 its backpointer, which we maintain. */ | |
| 1772 #define EXIT_IGNORE_STACK 1 | |
| 1773 | |
| 1774 /* Define this macro as a C expression that is nonzero for registers | |
| 1775 that are used by the epilogue or the return' pattern. The stack | |
| 1776 and frame pointer registers are already be assumed to be used as | |
| 1777 needed. */ | |
| 1778 | |
| 1779 #define EPILOGUE_USES(REGNO) \ | |
| 1780 ((reload_completed && (REGNO) == LR_REGNO) \ | |
| 1781 || (TARGET_ALTIVEC && (REGNO) == VRSAVE_REGNO) \ | |
|
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1782 || (crtl->calls_eh_return \ |
| 0 | 1783 && TARGET_AIX \ |
| 1784 && (REGNO) == 2)) | |
| 1785 | |
| 1786 | |
| 1787 /* Length in units of the trampoline for entering a nested function. */ | |
| 1788 | |
| 1789 #define TRAMPOLINE_SIZE rs6000_trampoline_size () | |
| 1790 | |
| 1791 /* Definitions for __builtin_return_address and __builtin_frame_address. | |
| 111 | 1792 __builtin_return_address (0) should give link register (LR_REGNO), enable |
| 0 | 1793 this. */ |
| 1794 /* This should be uncommented, so that the link register is used, but | |
| 1795 currently this would result in unmatched insns and spilling fixed | |
| 1796 registers so we'll leave it for another day. When these problems are | |
| 1797 taken care of one additional fetch will be necessary in RETURN_ADDR_RTX. | |
| 1798 (mrs) */ | |
| 1799 /* #define RETURN_ADDR_IN_PREVIOUS_FRAME */ | |
| 1800 | |
| 1801 /* Number of bytes into the frame return addresses can be found. See | |
| 1802 rs6000_stack_info in rs6000.c for more information on how the different | |
| 1803 abi's store the return address. */ | |
| 111 | 1804 #define RETURN_ADDRESS_OFFSET \ |
| 1805 ((DEFAULT_ABI == ABI_V4 ? 4 : 8) << (TARGET_64BIT ? 1 : 0)) | |
| 0 | 1806 |
| 1807 /* The current return address is in link register (65). The return address | |
| 1808 of anything farther back is accessed normally at an offset of 8 from the | |
| 1809 frame pointer. */ | |
| 1810 #define RETURN_ADDR_RTX(COUNT, FRAME) \ | |
| 1811 (rs6000_return_addr (COUNT, FRAME)) | |
| 1812 | |
| 1813 | |
| 1814 /* Definitions for register eliminations. | |
| 1815 | |
| 1816 We have two registers that can be eliminated on the RS/6000. First, the | |
| 1817 frame pointer register can often be eliminated in favor of the stack | |
| 1818 pointer register. Secondly, the argument pointer register can always be | |
| 1819 eliminated; it is replaced with either the stack or frame pointer. | |
| 1820 | |
| 1821 In addition, we use the elimination mechanism to see if r30 is needed | |
| 1822 Initially we assume that it isn't. If it is, we spill it. This is done | |
| 1823 by making it an eliminable register. We replace it with itself so that | |
| 1824 if it isn't needed, then existing uses won't be modified. */ | |
| 1825 | |
| 1826 /* This is an array of structures. Each structure initializes one pair | |
| 1827 of eliminable registers. The "from" register number is given first, | |
| 1828 followed by "to". Eliminations of the same "from" register are listed | |
| 1829 in order of preference. */ | |
| 1830 #define ELIMINABLE_REGS \ | |
| 1831 {{ HARD_FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
| 1832 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
| 1833 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ | |
| 1834 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
| 1835 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ | |
| 1836 { RS6000_PIC_OFFSET_TABLE_REGNUM, RS6000_PIC_OFFSET_TABLE_REGNUM } } | |
| 1837 | |
| 1838 /* Define the offset between two registers, one to be eliminated, and the other | |
| 1839 its replacement, at the start of a routine. */ | |
| 1840 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ | |
| 1841 ((OFFSET) = rs6000_initial_elimination_offset(FROM, TO)) | |
| 1842 | |
| 1843 /* Addressing modes, and classification of registers for them. */ | |
| 1844 | |
| 1845 #define HAVE_PRE_DECREMENT 1 | |
| 1846 #define HAVE_PRE_INCREMENT 1 | |
| 1847 #define HAVE_PRE_MODIFY_DISP 1 | |
| 1848 #define HAVE_PRE_MODIFY_REG 1 | |
| 1849 | |
| 1850 /* Macros to check register numbers against specific register classes. */ | |
| 1851 | |
| 1852 /* These assume that REGNO is a hard or pseudo reg number. | |
| 1853 They give nonzero only if REGNO is a hard reg of the suitable class | |
| 1854 or a pseudo reg currently allocated to a suitable hard reg. | |
| 1855 Since they use reg_renumber, they are safe only once reg_renumber | |
| 111 | 1856 has been allocated, which happens in reginfo.c during register |
| 1857 allocation. */ | |
| 0 | 1858 |
| 1859 #define REGNO_OK_FOR_INDEX_P(REGNO) \ | |
| 1860 ((REGNO) < FIRST_PSEUDO_REGISTER \ | |
| 1861 ? (REGNO) <= 31 || (REGNO) == 67 \ | |
| 1862 || (REGNO) == FRAME_POINTER_REGNUM \ | |
| 1863 : (reg_renumber[REGNO] >= 0 \ | |
| 1864 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67 \ | |
| 1865 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM))) | |
| 1866 | |
| 1867 #define REGNO_OK_FOR_BASE_P(REGNO) \ | |
| 1868 ((REGNO) < FIRST_PSEUDO_REGISTER \ | |
| 1869 ? ((REGNO) > 0 && (REGNO) <= 31) || (REGNO) == 67 \ | |
| 1870 || (REGNO) == FRAME_POINTER_REGNUM \ | |
| 1871 : (reg_renumber[REGNO] > 0 \ | |
| 1872 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67 \ | |
| 1873 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM))) | |
|
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1874 |
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1875 /* Nonzero if X is a hard reg that can be used as an index |
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1876 or if it is a pseudo reg in the non-strict case. */ |
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1877 #define INT_REG_OK_FOR_INDEX_P(X, STRICT) \ |
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1878 ((!(STRICT) && REGNO (X) >= FIRST_PSEUDO_REGISTER) \ |
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1879 || REGNO_OK_FOR_INDEX_P (REGNO (X))) |
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1880 |
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1881 /* Nonzero if X is a hard reg that can be used as a base reg |
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1882 or if it is a pseudo reg in the non-strict case. */ |
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1883 #define INT_REG_OK_FOR_BASE_P(X, STRICT) \ |
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1884 ((!(STRICT) && REGNO (X) >= FIRST_PSEUDO_REGISTER) \ |
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1885 || REGNO_OK_FOR_BASE_P (REGNO (X))) |
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1886 |
| 0 | 1887 |
| 1888 /* Maximum number of registers that can appear in a valid memory address. */ | |
| 1889 | |
| 1890 #define MAX_REGS_PER_ADDRESS 2 | |
| 1891 | |
| 1892 /* Recognize any constant value that is a valid address. */ | |
| 1893 | |
| 1894 #define CONSTANT_ADDRESS_P(X) \ | |
| 1895 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ | |
| 1896 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \ | |
| 1897 || GET_CODE (X) == HIGH) | |
| 1898 | |
| 1899 #define EASY_VECTOR_15(n) ((n) >= -16 && (n) <= 15) | |
| 1900 #define EASY_VECTOR_15_ADD_SELF(n) (!EASY_VECTOR_15((n)) \ | |
| 1901 && EASY_VECTOR_15((n) >> 1) \ | |
| 1902 && ((n) & 1) == 0) | |
| 1903 | |
|
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1904 #define EASY_VECTOR_MSB(n,mode) \ |
| 111 | 1905 ((((unsigned HOST_WIDE_INT) (n)) & GET_MODE_MASK (mode)) == \ |
|
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1906 ((((unsigned HOST_WIDE_INT)GET_MODE_MASK (mode)) + 1) >> 1)) |
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1907 |
| 0 | 1908 |
| 1909 /* Try a machine-dependent way of reloading an illegitimate address | |
| 1910 operand. If we find one, push the reload and jump to WIN. This | |
| 1911 macro is used in only one place: `find_reloads_address' in reload.c. | |
| 1912 | |
| 1913 Implemented on rs6000 by rs6000_legitimize_reload_address. | |
| 1914 Note that (X) is evaluated twice; this is safe in current usage. */ | |
| 1915 | |
| 1916 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \ | |
| 1917 do { \ | |
| 1918 int win; \ | |
|
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1919 (X) = rs6000_legitimize_reload_address_ptr ((X), (MODE), (OPNUM), \ |
| 0 | 1920 (int)(TYPE), (IND_LEVELS), &win); \ |
| 1921 if ( win ) \ | |
| 1922 goto WIN; \ | |
| 1923 } while (0) | |
| 1924 | |
| 1925 #define FIND_BASE_TERM rs6000_find_base_term | |
| 1926 | |
| 1927 /* The register number of the register used to address a table of | |
| 1928 static data addresses in memory. In some cases this register is | |
| 1929 defined by a processor's "application binary interface" (ABI). | |
| 1930 When this macro is defined, RTL is generated for this register | |
| 1931 once, as with the stack pointer and frame pointer registers. If | |
| 1932 this macro is not defined, it is up to the machine-dependent files | |
| 1933 to allocate such a register (if necessary). */ | |
| 1934 | |
| 1935 #define RS6000_PIC_OFFSET_TABLE_REGNUM 30 | |
| 111 | 1936 #define PIC_OFFSET_TABLE_REGNUM \ |
| 1937 (TARGET_TOC ? TOC_REGISTER \ | |
| 1938 : flag_pic ? RS6000_PIC_OFFSET_TABLE_REGNUM \ | |
| 1939 : INVALID_REGNUM) | |
| 0 | 1940 |
| 1941 #define TOC_REGISTER (TARGET_MINIMAL_TOC ? RS6000_PIC_OFFSET_TABLE_REGNUM : 2) | |
| 1942 | |
| 1943 /* Define this macro if the register defined by | |
| 1944 `PIC_OFFSET_TABLE_REGNUM' is clobbered by calls. Do not define | |
| 1945 this macro if `PIC_OFFSET_TABLE_REGNUM' is not defined. */ | |
| 1946 | |
| 1947 /* #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED */ | |
| 1948 | |
| 1949 /* A C expression that is nonzero if X is a legitimate immediate | |
| 1950 operand on the target machine when generating position independent | |
| 1951 code. You can assume that X satisfies `CONSTANT_P', so you need | |
| 1952 not check this. You can also assume FLAG_PIC is true, so you need | |
| 1953 not check it either. You need not define this macro if all | |
| 1954 constants (including `SYMBOL_REF') can be immediate operands when | |
| 1955 generating position independent code. */ | |
| 1956 | |
| 1957 /* #define LEGITIMATE_PIC_OPERAND_P (X) */ | |
| 1958 | |
| 1959 /* Specify the machine mode that this machine uses | |
| 1960 for the index in the tablejump instruction. */ | |
| 1961 #define CASE_VECTOR_MODE SImode | |
| 1962 | |
| 1963 /* Define as C expression which evaluates to nonzero if the tablejump | |
| 1964 instruction expects the table to contain offsets from the address of the | |
| 1965 table. | |
| 1966 Do not define this if the table should contain absolute addresses. */ | |
| 1967 #define CASE_VECTOR_PC_RELATIVE 1 | |
| 1968 | |
| 1969 /* Define this as 1 if `char' should by default be signed; else as 0. */ | |
| 1970 #define DEFAULT_SIGNED_CHAR 0 | |
| 1971 | |
| 1972 /* An integer expression for the size in bits of the largest integer machine | |
| 1973 mode that should actually be used. */ | |
| 1974 | |
| 1975 /* Allow pairs of registers to be used, which is the intent of the default. */ | |
| 1976 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_POWERPC64 ? TImode : DImode) | |
| 1977 | |
| 1978 /* Max number of bytes we can move from memory to memory | |
| 1979 in one reasonably fast instruction. */ | |
| 1980 #define MOVE_MAX (! TARGET_POWERPC64 ? 4 : 8) | |
| 1981 #define MAX_MOVE_MAX 8 | |
| 1982 | |
| 1983 /* Nonzero if access to memory by bytes is no faster than for words. | |
| 1984 Also nonzero if doing byte operations (specifically shifts) in registers | |
| 1985 is undesirable. */ | |
| 1986 #define SLOW_BYTE_ACCESS 1 | |
| 1987 | |
| 1988 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD | |
| 1989 will either zero-extend or sign-extend. The value of this macro should | |
| 1990 be the code that says which one of the two operations is implicitly | |
| 1991 done, UNKNOWN if none. */ | |
| 1992 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND | |
| 1993 | |
| 1994 /* Define if loading short immediate values into registers sign extends. */ | |
| 111 | 1995 #define SHORT_IMMEDIATES_SIGN_EXTEND 1 |
| 0 | 1996 |
| 1997 /* The cntlzw and cntlzd instructions return 32 and 64 for input of zero. */ | |
| 1998 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ | |
| 111 | 1999 ((VALUE) = GET_MODE_BITSIZE (MODE), 2) |
| 2000 | |
| 2001 /* The CTZ patterns that are implemented in terms of CLZ return -1 for input of | |
| 2002 zero. The hardware instructions added in Power9 and the sequences using | |
| 2003 popcount return 32 or 64. */ | |
| 2004 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ | |
| 2005 (TARGET_CTZ || TARGET_POPCNTD \ | |
| 2006 ? ((VALUE) = GET_MODE_BITSIZE (MODE), 2) \ | |
| 2007 : ((VALUE) = -1, 2)) | |
| 0 | 2008 |
| 2009 /* Specify the machine mode that pointers have. | |
| 2010 After generation of rtl, the compiler makes no further distinction | |
| 2011 between pointers and any other objects of this machine mode. */ | |
| 111 | 2012 extern scalar_int_mode rs6000_pmode; |
| 2013 #define Pmode rs6000_pmode | |
| 0 | 2014 |
| 2015 /* Supply definition of STACK_SIZE_MODE for allocate_dynamic_stack_space. */ | |
| 2016 #define STACK_SIZE_MODE (TARGET_32BIT ? SImode : DImode) | |
| 2017 | |
| 2018 /* Mode of a function address in a call instruction (for indexing purposes). | |
| 2019 Doesn't matter on RS/6000. */ | |
| 2020 #define FUNCTION_MODE SImode | |
| 2021 | |
| 2022 /* Define this if addresses of constant functions | |
| 2023 shouldn't be put through pseudo regs where they can be cse'd. | |
| 2024 Desirable on machines where ordinary constants are expensive | |
| 2025 but a CALL with constant address is cheap. */ | |
| 111 | 2026 #define NO_FUNCTION_CSE 1 |
| 0 | 2027 |
| 2028 /* Define this to be nonzero if shift instructions ignore all but the low-order | |
| 2029 few bits. | |
| 2030 | |
| 2031 The sle and sre instructions which allow SHIFT_COUNT_TRUNCATED | |
| 2032 have been dropped from the PowerPC architecture. */ | |
| 111 | 2033 #define SHIFT_COUNT_TRUNCATED 0 |
| 0 | 2034 |
| 2035 /* Adjust the length of an INSN. LENGTH is the currently-computed length and | |
| 2036 should be adjusted to reflect any required changes. This macro is used when | |
| 2037 there is some systematic length adjustment required that would be difficult | |
| 2038 to express in the length attribute. */ | |
| 2039 | |
| 2040 /* #define ADJUST_INSN_LENGTH(X,LENGTH) */ | |
| 2041 | |
| 2042 /* Given a comparison code (EQ, NE, etc.) and the first operand of a | |
| 2043 COMPARE, return the mode to be used for the comparison. For | |
| 2044 floating-point, CCFPmode should be used. CCUNSmode should be used | |
| 2045 for unsigned comparisons. CCEQmode should be used when we are | |
| 2046 doing an inequality comparison on the result of a | |
| 2047 comparison. CCmode should be used in all other cases. */ | |
| 2048 | |
| 2049 #define SELECT_CC_MODE(OP,X,Y) \ | |
| 2050 (SCALAR_FLOAT_MODE_P (GET_MODE (X)) ? CCFPmode \ | |
| 2051 : (OP) == GTU || (OP) == LTU || (OP) == GEU || (OP) == LEU ? CCUNSmode \ | |
| 2052 : (((OP) == EQ || (OP) == NE) && COMPARISON_P (X) \ | |
| 2053 ? CCEQmode : CCmode)) | |
| 2054 | |
| 2055 /* Can the condition code MODE be safely reversed? This is safe in | |
| 2056 all cases on this port, because at present it doesn't use the | |
| 2057 trapping FP comparisons (fcmpo). */ | |
| 2058 #define REVERSIBLE_CC_MODE(MODE) 1 | |
| 2059 | |
| 2060 /* Given a condition code and a mode, return the inverse condition. */ | |
| 2061 #define REVERSE_CONDITION(CODE, MODE) rs6000_reverse_condition (MODE, CODE) | |
| 2062 | |
| 2063 | |
| 111 | 2064 /* Target cpu costs. */ |
| 2065 | |
| 2066 struct processor_costs { | |
| 2067 const int mulsi; /* cost of SImode multiplication. */ | |
| 2068 const int mulsi_const; /* cost of SImode multiplication by constant. */ | |
| 2069 const int mulsi_const9; /* cost of SImode mult by short constant. */ | |
| 2070 const int muldi; /* cost of DImode multiplication. */ | |
| 2071 const int divsi; /* cost of SImode division. */ | |
| 2072 const int divdi; /* cost of DImode division. */ | |
| 2073 const int fp; /* cost of simple SFmode and DFmode insns. */ | |
| 2074 const int dmul; /* cost of DFmode multiplication (and fmadd). */ | |
| 2075 const int sdiv; /* cost of SFmode division (fdivs). */ | |
| 2076 const int ddiv; /* cost of DFmode division (fdiv). */ | |
| 2077 const int cache_line_size; /* cache line size in bytes. */ | |
| 2078 const int l1_cache_size; /* size of l1 cache, in kilobytes. */ | |
| 2079 const int l2_cache_size; /* size of l2 cache, in kilobytes. */ | |
| 2080 const int simultaneous_prefetches; /* number of parallel prefetch | |
| 2081 operations. */ | |
| 2082 const int sfdf_convert; /* cost of SF->DF conversion. */ | |
| 2083 }; | |
| 2084 | |
| 2085 extern const struct processor_costs *rs6000_cost; | |
| 2086 | |
| 0 | 2087 /* Control the assembler format that we output. */ |
| 2088 | |
| 2089 /* A C string constant describing how to begin a comment in the target | |
| 2090 assembler language. The compiler assumes that the comment will end at | |
| 2091 the end of the line. */ | |
| 2092 #define ASM_COMMENT_START " #" | |
| 2093 | |
| 2094 /* Flag to say the TOC is initialized */ | |
| 2095 extern int toc_initialized; | |
| 2096 | |
| 2097 /* Macro to output a special constant pool entry. Go to WIN if we output | |
| 2098 it. Otherwise, it is written the usual way. | |
| 2099 | |
| 2100 On the RS/6000, toc entries are handled this way. */ | |
| 2101 | |
| 2102 #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, WIN) \ | |
| 2103 { if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (X, MODE)) \ | |
| 2104 { \ | |
| 2105 output_toc (FILE, X, LABELNO, MODE); \ | |
| 2106 goto WIN; \ | |
| 2107 } \ | |
| 2108 } | |
| 2109 | |
| 2110 #ifdef HAVE_GAS_WEAK | |
| 2111 #define RS6000_WEAK 1 | |
| 2112 #else | |
| 2113 #define RS6000_WEAK 0 | |
| 2114 #endif | |
| 2115 | |
| 2116 #if RS6000_WEAK | |
| 2117 /* Used in lieu of ASM_WEAKEN_LABEL. */ | |
| 111 | 2118 #define ASM_WEAKEN_DECL(FILE, DECL, NAME, VAL) \ |
| 2119 rs6000_asm_weaken_decl ((FILE), (DECL), (NAME), (VAL)) | |
| 0 | 2120 #endif |
| 2121 | |
| 2122 #if HAVE_GAS_WEAKREF | |
| 2123 #define ASM_OUTPUT_WEAKREF(FILE, DECL, NAME, VALUE) \ | |
| 2124 do \ | |
| 2125 { \ | |
| 2126 fputs ("\t.weakref\t", (FILE)); \ | |
| 2127 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \ | |
| 2128 fputs (", ", (FILE)); \ | |
| 2129 RS6000_OUTPUT_BASENAME ((FILE), (VALUE)); \ | |
| 2130 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \ | |
| 2131 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \ | |
| 2132 { \ | |
| 2133 fputs ("\n\t.weakref\t.", (FILE)); \ | |
| 2134 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \ | |
| 2135 fputs (", .", (FILE)); \ | |
| 2136 RS6000_OUTPUT_BASENAME ((FILE), (VALUE)); \ | |
| 2137 } \ | |
| 2138 fputc ('\n', (FILE)); \ | |
| 2139 } while (0) | |
| 2140 #endif | |
| 2141 | |
| 2142 /* This implements the `alias' attribute. */ | |
| 2143 #undef ASM_OUTPUT_DEF_FROM_DECLS | |
| 2144 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL, TARGET) \ | |
| 2145 do \ | |
| 2146 { \ | |
| 2147 const char *alias = XSTR (XEXP (DECL_RTL (DECL), 0), 0); \ | |
| 2148 const char *name = IDENTIFIER_POINTER (TARGET); \ | |
| 2149 if (TREE_CODE (DECL) == FUNCTION_DECL \ | |
| 2150 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \ | |
| 2151 { \ | |
| 2152 if (TREE_PUBLIC (DECL)) \ | |
| 2153 { \ | |
| 2154 if (!RS6000_WEAK || !DECL_WEAK (DECL)) \ | |
| 2155 { \ | |
| 2156 fputs ("\t.globl\t.", FILE); \ | |
| 2157 RS6000_OUTPUT_BASENAME (FILE, alias); \ | |
| 2158 putc ('\n', FILE); \ | |
| 2159 } \ | |
| 2160 } \ | |
| 2161 else if (TARGET_XCOFF) \ | |
| 2162 { \ | |
| 111 | 2163 if (!RS6000_WEAK || !DECL_WEAK (DECL)) \ |
| 2164 { \ | |
| 2165 fputs ("\t.lglobl\t.", FILE); \ | |
| 2166 RS6000_OUTPUT_BASENAME (FILE, alias); \ | |
| 2167 putc ('\n', FILE); \ | |
| 2168 fputs ("\t.lglobl\t", FILE); \ | |
| 2169 RS6000_OUTPUT_BASENAME (FILE, alias); \ | |
| 2170 putc ('\n', FILE); \ | |
| 2171 } \ | |
| 0 | 2172 } \ |
| 2173 fputs ("\t.set\t.", FILE); \ | |
| 2174 RS6000_OUTPUT_BASENAME (FILE, alias); \ | |
| 2175 fputs (",.", FILE); \ | |
| 2176 RS6000_OUTPUT_BASENAME (FILE, name); \ | |
| 2177 fputc ('\n', FILE); \ | |
| 2178 } \ | |
| 2179 ASM_OUTPUT_DEF (FILE, alias, name); \ | |
| 2180 } \ | |
| 2181 while (0) | |
| 2182 | |
| 2183 #define TARGET_ASM_FILE_START rs6000_file_start | |
| 2184 | |
| 2185 /* Output to assembler file text saying following lines | |
| 2186 may contain character constants, extra white space, comments, etc. */ | |
| 2187 | |
| 2188 #define ASM_APP_ON "" | |
| 2189 | |
| 2190 /* Output to assembler file text saying following lines | |
| 2191 no longer contain unusual constructs. */ | |
| 2192 | |
| 2193 #define ASM_APP_OFF "" | |
| 2194 | |
| 2195 /* How to refer to registers in assembler output. | |
| 2196 This sequence is indexed by compiler's hard-register-number (see above). */ | |
| 2197 | |
| 2198 extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */ | |
| 2199 | |
| 2200 #define REGISTER_NAMES \ | |
| 2201 { \ | |
| 2202 &rs6000_reg_names[ 0][0], /* r0 */ \ | |
| 2203 &rs6000_reg_names[ 1][0], /* r1 */ \ | |
| 2204 &rs6000_reg_names[ 2][0], /* r2 */ \ | |
| 2205 &rs6000_reg_names[ 3][0], /* r3 */ \ | |
| 2206 &rs6000_reg_names[ 4][0], /* r4 */ \ | |
| 2207 &rs6000_reg_names[ 5][0], /* r5 */ \ | |
| 2208 &rs6000_reg_names[ 6][0], /* r6 */ \ | |
| 2209 &rs6000_reg_names[ 7][0], /* r7 */ \ | |
| 2210 &rs6000_reg_names[ 8][0], /* r8 */ \ | |
| 2211 &rs6000_reg_names[ 9][0], /* r9 */ \ | |
| 2212 &rs6000_reg_names[10][0], /* r10 */ \ | |
| 2213 &rs6000_reg_names[11][0], /* r11 */ \ | |
| 2214 &rs6000_reg_names[12][0], /* r12 */ \ | |
| 2215 &rs6000_reg_names[13][0], /* r13 */ \ | |
| 2216 &rs6000_reg_names[14][0], /* r14 */ \ | |
| 2217 &rs6000_reg_names[15][0], /* r15 */ \ | |
| 2218 &rs6000_reg_names[16][0], /* r16 */ \ | |
| 2219 &rs6000_reg_names[17][0], /* r17 */ \ | |
| 2220 &rs6000_reg_names[18][0], /* r18 */ \ | |
| 2221 &rs6000_reg_names[19][0], /* r19 */ \ | |
| 2222 &rs6000_reg_names[20][0], /* r20 */ \ | |
| 2223 &rs6000_reg_names[21][0], /* r21 */ \ | |
| 2224 &rs6000_reg_names[22][0], /* r22 */ \ | |
| 2225 &rs6000_reg_names[23][0], /* r23 */ \ | |
| 2226 &rs6000_reg_names[24][0], /* r24 */ \ | |
| 2227 &rs6000_reg_names[25][0], /* r25 */ \ | |
| 2228 &rs6000_reg_names[26][0], /* r26 */ \ | |
| 2229 &rs6000_reg_names[27][0], /* r27 */ \ | |
| 2230 &rs6000_reg_names[28][0], /* r28 */ \ | |
| 2231 &rs6000_reg_names[29][0], /* r29 */ \ | |
| 2232 &rs6000_reg_names[30][0], /* r30 */ \ | |
| 2233 &rs6000_reg_names[31][0], /* r31 */ \ | |
| 2234 \ | |
| 2235 &rs6000_reg_names[32][0], /* fr0 */ \ | |
| 2236 &rs6000_reg_names[33][0], /* fr1 */ \ | |
| 2237 &rs6000_reg_names[34][0], /* fr2 */ \ | |
| 2238 &rs6000_reg_names[35][0], /* fr3 */ \ | |
| 2239 &rs6000_reg_names[36][0], /* fr4 */ \ | |
| 2240 &rs6000_reg_names[37][0], /* fr5 */ \ | |
| 2241 &rs6000_reg_names[38][0], /* fr6 */ \ | |
| 2242 &rs6000_reg_names[39][0], /* fr7 */ \ | |
| 2243 &rs6000_reg_names[40][0], /* fr8 */ \ | |
| 2244 &rs6000_reg_names[41][0], /* fr9 */ \ | |
| 2245 &rs6000_reg_names[42][0], /* fr10 */ \ | |
| 2246 &rs6000_reg_names[43][0], /* fr11 */ \ | |
| 2247 &rs6000_reg_names[44][0], /* fr12 */ \ | |
| 2248 &rs6000_reg_names[45][0], /* fr13 */ \ | |
| 2249 &rs6000_reg_names[46][0], /* fr14 */ \ | |
| 2250 &rs6000_reg_names[47][0], /* fr15 */ \ | |
| 2251 &rs6000_reg_names[48][0], /* fr16 */ \ | |
| 2252 &rs6000_reg_names[49][0], /* fr17 */ \ | |
| 2253 &rs6000_reg_names[50][0], /* fr18 */ \ | |
| 2254 &rs6000_reg_names[51][0], /* fr19 */ \ | |
| 2255 &rs6000_reg_names[52][0], /* fr20 */ \ | |
| 2256 &rs6000_reg_names[53][0], /* fr21 */ \ | |
| 2257 &rs6000_reg_names[54][0], /* fr22 */ \ | |
| 2258 &rs6000_reg_names[55][0], /* fr23 */ \ | |
| 2259 &rs6000_reg_names[56][0], /* fr24 */ \ | |
| 2260 &rs6000_reg_names[57][0], /* fr25 */ \ | |
| 2261 &rs6000_reg_names[58][0], /* fr26 */ \ | |
| 2262 &rs6000_reg_names[59][0], /* fr27 */ \ | |
| 2263 &rs6000_reg_names[60][0], /* fr28 */ \ | |
| 2264 &rs6000_reg_names[61][0], /* fr29 */ \ | |
| 2265 &rs6000_reg_names[62][0], /* fr30 */ \ | |
| 2266 &rs6000_reg_names[63][0], /* fr31 */ \ | |
| 2267 \ | |
| 111 | 2268 &rs6000_reg_names[64][0], /* was mq */ \ |
| 0 | 2269 &rs6000_reg_names[65][0], /* lr */ \ |
| 2270 &rs6000_reg_names[66][0], /* ctr */ \ | |
| 2271 &rs6000_reg_names[67][0], /* ap */ \ | |
| 2272 \ | |
| 2273 &rs6000_reg_names[68][0], /* cr0 */ \ | |
| 2274 &rs6000_reg_names[69][0], /* cr1 */ \ | |
| 2275 &rs6000_reg_names[70][0], /* cr2 */ \ | |
| 2276 &rs6000_reg_names[71][0], /* cr3 */ \ | |
| 2277 &rs6000_reg_names[72][0], /* cr4 */ \ | |
| 2278 &rs6000_reg_names[73][0], /* cr5 */ \ | |
| 2279 &rs6000_reg_names[74][0], /* cr6 */ \ | |
| 2280 &rs6000_reg_names[75][0], /* cr7 */ \ | |
| 2281 \ | |
|
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|
2282 &rs6000_reg_names[76][0], /* ca */ \ |
| 0 | 2283 \ |
| 2284 &rs6000_reg_names[77][0], /* v0 */ \ | |
| 2285 &rs6000_reg_names[78][0], /* v1 */ \ | |
| 2286 &rs6000_reg_names[79][0], /* v2 */ \ | |
| 2287 &rs6000_reg_names[80][0], /* v3 */ \ | |
| 2288 &rs6000_reg_names[81][0], /* v4 */ \ | |
| 2289 &rs6000_reg_names[82][0], /* v5 */ \ | |
| 2290 &rs6000_reg_names[83][0], /* v6 */ \ | |
| 2291 &rs6000_reg_names[84][0], /* v7 */ \ | |
| 2292 &rs6000_reg_names[85][0], /* v8 */ \ | |
| 2293 &rs6000_reg_names[86][0], /* v9 */ \ | |
| 2294 &rs6000_reg_names[87][0], /* v10 */ \ | |
| 2295 &rs6000_reg_names[88][0], /* v11 */ \ | |
| 2296 &rs6000_reg_names[89][0], /* v12 */ \ | |
| 2297 &rs6000_reg_names[90][0], /* v13 */ \ | |
| 2298 &rs6000_reg_names[91][0], /* v14 */ \ | |
| 2299 &rs6000_reg_names[92][0], /* v15 */ \ | |
| 2300 &rs6000_reg_names[93][0], /* v16 */ \ | |
| 2301 &rs6000_reg_names[94][0], /* v17 */ \ | |
| 2302 &rs6000_reg_names[95][0], /* v18 */ \ | |
| 2303 &rs6000_reg_names[96][0], /* v19 */ \ | |
| 2304 &rs6000_reg_names[97][0], /* v20 */ \ | |
| 2305 &rs6000_reg_names[98][0], /* v21 */ \ | |
| 2306 &rs6000_reg_names[99][0], /* v22 */ \ | |
| 2307 &rs6000_reg_names[100][0], /* v23 */ \ | |
| 2308 &rs6000_reg_names[101][0], /* v24 */ \ | |
| 2309 &rs6000_reg_names[102][0], /* v25 */ \ | |
| 2310 &rs6000_reg_names[103][0], /* v26 */ \ | |
| 2311 &rs6000_reg_names[104][0], /* v27 */ \ | |
| 2312 &rs6000_reg_names[105][0], /* v28 */ \ | |
| 2313 &rs6000_reg_names[106][0], /* v29 */ \ | |
| 2314 &rs6000_reg_names[107][0], /* v30 */ \ | |
| 2315 &rs6000_reg_names[108][0], /* v31 */ \ | |
| 2316 &rs6000_reg_names[109][0], /* vrsave */ \ | |
| 2317 &rs6000_reg_names[110][0], /* vscr */ \ | |
| 111 | 2318 &rs6000_reg_names[111][0], /* sfp */ \ |
| 2319 &rs6000_reg_names[112][0], /* tfhar */ \ | |
| 2320 &rs6000_reg_names[113][0], /* tfiar */ \ | |
| 2321 &rs6000_reg_names[114][0], /* texasr */ \ | |
| 0 | 2322 } |
| 2323 | |
| 2324 /* Table of additional register names to use in user input. */ | |
| 2325 | |
| 2326 #define ADDITIONAL_REGISTER_NAMES \ | |
| 2327 {{"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3}, \ | |
| 2328 {"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7}, \ | |
| 2329 {"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11}, \ | |
| 2330 {"r12", 12}, {"r13", 13}, {"r14", 14}, {"r15", 15}, \ | |
| 2331 {"r16", 16}, {"r17", 17}, {"r18", 18}, {"r19", 19}, \ | |
| 2332 {"r20", 20}, {"r21", 21}, {"r22", 22}, {"r23", 23}, \ | |
| 2333 {"r24", 24}, {"r25", 25}, {"r26", 26}, {"r27", 27}, \ | |
| 2334 {"r28", 28}, {"r29", 29}, {"r30", 30}, {"r31", 31}, \ | |
| 2335 {"fr0", 32}, {"fr1", 33}, {"fr2", 34}, {"fr3", 35}, \ | |
| 2336 {"fr4", 36}, {"fr5", 37}, {"fr6", 38}, {"fr7", 39}, \ | |
| 2337 {"fr8", 40}, {"fr9", 41}, {"fr10", 42}, {"fr11", 43}, \ | |
| 2338 {"fr12", 44}, {"fr13", 45}, {"fr14", 46}, {"fr15", 47}, \ | |
| 2339 {"fr16", 48}, {"fr17", 49}, {"fr18", 50}, {"fr19", 51}, \ | |
| 2340 {"fr20", 52}, {"fr21", 53}, {"fr22", 54}, {"fr23", 55}, \ | |
| 2341 {"fr24", 56}, {"fr25", 57}, {"fr26", 58}, {"fr27", 59}, \ | |
| 2342 {"fr28", 60}, {"fr29", 61}, {"fr30", 62}, {"fr31", 63}, \ | |
| 2343 {"v0", 77}, {"v1", 78}, {"v2", 79}, {"v3", 80}, \ | |
| 2344 {"v4", 81}, {"v5", 82}, {"v6", 83}, {"v7", 84}, \ | |
| 2345 {"v8", 85}, {"v9", 86}, {"v10", 87}, {"v11", 88}, \ | |
| 2346 {"v12", 89}, {"v13", 90}, {"v14", 91}, {"v15", 92}, \ | |
| 2347 {"v16", 93}, {"v17", 94}, {"v18", 95}, {"v19", 96}, \ | |
| 2348 {"v20", 97}, {"v21", 98}, {"v22", 99}, {"v23", 100}, \ | |
| 2349 {"v24", 101},{"v25", 102},{"v26", 103},{"v27", 104}, \ | |
| 2350 {"v28", 105},{"v29", 106},{"v30", 107},{"v31", 108}, \ | |
| 2351 {"vrsave", 109}, {"vscr", 110}, \ | |
| 111 | 2352 /* no additional names for: lr, ctr, ap */ \ |
| 0 | 2353 {"cr0", 68}, {"cr1", 69}, {"cr2", 70}, {"cr3", 71}, \ |
| 2354 {"cr4", 72}, {"cr5", 73}, {"cr6", 74}, {"cr7", 75}, \ | |
|
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|
2355 {"cc", 68}, {"sp", 1}, {"toc", 2}, \ |
|
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|
2356 /* CA is only part of XER, but we do not model the other parts (yet). */ \ |
|
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|
2357 {"xer", 76}, \ |
|
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|
2358 /* VSX registers overlaid on top of FR, Altivec registers */ \ |
|
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|
2359 {"vs0", 32}, {"vs1", 33}, {"vs2", 34}, {"vs3", 35}, \ |
|
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|
2360 {"vs4", 36}, {"vs5", 37}, {"vs6", 38}, {"vs7", 39}, \ |
|
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|
2361 {"vs8", 40}, {"vs9", 41}, {"vs10", 42}, {"vs11", 43}, \ |
|
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|
2362 {"vs12", 44}, {"vs13", 45}, {"vs14", 46}, {"vs15", 47}, \ |
|
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|
2363 {"vs16", 48}, {"vs17", 49}, {"vs18", 50}, {"vs19", 51}, \ |
|
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|
2364 {"vs20", 52}, {"vs21", 53}, {"vs22", 54}, {"vs23", 55}, \ |
|
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2365 {"vs24", 56}, {"vs25", 57}, {"vs26", 58}, {"vs27", 59}, \ |
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|
2366 {"vs28", 60}, {"vs29", 61}, {"vs30", 62}, {"vs31", 63}, \ |
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2367 {"vs32", 77}, {"vs33", 78}, {"vs34", 79}, {"vs35", 80}, \ |
|
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2368 {"vs36", 81}, {"vs37", 82}, {"vs38", 83}, {"vs39", 84}, \ |
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2369 {"vs40", 85}, {"vs41", 86}, {"vs42", 87}, {"vs43", 88}, \ |
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2370 {"vs44", 89}, {"vs45", 90}, {"vs46", 91}, {"vs47", 92}, \ |
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2371 {"vs48", 93}, {"vs49", 94}, {"vs50", 95}, {"vs51", 96}, \ |
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2372 {"vs52", 97}, {"vs53", 98}, {"vs54", 99}, {"vs55", 100}, \ |
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2373 {"vs56", 101},{"vs57", 102},{"vs58", 103},{"vs59", 104}, \ |
| 111 | 2374 {"vs60", 105},{"vs61", 106},{"vs62", 107},{"vs63", 108}, \ |
| 2375 /* Transactional Memory Facility (HTM) Registers. */ \ | |
| 2376 {"tfhar", 112}, {"tfiar", 113}, {"texasr", 114}, \ | |
| 2377 } | |
| 0 | 2378 |
| 2379 /* This is how to output an element of a case-vector that is relative. */ | |
| 2380 | |
| 2381 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ | |
| 2382 do { char buf[100]; \ | |
| 2383 fputs ("\t.long ", FILE); \ | |
| 2384 ASM_GENERATE_INTERNAL_LABEL (buf, "L", VALUE); \ | |
| 2385 assemble_name (FILE, buf); \ | |
| 2386 putc ('-', FILE); \ | |
| 2387 ASM_GENERATE_INTERNAL_LABEL (buf, "L", REL); \ | |
| 2388 assemble_name (FILE, buf); \ | |
| 2389 putc ('\n', FILE); \ | |
| 2390 } while (0) | |
| 2391 | |
| 2392 /* This is how to output an assembler line | |
| 2393 that says to advance the location counter | |
| 2394 to a multiple of 2**LOG bytes. */ | |
| 2395 | |
| 2396 #define ASM_OUTPUT_ALIGN(FILE,LOG) \ | |
| 2397 if ((LOG) != 0) \ | |
| 2398 fprintf (FILE, "\t.align %d\n", (LOG)) | |
| 2399 | |
|
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|
2400 /* How to align the given loop. */ |
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|
2401 #define LOOP_ALIGN(LABEL) rs6000_loop_align(LABEL) |
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2402 |
| 111 | 2403 /* Alignment guaranteed by __builtin_malloc. */ |
| 2404 /* FIXME: 128-bit alignment is guaranteed by glibc for TARGET_64BIT. | |
| 2405 However, specifying the stronger guarantee currently leads to | |
| 2406 a regression in SPEC CPU2006 437.leslie3d. The stronger | |
| 2407 guarantee should be implemented here once that's fixed. */ | |
| 2408 #define MALLOC_ABI_ALIGNMENT (64) | |
| 2409 | |
| 0 | 2410 /* Pick up the return address upon entry to a procedure. Used for |
| 2411 dwarf2 unwind information. This also enables the table driven | |
| 2412 mechanism. */ | |
| 2413 | |
| 2414 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNO) | |
| 2415 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNO) | |
| 2416 | |
| 2417 /* Describe how we implement __builtin_eh_return. */ | |
| 2418 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 3 : INVALID_REGNUM) | |
| 2419 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 10) | |
| 2420 | |
| 2421 /* Print operand X (an rtx) in assembler syntax to file FILE. | |
| 2422 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. | |
| 2423 For `%' followed by punctuation, CODE is the punctuation and X is null. */ | |
| 2424 | |
| 2425 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE) | |
| 2426 | |
| 2427 /* Define which CODE values are valid. */ | |
| 2428 | |
| 111 | 2429 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) ((CODE) == '&') |
| 0 | 2430 |
| 2431 /* Print a memory address as an operand to reference that memory location. */ | |
| 2432 | |
| 2433 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR) | |
| 2434 | |
| 111 | 2435 /* For switching between functions with different target attributes. */ |
| 2436 #define SWITCHABLE_TARGET 1 | |
| 2437 | |
| 0 | 2438 /* uncomment for disabling the corresponding default options */ |
| 2439 /* #define MACHINE_no_sched_interblock */ | |
| 2440 /* #define MACHINE_no_sched_speculative */ | |
| 2441 /* #define MACHINE_no_sched_speculative_load */ | |
| 2442 | |
| 2443 /* General flags. */ | |
| 2444 extern int frame_pointer_needed; | |
| 2445 | |
| 111 | 2446 /* Classification of the builtin functions as to which switches enable the |
| 2447 builtin, and what attributes it should have. We used to use the target | |
| 2448 flags macros, but we've run out of bits, so we now map the options into new | |
| 2449 settings used here. */ | |
| 2450 | |
| 2451 /* Builtin attributes. */ | |
| 2452 #define RS6000_BTC_SPECIAL 0x00000000 /* Special function. */ | |
| 2453 #define RS6000_BTC_UNARY 0x00000001 /* normal unary function. */ | |
| 2454 #define RS6000_BTC_BINARY 0x00000002 /* normal binary function. */ | |
| 2455 #define RS6000_BTC_TERNARY 0x00000003 /* normal ternary function. */ | |
| 2456 #define RS6000_BTC_PREDICATE 0x00000004 /* predicate function. */ | |
| 2457 #define RS6000_BTC_ABS 0x00000005 /* Altivec/VSX ABS function. */ | |
| 2458 #define RS6000_BTC_DST 0x00000007 /* Altivec DST function. */ | |
| 2459 #define RS6000_BTC_TYPE_MASK 0x0000000f /* Mask to isolate types */ | |
| 2460 | |
| 2461 #define RS6000_BTC_MISC 0x00000000 /* No special attributes. */ | |
| 2462 #define RS6000_BTC_CONST 0x00000100 /* Neither uses, nor | |
| 2463 modifies global state. */ | |
| 2464 #define RS6000_BTC_PURE 0x00000200 /* reads global | |
| 2465 state/mem and does | |
| 2466 not modify global state. */ | |
| 2467 #define RS6000_BTC_FP 0x00000400 /* depends on rounding mode. */ | |
| 2468 #define RS6000_BTC_ATTR_MASK 0x00000700 /* Mask of the attributes. */ | |
| 2469 | |
| 2470 /* Miscellaneous information. */ | |
| 2471 #define RS6000_BTC_SPR 0x01000000 /* function references SPRs. */ | |
| 2472 #define RS6000_BTC_VOID 0x02000000 /* function has no return value. */ | |
| 2473 #define RS6000_BTC_CR 0x04000000 /* function references a CR. */ | |
| 2474 #define RS6000_BTC_OVERLOADED 0x08000000 /* function is overloaded. */ | |
| 2475 #define RS6000_BTC_MISC_MASK 0x1f000000 /* Mask of the misc info. */ | |
|
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2476 |
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2477 /* Convenience macros to document the instruction type. */ |
| 111 | 2478 #define RS6000_BTC_MEM RS6000_BTC_MISC /* load/store touches mem. */ |
| 2479 #define RS6000_BTC_SAT RS6000_BTC_MISC /* saturate sets VSCR. */ | |
| 2480 | |
| 2481 /* Builtin targets. For now, we reuse the masks for those options that are in | |
| 2482 target flags, and pick two random bits for paired and ldbl128, which | |
| 2483 aren't in target_flags. */ | |
| 2484 #define RS6000_BTM_ALWAYS 0 /* Always enabled. */ | |
| 2485 #define RS6000_BTM_ALTIVEC MASK_ALTIVEC /* VMX/altivec vectors. */ | |
| 2486 #define RS6000_BTM_CMPB MASK_CMPB /* ISA 2.05: compare bytes. */ | |
| 2487 #define RS6000_BTM_VSX MASK_VSX /* VSX (vector/scalar). */ | |
| 2488 #define RS6000_BTM_P8_VECTOR MASK_P8_VECTOR /* ISA 2.07 vector. */ | |
| 2489 #define RS6000_BTM_P9_VECTOR MASK_P9_VECTOR /* ISA 3.0 vector. */ | |
| 2490 #define RS6000_BTM_P9_MISC MASK_P9_MISC /* ISA 3.0 misc. non-vector */ | |
| 2491 #define RS6000_BTM_CRYPTO MASK_CRYPTO /* crypto funcs. */ | |
| 2492 #define RS6000_BTM_HTM MASK_HTM /* hardware TM funcs. */ | |
| 2493 #define RS6000_BTM_PAIRED MASK_MULHW /* 750CL paired insns. */ | |
| 2494 #define RS6000_BTM_FRE MASK_POPCNTB /* FRE instruction. */ | |
| 2495 #define RS6000_BTM_FRES MASK_PPC_GFXOPT /* FRES instruction. */ | |
| 2496 #define RS6000_BTM_FRSQRTE MASK_PPC_GFXOPT /* FRSQRTE instruction. */ | |
| 2497 #define RS6000_BTM_FRSQRTES MASK_POPCNTB /* FRSQRTES instruction. */ | |
| 2498 #define RS6000_BTM_POPCNTD MASK_POPCNTD /* Target supports ISA 2.06. */ | |
| 2499 #define RS6000_BTM_CELL MASK_FPRND /* Target is cell powerpc. */ | |
| 2500 #define RS6000_BTM_DFP MASK_DFP /* Decimal floating point. */ | |
| 2501 #define RS6000_BTM_HARD_FLOAT MASK_SOFT_FLOAT /* Hardware floating point. */ | |
| 2502 #define RS6000_BTM_LDBL128 MASK_MULTIPLE /* 128-bit long double. */ | |
| 2503 #define RS6000_BTM_64BIT MASK_64BIT /* 64-bit addressing. */ | |
| 2504 #define RS6000_BTM_FLOAT128 MASK_FLOAT128_KEYWORD /* IEEE 128-bit float. */ | |
| 2505 #define RS6000_BTM_FLOAT128_HW MASK_FLOAT128_HW /* IEEE 128-bit float h/w. */ | |
| 2506 | |
| 2507 #define RS6000_BTM_COMMON (RS6000_BTM_ALTIVEC \ | |
| 2508 | RS6000_BTM_VSX \ | |
| 2509 | RS6000_BTM_P8_VECTOR \ | |
| 2510 | RS6000_BTM_P9_VECTOR \ | |
| 2511 | RS6000_BTM_P9_MISC \ | |
| 2512 | RS6000_BTM_MODULO \ | |
| 2513 | RS6000_BTM_CRYPTO \ | |
| 2514 | RS6000_BTM_FRE \ | |
| 2515 | RS6000_BTM_FRES \ | |
| 2516 | RS6000_BTM_FRSQRTE \ | |
| 2517 | RS6000_BTM_FRSQRTES \ | |
| 2518 | RS6000_BTM_HTM \ | |
| 2519 | RS6000_BTM_POPCNTD \ | |
| 2520 | RS6000_BTM_CELL \ | |
| 2521 | RS6000_BTM_DFP \ | |
| 2522 | RS6000_BTM_HARD_FLOAT \ | |
| 2523 | RS6000_BTM_LDBL128 \ | |
| 2524 | RS6000_BTM_FLOAT128 \ | |
| 2525 | RS6000_BTM_FLOAT128_HW) | |
| 2526 | |
| 2527 /* Define builtin enum index. */ | |
| 2528 | |
| 2529 #undef RS6000_BUILTIN_0 | |
| 2530 #undef RS6000_BUILTIN_1 | |
| 2531 #undef RS6000_BUILTIN_2 | |
| 2532 #undef RS6000_BUILTIN_3 | |
| 2533 #undef RS6000_BUILTIN_A | |
| 2534 #undef RS6000_BUILTIN_D | |
| 2535 #undef RS6000_BUILTIN_H | |
| 2536 #undef RS6000_BUILTIN_P | |
| 2537 #undef RS6000_BUILTIN_Q | |
| 2538 #undef RS6000_BUILTIN_X | |
| 2539 | |
| 2540 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) ENUM, | |
| 2541 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) ENUM, | |
| 2542 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) ENUM, | |
| 2543 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) ENUM, | |
| 2544 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) ENUM, | |
| 2545 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) ENUM, | |
| 2546 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) ENUM, | |
| 2547 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) ENUM, | |
| 2548 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) ENUM, | |
| 2549 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) ENUM, | |
|
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2550 |
| 0 | 2551 enum rs6000_builtins |
| 2552 { | |
|
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2553 #include "rs6000-builtin.def" |
| 0 | 2554 |
| 2555 RS6000_BUILTIN_COUNT | |
| 2556 }; | |
| 2557 | |
| 111 | 2558 #undef RS6000_BUILTIN_0 |
| 2559 #undef RS6000_BUILTIN_1 | |
| 2560 #undef RS6000_BUILTIN_2 | |
| 2561 #undef RS6000_BUILTIN_3 | |
| 2562 #undef RS6000_BUILTIN_A | |
| 2563 #undef RS6000_BUILTIN_D | |
| 2564 #undef RS6000_BUILTIN_H | |
| 2565 #undef RS6000_BUILTIN_P | |
| 2566 #undef RS6000_BUILTIN_Q | |
| 2567 #undef RS6000_BUILTIN_X | |
|
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2568 |
| 0 | 2569 enum rs6000_builtin_type_index |
| 2570 { | |
| 2571 RS6000_BTI_NOT_OPAQUE, | |
| 2572 RS6000_BTI_opaque_V2SI, | |
| 2573 RS6000_BTI_opaque_V2SF, | |
| 2574 RS6000_BTI_opaque_p_V2SI, | |
| 2575 RS6000_BTI_opaque_V4SI, | |
| 2576 RS6000_BTI_V16QI, | |
| 111 | 2577 RS6000_BTI_V1TI, |
| 0 | 2578 RS6000_BTI_V2SI, |
| 2579 RS6000_BTI_V2SF, | |
|
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2580 RS6000_BTI_V2DI, |
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2581 RS6000_BTI_V2DF, |
| 0 | 2582 RS6000_BTI_V4HI, |
| 2583 RS6000_BTI_V4SI, | |
| 2584 RS6000_BTI_V4SF, | |
| 2585 RS6000_BTI_V8HI, | |
| 2586 RS6000_BTI_unsigned_V16QI, | |
| 111 | 2587 RS6000_BTI_unsigned_V1TI, |
| 0 | 2588 RS6000_BTI_unsigned_V8HI, |
| 2589 RS6000_BTI_unsigned_V4SI, | |
|
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2590 RS6000_BTI_unsigned_V2DI, |
| 0 | 2591 RS6000_BTI_bool_char, /* __bool char */ |
| 2592 RS6000_BTI_bool_short, /* __bool short */ | |
| 2593 RS6000_BTI_bool_int, /* __bool int */ | |
|
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2594 RS6000_BTI_bool_long, /* __bool long */ |
| 0 | 2595 RS6000_BTI_pixel, /* __pixel */ |
| 2596 RS6000_BTI_bool_V16QI, /* __vector __bool char */ | |
| 2597 RS6000_BTI_bool_V8HI, /* __vector __bool short */ | |
| 2598 RS6000_BTI_bool_V4SI, /* __vector __bool int */ | |
|
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2599 RS6000_BTI_bool_V2DI, /* __vector __bool long */ |
| 0 | 2600 RS6000_BTI_pixel_V8HI, /* __vector __pixel */ |
| 2601 RS6000_BTI_long, /* long_integer_type_node */ | |
| 2602 RS6000_BTI_unsigned_long, /* long_unsigned_type_node */ | |
|
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2603 RS6000_BTI_long_long, /* long_long_integer_type_node */ |
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2604 RS6000_BTI_unsigned_long_long, /* long_long_unsigned_type_node */ |
| 0 | 2605 RS6000_BTI_INTQI, /* intQI_type_node */ |
| 2606 RS6000_BTI_UINTQI, /* unsigned_intQI_type_node */ | |
| 2607 RS6000_BTI_INTHI, /* intHI_type_node */ | |
| 2608 RS6000_BTI_UINTHI, /* unsigned_intHI_type_node */ | |
| 2609 RS6000_BTI_INTSI, /* intSI_type_node */ | |
| 2610 RS6000_BTI_UINTSI, /* unsigned_intSI_type_node */ | |
|
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2611 RS6000_BTI_INTDI, /* intDI_type_node */ |
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2612 RS6000_BTI_UINTDI, /* unsigned_intDI_type_node */ |
| 111 | 2613 RS6000_BTI_INTTI, /* intTI_type_node */ |
| 2614 RS6000_BTI_UINTTI, /* unsigned_intTI_type_node */ | |
| 0 | 2615 RS6000_BTI_float, /* float_type_node */ |
|
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2616 RS6000_BTI_double, /* double_type_node */ |
| 111 | 2617 RS6000_BTI_long_double, /* long_double_type_node */ |
| 2618 RS6000_BTI_dfloat64, /* dfloat64_type_node */ | |
| 2619 RS6000_BTI_dfloat128, /* dfloat128_type_node */ | |
| 0 | 2620 RS6000_BTI_void, /* void_type_node */ |
| 111 | 2621 RS6000_BTI_ieee128_float, /* ieee 128-bit floating point */ |
| 2622 RS6000_BTI_ibm128_float, /* IBM 128-bit floating point */ | |
| 2623 RS6000_BTI_const_str, /* pointer to const char * */ | |
| 0 | 2624 RS6000_BTI_MAX |
| 2625 }; | |
| 2626 | |
| 2627 | |
| 2628 #define opaque_V2SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V2SI]) | |
| 2629 #define opaque_V2SF_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V2SF]) | |
| 2630 #define opaque_p_V2SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_p_V2SI]) | |
| 2631 #define opaque_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V4SI]) | |
| 2632 #define V16QI_type_node (rs6000_builtin_types[RS6000_BTI_V16QI]) | |
| 111 | 2633 #define V1TI_type_node (rs6000_builtin_types[RS6000_BTI_V1TI]) |
|
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2634 #define V2DI_type_node (rs6000_builtin_types[RS6000_BTI_V2DI]) |
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2635 #define V2DF_type_node (rs6000_builtin_types[RS6000_BTI_V2DF]) |
| 0 | 2636 #define V2SI_type_node (rs6000_builtin_types[RS6000_BTI_V2SI]) |
| 2637 #define V2SF_type_node (rs6000_builtin_types[RS6000_BTI_V2SF]) | |
| 2638 #define V4HI_type_node (rs6000_builtin_types[RS6000_BTI_V4HI]) | |
| 2639 #define V4SI_type_node (rs6000_builtin_types[RS6000_BTI_V4SI]) | |
| 2640 #define V4SF_type_node (rs6000_builtin_types[RS6000_BTI_V4SF]) | |
| 2641 #define V8HI_type_node (rs6000_builtin_types[RS6000_BTI_V8HI]) | |
| 2642 #define unsigned_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V16QI]) | |
| 111 | 2643 #define unsigned_V1TI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V1TI]) |
| 0 | 2644 #define unsigned_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V8HI]) |
| 2645 #define unsigned_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V4SI]) | |
|
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2646 #define unsigned_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V2DI]) |
| 0 | 2647 #define bool_char_type_node (rs6000_builtin_types[RS6000_BTI_bool_char]) |
| 2648 #define bool_short_type_node (rs6000_builtin_types[RS6000_BTI_bool_short]) | |
| 2649 #define bool_int_type_node (rs6000_builtin_types[RS6000_BTI_bool_int]) | |
|
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2650 #define bool_long_type_node (rs6000_builtin_types[RS6000_BTI_bool_long]) |
| 0 | 2651 #define pixel_type_node (rs6000_builtin_types[RS6000_BTI_pixel]) |
| 2652 #define bool_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V16QI]) | |
| 2653 #define bool_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V8HI]) | |
| 2654 #define bool_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V4SI]) | |
|
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2655 #define bool_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V2DI]) |
| 0 | 2656 #define pixel_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_pixel_V8HI]) |
| 2657 | |
|
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2658 #define long_long_integer_type_internal_node (rs6000_builtin_types[RS6000_BTI_long_long]) |
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2659 #define long_long_unsigned_type_internal_node (rs6000_builtin_types[RS6000_BTI_unsigned_long_long]) |
| 0 | 2660 #define long_integer_type_internal_node (rs6000_builtin_types[RS6000_BTI_long]) |
| 2661 #define long_unsigned_type_internal_node (rs6000_builtin_types[RS6000_BTI_unsigned_long]) | |
| 2662 #define intQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTQI]) | |
| 2663 #define uintQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTQI]) | |
| 2664 #define intHI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTHI]) | |
| 2665 #define uintHI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTHI]) | |
| 2666 #define intSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTSI]) | |
| 2667 #define uintSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTSI]) | |
|
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2668 #define intDI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTDI]) |
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2669 #define uintDI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTDI]) |
| 111 | 2670 #define intTI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTTI]) |
| 2671 #define uintTI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTTI]) | |
| 0 | 2672 #define float_type_internal_node (rs6000_builtin_types[RS6000_BTI_float]) |
|
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2673 #define double_type_internal_node (rs6000_builtin_types[RS6000_BTI_double]) |
| 111 | 2674 #define long_double_type_internal_node (rs6000_builtin_types[RS6000_BTI_long_double]) |
| 2675 #define dfloat64_type_internal_node (rs6000_builtin_types[RS6000_BTI_dfloat64]) | |
| 2676 #define dfloat128_type_internal_node (rs6000_builtin_types[RS6000_BTI_dfloat128]) | |
| 0 | 2677 #define void_type_internal_node (rs6000_builtin_types[RS6000_BTI_void]) |
| 111 | 2678 #define ieee128_float_type_node (rs6000_builtin_types[RS6000_BTI_ieee128_float]) |
| 2679 #define ibm128_float_type_node (rs6000_builtin_types[RS6000_BTI_ibm128_float]) | |
| 2680 #define const_str_type_node (rs6000_builtin_types[RS6000_BTI_const_str]) | |
| 0 | 2681 |
| 2682 extern GTY(()) tree rs6000_builtin_types[RS6000_BTI_MAX]; | |
| 2683 extern GTY(()) tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT]; | |
| 2684 | |
| 111 | 2685 #define TARGET_SUPPORTS_WIDE_INT 1 |
| 2686 | |
| 2687 #if (GCC_VERSION >= 3000) | |
| 2688 #pragma GCC poison TARGET_FLOAT128 OPTION_MASK_FLOAT128 MASK_FLOAT128 | |
| 2689 #endif |