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1 ;; Scheduling description for the SPARC M8.
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2 ;; Copyright (C) 2017 Free Software Foundation, Inc.
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3 ;;
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4 ;; This file is part of GCC.
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5 ;;
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6 ;; GCC is free software; you can redistribute it and/or modify
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7 ;; it under the terms of the GNU General Public License as published by
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8 ;; the Free Software Foundation; either version 3, or (at your option)
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9 ;; any later version.
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10 ;;
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11 ;; GCC is distributed in the hope that it will be useful,
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12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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14 ;; GNU General Public License for more details.
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15 ;;
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16 ;; You should have received a copy of the GNU General Public License
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17 ;; along with GCC; see the file COPYING3. If not see
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18 ;; <http://www.gnu.org/licenses/>.
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19
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20 ;; Thigs to improve:
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21 ;;
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22 ;; - Store instructions are implemented by micro-ops, one of which
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23 ;; generates the store address and is executed in the store address
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24 ;; generation unit in the slot0. We need to model that.
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25 ;;
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26 ;; - There are two V3 pipes connected to different slots. The current
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27 ;; implementation assumes that all the instructions executing in a
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28 ;; V3 pipe are issued to the unit in slot3.
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29 ;;
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30 ;; - Single-issue ALU operations incur an additional cycle of latency to
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31 ;; slot 0 and slot 1 instructions. This is not currently reflected
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32 ;; in the DFA.
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33
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34 (define_automaton "m8_0")
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35
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36 ;; The S5 core has two dual-issue queues, PQLS and PQEX. Each queue
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37 ;; is divided into two slots: PQLS corresponds to slots 0 and 1, and
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38 ;; PQEX corresponds to slots 2 and 3. The core can issue 4
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39 ;; instructions per-cycle, and up to 4 instructions are committed each
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40 ;; cycle.
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41 ;;
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42 ;;
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43 ;; m8_slot0 - Load Unit.
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44 ;; - Store address gen. Unit.
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45 ;;
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46 ;;
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47 ;; === PQLS ==> m8_slot1 - Store data unit.
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48 ;; - Branch unit.
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49 ;;
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50 ;;
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51 ;; === PQEX ==> m8_slot2 - Integer Unit (EXU2).
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52 ;; - 3-cycles Crypto Unit (SPU2).
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53 ;;
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54 ;; m8_slot3 - Integer Unit (EXU3).
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55 ;; - 3-cycles Crypto Unit (SPU3).
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56 ;; - Floating-point and graphics unit (FPG).
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57 ;; - Long-latency Crypto Unit.
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58 ;; - Oracle Numbers Unit (ONU).
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59
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60 (define_cpu_unit "m8_slot0,m8_slot1,m8_slot2,m8_slot3" "m8_0")
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61
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62 ;; Some instructions stall the pipeline and avoid any other
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63 ;; instruction to be issued in the same cycle. We assume the same for
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64 ;; multi-instruction insns.
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65
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66 (define_reservation "m8_single_issue" "m8_slot0 + m8_slot1 + m8_slot2 + m8_slot3")
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67
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68 (define_insn_reservation "m8_single" 1
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69 (and (eq_attr "cpu" "m8")
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70 (eq_attr "type" "multi,savew,flushw,trap,bmask"))
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71 "m8_single_issue")
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72
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73 ;; Most of the instructions executing in the integer units have a
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74 ;; latency of 1.
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75
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76 (define_insn_reservation "m8_integer" 1
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77 (and (eq_attr "cpu" "m8")
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78 (eq_attr "type" "ialu,ialuX,shift,cmove,compare,bmask"))
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79 "(m8_slot2 | m8_slot3)")
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80
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81 ;; Flushing the instruction memory takes 27 cycles.
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82
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83
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84 (define_insn_reservation "m8_iflush" 27
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85 (and (eq_attr "cpu" "m8")
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86 (eq_attr "type" "iflush"))
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87 "(m8_slot2 | m8_slot3), nothing*26")
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88
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89 ;; The integer multiplication instructions have a latency of 10 cycles
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90 ;; and execute in integer units.
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91 ;;
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92 ;; Likewise for array*, edge* and pdistn instructions.
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93 ;;
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94 ;; However, the latency is only 9 cycles if the consumer of the
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95 ;; operation is also capable of 9 cycles latency. We model this with
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96 ;; a bypass.
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97
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98 (define_insn_reservation "m8_imul" 10
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99 (and (eq_attr "cpu" "m8")
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100 (eq_attr "type" "imul,array,edge,edgen,pdistn"))
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101 "(m8_slot2 | m8_slot3), nothing*12")
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102
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103 (define_bypass 9 "m8_imul" "m8_imul")
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104
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105 ;; The integer division instructions `sdiv' and `udivx' have a latency
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106 ;; of 30 cycles and execute in integer units.
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107
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108 (define_insn_reservation "m8_idiv" 30
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109 (and (eq_attr "cpu" "m8")
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110 (eq_attr "type" "idiv"))
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111 "(m8_slot2 | m8_slot3), nothing*29")
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112
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113 ;; Both integer and floating-point load instructions have a latency of
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114 ;; only 3 cycles,and execute in the slot0.
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115 ;;
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116 ;; Misaligned load instructions feature a latency of 11 cycles.
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117 ;;
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118 ;; The prefetch instruction also executes in the load unit, but it's
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119 ;; latency is only 1 cycle.
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120
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121 (define_insn_reservation "m8_load" 3
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122 (and (eq_attr "cpu" "m8")
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123 (ior (eq_attr "type" "fpload,sload")
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124 (and (eq_attr "type" "load")
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125 (eq_attr "subtype" "regular"))))
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126 "m8_slot0, nothing*2")
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127
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128 ;; (define_insn_reservation "m8_load_misalign" 11
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129 ;; (and (eq_attr "cpu" "m8")
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130 ;; (eq_attr "type" "load_mis,fpload_mis"))
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131 ;; "m8_slot0, nothing*10")
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132
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133 (define_insn_reservation "m8_prefetch" 1
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134 (and (eq_attr "cpu" "m8")
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135 (eq_attr "type" "load")
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136 (eq_attr "subtype" "prefetch"))
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137 "m8_slot0")
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138
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139 ;; Both integer and floating-point store instructions have a latency
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140 ;; of 1 cycle, and execute in the store data unit in slot1.
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141 ;;
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142 ;; However, misaligned store instructions feature a latency of 3
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143 ;; cycles.
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144
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145 (define_insn_reservation "m8_store" 1
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146 (and (eq_attr "cpu" "m8")
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147 (eq_attr "type" "store,fpstore"))
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148 "m8_slot1")
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149
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150 ;; (define_insn_reservation "m8_store_misalign" 3
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151 ;; (and (eq_attr "cpu" "m8")
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152 ;; (eq_attr "type" "store_mis,fpstore_mis"))
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153 ;; "m8_slot1, nothing*2")
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154
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155 ;; Control-transfer instructions execute in the Branch Unit in the
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156 ;; slot1.
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157
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158 (define_insn_reservation "m8_cti" 1
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159 (and (eq_attr "cpu" "m8")
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160 (eq_attr "type" "cbcond,uncond_cbcond,branch,call,sibcall,call_no_delay_slot,uncond_branch,return"))
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161 "m8_slot1")
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162
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163 ;; Many instructions executing in the Floating-point and Graphics Unit
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164 ;; (FGU) serving slot3 feature a default latency of 9 cycles.
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165
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166 (define_insn_reservation "m8_fp" 9
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167 (and (eq_attr "cpu" "m8")
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168 (ior (eq_attr "type" "fpmove,fpcmove,fpcrmove,fp,fpcmp,fpmul,fgm_pack,fgm_mul,pdist")
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169 (and (eq_attr "type" "fga")
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170 (eq_attr "subtype" "fpu"))))
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171 "m8_slot3, nothing*8")
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172
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173 ;; Floating-point division and floating-point square-root instructions
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174 ;; have high latencies. They execute in the FGU.
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175
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176 (define_insn_reservation "m8_fpdivs" 26
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177 (and (eq_attr "cpu" "m8")
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178 (eq_attr "type" "fpdivs"))
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179 "m8_slot3, nothing*25")
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180
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181 (define_insn_reservation "m8_fpsqrts" 33
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182 (and (eq_attr "cpu" "m8")
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183 (eq_attr "type" "fpsqrts"))
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184 "m8_slot3, nothing*32")
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185
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186 (define_insn_reservation "m8_fpdivd" 30
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187 (and (eq_attr "cpu" "m8")
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188 (eq_attr "type" "fpdivd"))
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189 "m8_slot3, nothing*29")
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190
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191 (define_insn_reservation "m8_fpsqrtd" 41
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192 (and (eq_attr "cpu" "m8")
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193 (eq_attr "type" "fpsqrtd"))
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194 "m8_slot3, nothing*40")
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195
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196 ;; SIMD VIS instructions executing in the Floating-point and graphics
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197 ;; unit (FPG) in slot3 usually have a latency of 5 cycles.
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198 ;;
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199 ;; However, the latency for many instructions is only 3 cycles if the
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200 ;; consumer can also be executed in 3 cycles. We model this with a
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201 ;; bypass. In these cases the instructions are executed in one of the
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202 ;; two 3-cycle crypto units (SPU, also known as "v3-pipes") in slots 2
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203 ;; and 3.
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204
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205 (define_insn_reservation "m8_vis" 5
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206 (and (eq_attr "cpu" "m8")
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207 (ior (eq_attr "type" "viscmp,lzd")
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208 (and (eq_attr "type" "fga")
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209 (eq_attr "subtype" "maxmin,cmask,other"))
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210 (and (eq_attr "type" "vismv")
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211 (eq_attr "subtype" "single,movstouw"))
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212 (and (eq_attr "type" "visl")
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213 (eq_attr "subtype" "single"))))
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214 "m8_slot3, nothing*4")
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215
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216 (define_bypass 3 "m8_vis" "m8_vis")
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217
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218 (define_insn_reservation "m8_gsr" 5
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219 (and (eq_attr "cpu" "m8")
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220 (eq_attr "type" "gsr")
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221 (eq_attr "subtype" "alignaddr"))
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222 "m8_slot3, nothing*4")
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223
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224 ;; A few VIS instructions have a latency of 1.
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225
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226 (define_insn_reservation "m8_vis_1cycle" 1
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227 (and (eq_attr "cpu" "m8")
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228 (ior (and (eq_attr "type" "vismv")
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229 (eq_attr "subtype" "double,movxtod,movdtox"))
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230 (and (eq_attr "type" "visl")
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231 (eq_attr "subtype" "double"))
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232 (and (eq_attr "type" "fga")
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233 (eq_attr "subtype" "addsub64"))))
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234 "m8_slot3")
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235
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236 ;; Reading and writing to the gsr register takes more than 70 cycles.
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237
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238 (define_insn_reservation "m8_gsr_reg" 70
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239 (and (eq_attr "cpu" "m8")
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240 (eq_attr "type" "gsr")
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241 (eq_attr "subtype" "reg"))
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242 "m8_slot3, nothing*69")
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