Mercurial > hg > CbC > CbC_gcc
annotate gcc/config/sparc/sparc.h @ 111:04ced10e8804
gcc 7
author | kono |
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date | Fri, 27 Oct 2017 22:46:09 +0900 |
parents | f6334be47118 |
children | 84e7813d76e9 |
rev | line source |
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0 | 1 /* Definitions of target machine for GNU compiler, for Sun SPARC. |
111 | 2 Copyright (C) 1987-2017 Free Software Foundation, Inc. |
0 | 3 Contributed by Michael Tiemann (tiemann@cygnus.com). |
4 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans, | |
5 at Cygnus Support. | |
6 | |
7 This file is part of GCC. | |
8 | |
9 GCC is free software; you can redistribute it and/or modify | |
10 it under the terms of the GNU General Public License as published by | |
11 the Free Software Foundation; either version 3, or (at your option) | |
12 any later version. | |
13 | |
14 GCC is distributed in the hope that it will be useful, | |
15 but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 GNU General Public License for more details. | |
18 | |
19 You should have received a copy of the GNU General Public License | |
20 along with GCC; see the file COPYING3. If not see | |
21 <http://www.gnu.org/licenses/>. */ | |
22 | |
23 #include "config/vxworks-dummy.h" | |
24 | |
25 /* Note that some other tm.h files include this one and then override | |
26 whatever definitions are necessary. */ | |
27 | |
111 | 28 #define TARGET_CPU_CPP_BUILTINS() sparc_target_macros () |
0 | 29 |
30 /* Specify this in a cover file to provide bi-architecture (32/64) support. */ | |
31 /* #define SPARC_BI_ARCH */ | |
32 | |
33 /* Macro used later in this file to determine default architecture. */ | |
34 #define DEFAULT_ARCH32_P ((TARGET_DEFAULT & MASK_64BIT) == 0) | |
35 | |
36 /* TARGET_ARCH{32,64} are the main macros to decide which of the two | |
37 architectures to compile for. We allow targets to choose compile time or | |
38 runtime selection. */ | |
39 #ifdef IN_LIBGCC2 | |
40 #if defined(__sparcv9) || defined(__arch64__) | |
41 #define TARGET_ARCH32 0 | |
42 #else | |
43 #define TARGET_ARCH32 1 | |
44 #endif /* sparc64 */ | |
45 #else | |
46 #ifdef SPARC_BI_ARCH | |
111 | 47 #define TARGET_ARCH32 (!TARGET_64BIT) |
0 | 48 #else |
49 #define TARGET_ARCH32 (DEFAULT_ARCH32_P) | |
50 #endif /* SPARC_BI_ARCH */ | |
51 #endif /* IN_LIBGCC2 */ | |
111 | 52 #define TARGET_ARCH64 (!TARGET_ARCH32) |
0 | 53 |
54 /* Code model selection in 64-bit environment. | |
55 | |
56 The machine mode used for addresses is 32-bit wide: | |
57 | |
58 TARGET_CM_32: 32-bit address space. | |
59 It is the code model used when generating 32-bit code. | |
60 | |
61 The machine mode used for addresses is 64-bit wide: | |
62 | |
63 TARGET_CM_MEDLOW: 32-bit address space. | |
64 The executable must be in the low 32 bits of memory. | |
65 This avoids generating %uhi and %ulo terms. Programs | |
66 can be statically or dynamically linked. | |
67 | |
68 TARGET_CM_MEDMID: 44-bit address space. | |
69 The executable must be in the low 44 bits of memory, | |
70 and the %[hml]44 terms are used. The text and data | |
71 segments have a maximum size of 2GB (31-bit span). | |
72 The maximum offset from any instruction to the label | |
73 _GLOBAL_OFFSET_TABLE_ is 2GB (31-bit span). | |
74 | |
75 TARGET_CM_MEDANY: 64-bit address space. | |
76 The text and data segments have a maximum size of 2GB | |
77 (31-bit span) and may be located anywhere in memory. | |
78 The maximum offset from any instruction to the label | |
79 _GLOBAL_OFFSET_TABLE_ is 2GB (31-bit span). | |
80 | |
81 TARGET_CM_EMBMEDANY: 64-bit address space. | |
82 The text and data segments have a maximum size of 2GB | |
83 (31-bit span) and may be located anywhere in memory. | |
84 The global register %g4 contains the start address of | |
85 the data segment. Programs are statically linked and | |
86 PIC is not supported. | |
87 | |
88 Different code models are not supported in 32-bit environment. */ | |
89 | |
90 enum cmodel { | |
91 CM_32, | |
92 CM_MEDLOW, | |
93 CM_MEDMID, | |
94 CM_MEDANY, | |
95 CM_EMBMEDANY | |
96 }; | |
97 | |
98 /* One of CM_FOO. */ | |
99 extern enum cmodel sparc_cmodel; | |
100 | |
101 /* V9 code model selection. */ | |
102 #define TARGET_CM_MEDLOW (sparc_cmodel == CM_MEDLOW) | |
103 #define TARGET_CM_MEDMID (sparc_cmodel == CM_MEDMID) | |
104 #define TARGET_CM_MEDANY (sparc_cmodel == CM_MEDANY) | |
105 #define TARGET_CM_EMBMEDANY (sparc_cmodel == CM_EMBMEDANY) | |
106 | |
107 #define SPARC_DEFAULT_CMODEL CM_32 | |
108 | |
109 /* Do not use the .note.GNU-stack convention by default. */ | |
110 #define NEED_INDICATE_EXEC_STACK 0 | |
111 | |
112 /* This is call-clobbered in the normal ABI, but is reserved in the | |
113 home grown (aka upward compatible) embedded ABI. */ | |
114 #define EMBMEDANY_BASE_REG "%g4" | |
115 | |
116 /* Values of TARGET_CPU_DEFAULT, set via -D in the Makefile, | |
117 and specified by the user via --with-cpu=foo. | |
118 This specifies the cpu implementation, not the architecture size. */ | |
119 /* Note that TARGET_CPU_v9 is assumed to start the list of 64-bit | |
120 capable cpu's. */ | |
121 #define TARGET_CPU_sparc 0 | |
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122 #define TARGET_CPU_v7 0 /* alias */ |
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123 #define TARGET_CPU_cypress 0 /* alias */ |
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124 #define TARGET_CPU_v8 1 /* generic v8 implementation */ |
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125 #define TARGET_CPU_supersparc 2 |
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126 #define TARGET_CPU_hypersparc 3 |
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127 #define TARGET_CPU_leon 4 |
111 | 128 #define TARGET_CPU_leon3 5 |
129 #define TARGET_CPU_leon3v7 6 | |
130 #define TARGET_CPU_sparclite 7 | |
131 #define TARGET_CPU_f930 7 /* alias */ | |
132 #define TARGET_CPU_f934 7 /* alias */ | |
133 #define TARGET_CPU_sparclite86x 8 | |
134 #define TARGET_CPU_sparclet 9 | |
135 #define TARGET_CPU_tsc701 9 /* alias */ | |
136 #define TARGET_CPU_v9 10 /* generic v9 implementation */ | |
137 #define TARGET_CPU_sparcv9 10 /* alias */ | |
138 #define TARGET_CPU_sparc64 10 /* alias */ | |
139 #define TARGET_CPU_ultrasparc 11 | |
140 #define TARGET_CPU_ultrasparc3 12 | |
141 #define TARGET_CPU_niagara 13 | |
142 #define TARGET_CPU_niagara2 14 | |
143 #define TARGET_CPU_niagara3 15 | |
144 #define TARGET_CPU_niagara4 16 | |
145 #define TARGET_CPU_niagara7 19 | |
146 #define TARGET_CPU_m8 20 | |
0 | 147 |
148 #if TARGET_CPU_DEFAULT == TARGET_CPU_v9 \ | |
149 || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc \ | |
150 || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc3 \ | |
151 || TARGET_CPU_DEFAULT == TARGET_CPU_niagara \ | |
111 | 152 || TARGET_CPU_DEFAULT == TARGET_CPU_niagara2 \ |
153 || TARGET_CPU_DEFAULT == TARGET_CPU_niagara3 \ | |
154 || TARGET_CPU_DEFAULT == TARGET_CPU_niagara4 \ | |
155 || TARGET_CPU_DEFAULT == TARGET_CPU_niagara7 \ | |
156 || TARGET_CPU_DEFAULT == TARGET_CPU_m8 | |
0 | 157 |
158 #define CPP_CPU32_DEFAULT_SPEC "" | |
159 #define ASM_CPU32_DEFAULT_SPEC "" | |
160 | |
161 #if TARGET_CPU_DEFAULT == TARGET_CPU_v9 | |
162 /* ??? What does Sun's CC pass? */ | |
163 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" | |
164 /* ??? It's not clear how other assemblers will handle this, so by default | |
165 use GAS. Sun's Solaris assembler recognizes -xarch=v8plus, but this case | |
166 is handled in sol2.h. */ | |
167 #define ASM_CPU64_DEFAULT_SPEC "-Av9" | |
168 #endif | |
169 #if TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc | |
170 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" | |
171 #define ASM_CPU64_DEFAULT_SPEC "-Av9a" | |
172 #endif | |
173 #if TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc3 | |
174 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" | |
175 #define ASM_CPU64_DEFAULT_SPEC "-Av9b" | |
176 #endif | |
177 #if TARGET_CPU_DEFAULT == TARGET_CPU_niagara | |
178 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" | |
179 #define ASM_CPU64_DEFAULT_SPEC "-Av9b" | |
180 #endif | |
181 #if TARGET_CPU_DEFAULT == TARGET_CPU_niagara2 | |
182 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" | |
183 #define ASM_CPU64_DEFAULT_SPEC "-Av9b" | |
184 #endif | |
111 | 185 #if TARGET_CPU_DEFAULT == TARGET_CPU_niagara3 |
186 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" | |
187 #define ASM_CPU64_DEFAULT_SPEC "-Av9" AS_NIAGARA3_FLAG | |
188 #endif | |
189 #if TARGET_CPU_DEFAULT == TARGET_CPU_niagara4 | |
190 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" | |
191 #define ASM_CPU64_DEFAULT_SPEC AS_NIAGARA4_FLAG | |
192 #endif | |
193 #if TARGET_CPU_DEFAULT == TARGET_CPU_niagara7 | |
194 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" | |
195 #define ASM_CPU64_DEFAULT_SPEC AS_NIAGARA7_FLAG | |
196 #endif | |
197 #if TARGET_CPU_DEFAULT == TARGET_CPU_m8 | |
198 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" | |
199 #define ASM_CPU64_DEFAULT_SPEC AS_M8_FLAG | |
200 #endif | |
0 | 201 |
202 #else | |
203 | |
204 #define CPP_CPU64_DEFAULT_SPEC "" | |
205 #define ASM_CPU64_DEFAULT_SPEC "" | |
206 | |
207 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparc \ | |
208 || TARGET_CPU_DEFAULT == TARGET_CPU_v8 | |
209 #define CPP_CPU32_DEFAULT_SPEC "" | |
210 #define ASM_CPU32_DEFAULT_SPEC "" | |
211 #endif | |
212 | |
213 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclet | |
214 #define CPP_CPU32_DEFAULT_SPEC "-D__sparclet__" | |
215 #define ASM_CPU32_DEFAULT_SPEC "-Asparclet" | |
216 #endif | |
217 | |
218 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclite | |
219 #define CPP_CPU32_DEFAULT_SPEC "-D__sparclite__" | |
220 #define ASM_CPU32_DEFAULT_SPEC "-Asparclite" | |
221 #endif | |
222 | |
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223 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclite86x |
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224 #define CPP_CPU32_DEFAULT_SPEC "-D__sparclite86x__" |
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225 #define ASM_CPU32_DEFAULT_SPEC "-Asparclite" |
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226 #endif |
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227 |
0 | 228 #if TARGET_CPU_DEFAULT == TARGET_CPU_supersparc |
229 #define CPP_CPU32_DEFAULT_SPEC "-D__supersparc__ -D__sparc_v8__" | |
230 #define ASM_CPU32_DEFAULT_SPEC "" | |
231 #endif | |
232 | |
233 #if TARGET_CPU_DEFAULT == TARGET_CPU_hypersparc | |
234 #define CPP_CPU32_DEFAULT_SPEC "-D__hypersparc__ -D__sparc_v8__" | |
235 #define ASM_CPU32_DEFAULT_SPEC "" | |
236 #endif | |
237 | |
111 | 238 #if TARGET_CPU_DEFAULT == TARGET_CPU_leon \ |
239 || TARGET_CPU_DEFAULT == TARGET_CPU_leon3 | |
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240 #define CPP_CPU32_DEFAULT_SPEC "-D__leon__ -D__sparc_v8__" |
111 | 241 #define ASM_CPU32_DEFAULT_SPEC AS_LEON_FLAG |
242 #endif | |
243 | |
244 #if TARGET_CPU_DEFAULT == TARGET_CPU_leon3v7 | |
245 #define CPP_CPU32_DEFAULT_SPEC "-D__leon__" | |
246 #define ASM_CPU32_DEFAULT_SPEC AS_LEONV7_FLAG | |
0 | 247 #endif |
248 | |
249 #endif | |
250 | |
251 #if !defined(CPP_CPU32_DEFAULT_SPEC) || !defined(CPP_CPU64_DEFAULT_SPEC) | |
252 #error Unrecognized value in TARGET_CPU_DEFAULT. | |
253 #endif | |
254 | |
255 #ifdef SPARC_BI_ARCH | |
256 | |
257 #define CPP_CPU_DEFAULT_SPEC \ | |
258 (DEFAULT_ARCH32_P ? "\ | |
259 %{m64:" CPP_CPU64_DEFAULT_SPEC "} \ | |
260 %{!m64:" CPP_CPU32_DEFAULT_SPEC "} \ | |
261 " : "\ | |
262 %{m32:" CPP_CPU32_DEFAULT_SPEC "} \ | |
263 %{!m32:" CPP_CPU64_DEFAULT_SPEC "} \ | |
264 ") | |
265 #define ASM_CPU_DEFAULT_SPEC \ | |
266 (DEFAULT_ARCH32_P ? "\ | |
267 %{m64:" ASM_CPU64_DEFAULT_SPEC "} \ | |
268 %{!m64:" ASM_CPU32_DEFAULT_SPEC "} \ | |
269 " : "\ | |
270 %{m32:" ASM_CPU32_DEFAULT_SPEC "} \ | |
271 %{!m32:" ASM_CPU64_DEFAULT_SPEC "} \ | |
272 ") | |
273 | |
274 #else /* !SPARC_BI_ARCH */ | |
275 | |
276 #define CPP_CPU_DEFAULT_SPEC (DEFAULT_ARCH32_P ? CPP_CPU32_DEFAULT_SPEC : CPP_CPU64_DEFAULT_SPEC) | |
277 #define ASM_CPU_DEFAULT_SPEC (DEFAULT_ARCH32_P ? ASM_CPU32_DEFAULT_SPEC : ASM_CPU64_DEFAULT_SPEC) | |
278 | |
279 #endif /* !SPARC_BI_ARCH */ | |
280 | |
281 /* Define macros to distinguish architectures. */ | |
282 | |
283 /* Common CPP definitions used by CPP_SPEC amongst the various targets | |
284 for handling -mcpu=xxx switches. */ | |
285 #define CPP_CPU_SPEC "\ | |
286 %{mcpu=sparclet:-D__sparclet__} %{mcpu=tsc701:-D__sparclet__} \ | |
287 %{mcpu=sparclite:-D__sparclite__} \ | |
288 %{mcpu=f930:-D__sparclite__} %{mcpu=f934:-D__sparclite__} \ | |
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parents:
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289 %{mcpu=sparclite86x:-D__sparclite86x__} \ |
0 | 290 %{mcpu=v8:-D__sparc_v8__} \ |
291 %{mcpu=supersparc:-D__supersparc__ -D__sparc_v8__} \ | |
292 %{mcpu=hypersparc:-D__hypersparc__ -D__sparc_v8__} \ | |
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293 %{mcpu=leon:-D__leon__ -D__sparc_v8__} \ |
111 | 294 %{mcpu=leon3:-D__leon__ -D__sparc_v8__} \ |
295 %{mcpu=leon3v7:-D__leon__} \ | |
0 | 296 %{mcpu=v9:-D__sparc_v9__} \ |
297 %{mcpu=ultrasparc:-D__sparc_v9__} \ | |
298 %{mcpu=ultrasparc3:-D__sparc_v9__} \ | |
299 %{mcpu=niagara:-D__sparc_v9__} \ | |
300 %{mcpu=niagara2:-D__sparc_v9__} \ | |
111 | 301 %{mcpu=niagara3:-D__sparc_v9__} \ |
302 %{mcpu=niagara4:-D__sparc_v9__} \ | |
303 %{mcpu=niagara7:-D__sparc_v9__} \ | |
304 %{mcpu=m8:-D__sparc_v9__} \ | |
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305 %{!mcpu*:%(cpp_cpu_default)} \ |
0 | 306 " |
307 #define CPP_ARCH32_SPEC "" | |
308 #define CPP_ARCH64_SPEC "-D__arch64__" | |
309 | |
310 #define CPP_ARCH_DEFAULT_SPEC \ | |
311 (DEFAULT_ARCH32_P ? CPP_ARCH32_SPEC : CPP_ARCH64_SPEC) | |
312 | |
313 #define CPP_ARCH_SPEC "\ | |
314 %{m32:%(cpp_arch32)} \ | |
315 %{m64:%(cpp_arch64)} \ | |
316 %{!m32:%{!m64:%(cpp_arch_default)}} \ | |
317 " | |
318 | |
111 | 319 /* Macros to distinguish the endianness, window model and FP support. */ |
320 #define CPP_OTHER_SPEC "\ | |
321 %{mflat:-D_FLAT} \ | |
322 %{msoft-float:-D_SOFT_FLOAT} \ | |
323 " | |
0 | 324 |
325 /* Macros to distinguish the particular subtarget. */ | |
326 #define CPP_SUBTARGET_SPEC "" | |
327 | |
111 | 328 #define CPP_SPEC \ |
329 "%(cpp_cpu) %(cpp_arch) %(cpp_endian) %(cpp_other) %(cpp_subtarget)" | |
0 | 330 |
331 /* This used to translate -dalign to -malign, but that is no good | |
332 because it can't turn off the usual meaning of making debugging dumps. */ | |
333 | |
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334 #define CC1_SPEC "" |
0 | 335 |
336 /* Override in target specific files. */ | |
337 #define ASM_CPU_SPEC "\ | |
338 %{mcpu=sparclet:-Asparclet} %{mcpu=tsc701:-Asparclet} \ | |
339 %{mcpu=sparclite:-Asparclite} \ | |
340 %{mcpu=sparclite86x:-Asparclite} \ | |
341 %{mcpu=f930:-Asparclite} %{mcpu=f934:-Asparclite} \ | |
111 | 342 %{mcpu=v8:-Av8} \ |
343 %{mcpu=supersparc:-Av8} \ | |
344 %{mcpu=hypersparc:-Av8} \ | |
345 %{mcpu=leon:" AS_LEON_FLAG "} \ | |
346 %{mcpu=leon3:" AS_LEON_FLAG "} \ | |
347 %{mcpu=leon3v7:" AS_LEONV7_FLAG "} \ | |
0 | 348 %{mv8plus:-Av8plus} \ |
349 %{mcpu=v9:-Av9} \ | |
350 %{mcpu=ultrasparc:%{!mv8plus:-Av9a}} \ | |
351 %{mcpu=ultrasparc3:%{!mv8plus:-Av9b}} \ | |
352 %{mcpu=niagara:%{!mv8plus:-Av9b}} \ | |
353 %{mcpu=niagara2:%{!mv8plus:-Av9b}} \ | |
111 | 354 %{mcpu=niagara3:%{!mv8plus:-Av9" AS_NIAGARA3_FLAG "}} \ |
355 %{mcpu=niagara4:%{!mv8plus:" AS_NIAGARA4_FLAG "}} \ | |
356 %{mcpu=niagara7:%{!mv8plus:" AS_NIAGARA7_FLAG "}} \ | |
357 %{mcpu=m8:%{!mv8plus:" AS_M8_FLAG "}} \ | |
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358 %{!mcpu*:%(asm_cpu_default)} \ |
0 | 359 " |
360 | |
361 /* Word size selection, among other things. | |
362 This is what GAS uses. Add %(asm_arch) to ASM_SPEC to enable. */ | |
363 | |
364 #define ASM_ARCH32_SPEC "-32" | |
365 #ifdef HAVE_AS_REGISTER_PSEUDO_OP | |
366 #define ASM_ARCH64_SPEC "-64 -no-undeclared-regs" | |
367 #else | |
368 #define ASM_ARCH64_SPEC "-64" | |
369 #endif | |
370 #define ASM_ARCH_DEFAULT_SPEC \ | |
371 (DEFAULT_ARCH32_P ? ASM_ARCH32_SPEC : ASM_ARCH64_SPEC) | |
372 | |
373 #define ASM_ARCH_SPEC "\ | |
374 %{m32:%(asm_arch32)} \ | |
375 %{m64:%(asm_arch64)} \ | |
376 %{!m32:%{!m64:%(asm_arch_default)}} \ | |
377 " | |
378 | |
379 #ifdef HAVE_AS_RELAX_OPTION | |
380 #define ASM_RELAX_SPEC "%{!mno-relax:-relax}" | |
381 #else | |
382 #define ASM_RELAX_SPEC "" | |
383 #endif | |
384 | |
385 /* Special flags to the Sun-4 assembler when using pipe for input. */ | |
386 | |
387 #define ASM_SPEC "\ | |
111 | 388 %{!pg:%{!p:%{" FPIE_OR_FPIC_SPEC ":-k}}} %{keep-local-as-symbols:-L} \ |
0 | 389 %(asm_cpu) %(asm_relax)" |
390 | |
391 /* This macro defines names of additional specifications to put in the specs | |
392 that can be used in various specifications like CC1_SPEC. Its definition | |
393 is an initializer with a subgrouping for each command option. | |
394 | |
395 Each subgrouping contains a string constant, that defines the | |
396 specification name, and a string constant that used by the GCC driver | |
397 program. | |
398 | |
399 Do not define this macro if it does not need to do anything. */ | |
400 | |
401 #define EXTRA_SPECS \ | |
402 { "cpp_cpu", CPP_CPU_SPEC }, \ | |
403 { "cpp_cpu_default", CPP_CPU_DEFAULT_SPEC }, \ | |
404 { "cpp_arch32", CPP_ARCH32_SPEC }, \ | |
405 { "cpp_arch64", CPP_ARCH64_SPEC }, \ | |
406 { "cpp_arch_default", CPP_ARCH_DEFAULT_SPEC },\ | |
407 { "cpp_arch", CPP_ARCH_SPEC }, \ | |
111 | 408 { "cpp_other", CPP_OTHER_SPEC }, \ |
0 | 409 { "cpp_subtarget", CPP_SUBTARGET_SPEC }, \ |
410 { "asm_cpu", ASM_CPU_SPEC }, \ | |
411 { "asm_cpu_default", ASM_CPU_DEFAULT_SPEC }, \ | |
412 { "asm_arch32", ASM_ARCH32_SPEC }, \ | |
413 { "asm_arch64", ASM_ARCH64_SPEC }, \ | |
414 { "asm_relax", ASM_RELAX_SPEC }, \ | |
415 { "asm_arch_default", ASM_ARCH_DEFAULT_SPEC },\ | |
416 { "asm_arch", ASM_ARCH_SPEC }, \ | |
417 SUBTARGET_EXTRA_SPECS | |
418 | |
419 #define SUBTARGET_EXTRA_SPECS | |
420 | |
421 /* Because libgcc can generate references back to libc (via .umul etc.) we have | |
422 to list libc again after the second libgcc. */ | |
423 #define LINK_GCC_C_SEQUENCE_SPEC "%G %L %G %L" | |
424 | |
425 | |
426 #define PTRDIFF_TYPE (TARGET_ARCH64 ? "long int" : "int") | |
427 #define SIZE_TYPE (TARGET_ARCH64 ? "long unsigned int" : "unsigned int") | |
428 | |
429 /* ??? This should be 32 bits for v9 but what can we do? */ | |
430 #define WCHAR_TYPE "short unsigned int" | |
431 #define WCHAR_TYPE_SIZE 16 | |
432 | |
433 /* Mask of all CPU selection flags. */ | |
111 | 434 #define MASK_ISA \ |
435 (MASK_SPARCLITE + MASK_SPARCLET + MASK_LEON + MASK_LEON3 \ | |
436 + MASK_V8 + MASK_V9 + MASK_DEPRECATED_V8_INSNS) | |
0 | 437 |
111 | 438 /* Mask of all CPU feature flags. */ |
439 #define MASK_FEATURES \ | |
440 (MASK_FPU + MASK_HARD_QUAD + MASK_VIS + MASK_VIS2 + MASK_VIS3 \ | |
441 + MASK_VIS4 + MASK_CBCOND + MASK_FMAF + MASK_FSMULD \ | |
442 + MASK_POPC + MASK_SUBXC) | |
443 | |
444 /* TARGET_HARD_MUL: Use 32-bit hardware multiply instructions but not %y. */ | |
445 #define TARGET_HARD_MUL \ | |
446 (TARGET_SPARCLITE || TARGET_SPARCLET \ | |
447 || TARGET_V8 || TARGET_DEPRECATED_V8_INSNS) | |
0 | 448 |
111 | 449 /* TARGET_HARD_MUL32: Use 32-bit hardware multiply instructions with %y |
450 to get high 32 bits. False in 64-bit or V8+ because multiply stores | |
451 a 64-bit result in a register. */ | |
452 #define TARGET_HARD_MUL32 \ | |
453 (TARGET_HARD_MUL && TARGET_ARCH32 && !TARGET_V8PLUS) | |
0 | 454 |
455 /* MASK_APP_REGS must always be the default because that's what | |
456 FIXED_REGISTERS is set to and -ffixed- is processed before | |
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457 TARGET_CONDITIONAL_REGISTER_USAGE is called (where we process |
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458 -mno-app-regs). */ |
0 | 459 #define TARGET_DEFAULT (MASK_APP_REGS + MASK_FPU) |
460 | |
461 /* Recast the cpu class to be the cpu attribute. | |
462 Every file includes us, but not every file includes insn-attr.h. */ | |
463 #define sparc_cpu_attr ((enum attr_cpu) sparc_cpu) | |
464 | |
465 /* Support for a compile-time default CPU, et cetera. The rules are: | |
466 --with-cpu is ignored if -mcpu is specified. | |
467 --with-tune is ignored if -mtune is specified. | |
468 --with-float is ignored if -mhard-float, -msoft-float, -mfpu, or -mno-fpu | |
469 are specified. */ | |
470 #define OPTION_DEFAULT_SPECS \ | |
471 {"cpu", "%{!mcpu=*:-mcpu=%(VALUE)}" }, \ | |
472 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \ | |
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473 {"float", "%{!msoft-float:%{!mhard-float:%{!mfpu:%{!mno-fpu:-m%(VALUE)-float}}}}" } |
0 | 474 |
475 /* target machine storage layout */ | |
476 | |
477 /* Define this if most significant bit is lowest numbered | |
478 in instructions that operate on numbered bit-fields. */ | |
479 #define BITS_BIG_ENDIAN 1 | |
480 | |
481 /* Define this if most significant byte of a word is the lowest numbered. */ | |
482 #define BYTES_BIG_ENDIAN 1 | |
483 | |
484 /* Define this if most significant word of a multiword number is the lowest | |
485 numbered. */ | |
486 #define WORDS_BIG_ENDIAN 1 | |
487 | |
488 #define MAX_BITS_PER_WORD 64 | |
489 | |
490 /* Width of a word, in units (bytes). */ | |
491 #define UNITS_PER_WORD (TARGET_ARCH64 ? 8 : 4) | |
492 #ifdef IN_LIBGCC2 | |
493 #define MIN_UNITS_PER_WORD UNITS_PER_WORD | |
494 #else | |
495 #define MIN_UNITS_PER_WORD 4 | |
496 #endif | |
497 | |
498 /* Now define the sizes of the C data types. */ | |
499 #define SHORT_TYPE_SIZE 16 | |
500 #define INT_TYPE_SIZE 32 | |
501 #define LONG_TYPE_SIZE (TARGET_ARCH64 ? 64 : 32) | |
502 #define LONG_LONG_TYPE_SIZE 64 | |
503 #define FLOAT_TYPE_SIZE 32 | |
504 #define DOUBLE_TYPE_SIZE 64 | |
505 | |
506 /* LONG_DOUBLE_TYPE_SIZE is defined per OS even though the | |
507 SPARC ABI says that it is 128-bit wide. */ | |
508 /* #define LONG_DOUBLE_TYPE_SIZE 128 */ | |
509 | |
510 /* The widest floating-point format really supported by the hardware. */ | |
511 #define WIDEST_HARDWARE_FP_SIZE 64 | |
512 | |
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513 /* Width in bits of a pointer. This is the size of ptr_mode. */ |
0 | 514 #define POINTER_SIZE (TARGET_PTR64 ? 64 : 32) |
515 | |
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516 /* This is the machine mode used for addresses. */ |
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517 #define Pmode (TARGET_ARCH64 ? DImode : SImode) |
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518 |
0 | 519 /* If we have to extend pointers (only when TARGET_ARCH64 and not |
520 TARGET_PTR64), we want to do it unsigned. This macro does nothing | |
521 if ptr_mode and Pmode are the same. */ | |
522 #define POINTERS_EXTEND_UNSIGNED 1 | |
523 | |
524 /* Allocation boundary (in *bits*) for storing arguments in argument list. */ | |
525 #define PARM_BOUNDARY (TARGET_ARCH64 ? 64 : 32) | |
526 | |
527 /* Boundary (in *bits*) on which stack pointer should be aligned. */ | |
528 /* FIXME, this is wrong when TARGET_ARCH64 and TARGET_STACK_BIAS, because | |
529 then %sp+2047 is 128-bit aligned so %sp is really only byte-aligned. */ | |
530 #define STACK_BOUNDARY (TARGET_ARCH64 ? 128 : 64) | |
111 | 531 |
0 | 532 /* Temporary hack until the FIXME above is fixed. */ |
533 #define SPARC_STACK_BOUNDARY_HACK (TARGET_ARCH64 && TARGET_STACK_BIAS) | |
534 | |
535 /* ALIGN FRAMES on double word boundaries */ | |
111 | 536 #define SPARC_STACK_ALIGN(LOC) ROUND_UP ((LOC), UNITS_PER_WORD * 2) |
0 | 537 |
538 /* Allocation boundary (in *bits*) for the code of a function. */ | |
539 #define FUNCTION_BOUNDARY 32 | |
540 | |
541 /* Alignment of field after `int : 0' in a structure. */ | |
542 #define EMPTY_FIELD_BOUNDARY (TARGET_ARCH64 ? 64 : 32) | |
543 | |
544 /* Every structure's size must be a multiple of this. */ | |
545 #define STRUCTURE_SIZE_BOUNDARY 8 | |
546 | |
547 /* A bit-field declared as `int' forces `int' alignment for the struct. */ | |
548 #define PCC_BITFIELD_TYPE_MATTERS 1 | |
549 | |
550 /* No data type wants to be aligned rounder than this. */ | |
551 #define BIGGEST_ALIGNMENT (TARGET_ARCH64 ? 128 : 64) | |
552 | |
553 /* The best alignment to use in cases where we have a choice. */ | |
554 #define FASTEST_ALIGNMENT 64 | |
555 | |
556 /* Define this macro as an expression for the alignment of a structure | |
557 (given by STRUCT as a tree node) if the alignment computed in the | |
558 usual way is COMPUTED and the alignment explicitly specified was | |
559 SPECIFIED. | |
560 | |
561 The default is to use SPECIFIED if it is larger; otherwise, use | |
562 the smaller of COMPUTED and `BIGGEST_ALIGNMENT' */ | |
563 #define ROUND_TYPE_ALIGN(STRUCT, COMPUTED, SPECIFIED) \ | |
564 (TARGET_FASTER_STRUCTS ? \ | |
565 ((TREE_CODE (STRUCT) == RECORD_TYPE \ | |
566 || TREE_CODE (STRUCT) == UNION_TYPE \ | |
567 || TREE_CODE (STRUCT) == QUAL_UNION_TYPE) \ | |
568 && TYPE_FIELDS (STRUCT) != 0 \ | |
569 ? MAX (MAX ((COMPUTED), (SPECIFIED)), BIGGEST_ALIGNMENT) \ | |
570 : MAX ((COMPUTED), (SPECIFIED))) \ | |
571 : MAX ((COMPUTED), (SPECIFIED))) | |
572 | |
111 | 573 /* An integer expression for the size in bits of the largest integer machine |
574 mode that should actually be used. We allow pairs of registers. */ | |
575 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_ARCH64 ? TImode : DImode) | |
576 | |
577 /* We need 2 words, so we can save the stack pointer and the return register | |
578 of the function containing a non-local goto target. */ | |
579 #define STACK_SAVEAREA_MODE(LEVEL) \ | |
580 ((LEVEL) == SAVE_NONLOCAL ? (TARGET_ARCH64 ? TImode : DImode) : Pmode) | |
0 | 581 |
582 /* Make arrays of chars word-aligned for the same reasons. */ | |
583 #define DATA_ALIGNMENT(TYPE, ALIGN) \ | |
584 (TREE_CODE (TYPE) == ARRAY_TYPE \ | |
585 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ | |
586 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN)) | |
587 | |
588 /* Make local arrays of chars word-aligned for the same reasons. */ | |
589 #define LOCAL_ALIGNMENT(TYPE, ALIGN) DATA_ALIGNMENT (TYPE, ALIGN) | |
590 | |
591 /* Set this nonzero if move instructions will actually fail to work | |
592 when given unaligned data. */ | |
593 #define STRICT_ALIGNMENT 1 | |
594 | |
595 /* Things that must be doubleword aligned cannot go in the text section, | |
596 because the linker fails to align the text section enough! | |
597 Put them in the data section. This macro is only used in this file. */ | |
598 #define MAX_TEXT_ALIGN 32 | |
599 | |
600 /* Standard register usage. */ | |
601 | |
602 /* Number of actual hardware registers. | |
603 The hardware registers are assigned numbers for the compiler | |
604 from 0 to just below FIRST_PSEUDO_REGISTER. | |
605 All registers that the compiler knows about must be given numbers, | |
606 even those that are not normally considered general registers. | |
607 | |
608 SPARC has 32 integer registers and 32 floating point registers. | |
609 64-bit SPARC has 32 additional fp regs, but the odd numbered ones are not | |
610 accessible. We still account for them to simplify register computations | |
611 (e.g.: in CLASS_MAX_NREGS). There are also 4 fp condition code registers, so | |
612 32+32+32+4 == 100. | |
613 Register 100 is used as the integer condition code register. | |
111 | 614 Register 101 is used as the soft frame pointer register. |
615 Register 102 is used as the general status register by VIS instructions. */ | |
0 | 616 |
111 | 617 #define FIRST_PSEUDO_REGISTER 103 |
0 | 618 |
111 | 619 #define SPARC_FIRST_INT_REG 0 |
620 #define SPARC_LAST_INT_REG 31 | |
0 | 621 #define SPARC_FIRST_FP_REG 32 |
622 /* Additional V9 fp regs. */ | |
623 #define SPARC_FIRST_V9_FP_REG 64 | |
624 #define SPARC_LAST_V9_FP_REG 95 | |
625 /* V9 %fcc[0123]. V8 uses (figuratively) %fcc0. */ | |
626 #define SPARC_FIRST_V9_FCC_REG 96 | |
627 #define SPARC_LAST_V9_FCC_REG 99 | |
628 /* V8 fcc reg. */ | |
629 #define SPARC_FCC_REG 96 | |
630 /* Integer CC reg. We don't distinguish %icc from %xcc. */ | |
631 #define SPARC_ICC_REG 100 | |
111 | 632 #define SPARC_GSR_REG 102 |
0 | 633 |
634 /* Nonzero if REGNO is an fp reg. */ | |
635 #define SPARC_FP_REG_P(REGNO) \ | |
636 ((REGNO) >= SPARC_FIRST_FP_REG && (REGNO) <= SPARC_LAST_V9_FP_REG) | |
637 | |
111 | 638 /* Nonzero if REGNO is an int reg. */ |
639 #define SPARC_INT_REG_P(REGNO) \ | |
640 (((unsigned) (REGNO)) <= SPARC_LAST_INT_REG) | |
641 | |
0 | 642 /* Argument passing regs. */ |
643 #define SPARC_OUTGOING_INT_ARG_FIRST 8 | |
111 | 644 #define SPARC_INCOMING_INT_ARG_FIRST (TARGET_FLAT ? 8 : 24) |
0 | 645 #define SPARC_FP_ARG_FIRST 32 |
646 | |
647 /* 1 for registers that have pervasive standard uses | |
648 and are not available for the register allocator. | |
649 | |
650 On non-v9 systems: | |
651 g1 is free to use as temporary. | |
652 g2-g4 are reserved for applications. Gcc normally uses them as | |
653 temporaries, but this can be disabled via the -mno-app-regs option. | |
654 g5 through g7 are reserved for the operating system. | |
655 | |
656 On v9 systems: | |
657 g1,g5 are free to use as temporaries, and are free to use between calls | |
658 if the call is to an external function via the PLT. | |
659 g4 is free to use as a temporary in the non-embedded case. | |
660 g4 is reserved in the embedded case. | |
661 g2-g3 are reserved for applications. Gcc normally uses them as | |
662 temporaries, but this can be disabled via the -mno-app-regs option. | |
663 g6-g7 are reserved for the operating system (or application in | |
664 embedded case). | |
665 ??? Register 1 is used as a temporary by the 64 bit sethi pattern, so must | |
666 currently be a fixed register until this pattern is rewritten. | |
667 Register 1 is also used when restoring call-preserved registers in large | |
668 stack frames. | |
669 | |
670 Registers fixed in arch32 and not arch64 (or vice-versa) are marked in | |
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671 TARGET_CONDITIONAL_REGISTER_USAGE in order to properly handle -ffixed-. |
0 | 672 */ |
673 | |
674 #define FIXED_REGISTERS \ | |
675 {1, 0, 2, 2, 2, 2, 1, 1, \ | |
676 0, 0, 0, 0, 0, 0, 1, 0, \ | |
677 0, 0, 0, 0, 0, 0, 0, 0, \ | |
111 | 678 0, 0, 0, 0, 0, 0, 0, 1, \ |
0 | 679 \ |
680 0, 0, 0, 0, 0, 0, 0, 0, \ | |
681 0, 0, 0, 0, 0, 0, 0, 0, \ | |
682 0, 0, 0, 0, 0, 0, 0, 0, \ | |
683 0, 0, 0, 0, 0, 0, 0, 0, \ | |
684 \ | |
685 0, 0, 0, 0, 0, 0, 0, 0, \ | |
686 0, 0, 0, 0, 0, 0, 0, 0, \ | |
687 0, 0, 0, 0, 0, 0, 0, 0, \ | |
688 0, 0, 0, 0, 0, 0, 0, 0, \ | |
689 \ | |
111 | 690 0, 0, 0, 0, 1, 1, 1} |
0 | 691 |
692 /* 1 for registers not available across function calls. | |
693 These must include the FIXED_REGISTERS and also any | |
694 registers that can be used without being saved. | |
695 The latter must include the registers where values are returned | |
696 and the register where structure-value addresses are passed. | |
697 Aside from that, you can include as many other registers as you like. */ | |
698 | |
699 #define CALL_USED_REGISTERS \ | |
700 {1, 1, 1, 1, 1, 1, 1, 1, \ | |
701 1, 1, 1, 1, 1, 1, 1, 1, \ | |
702 0, 0, 0, 0, 0, 0, 0, 0, \ | |
111 | 703 0, 0, 0, 0, 0, 0, 0, 1, \ |
0 | 704 \ |
705 1, 1, 1, 1, 1, 1, 1, 1, \ | |
706 1, 1, 1, 1, 1, 1, 1, 1, \ | |
707 1, 1, 1, 1, 1, 1, 1, 1, \ | |
708 1, 1, 1, 1, 1, 1, 1, 1, \ | |
709 \ | |
710 1, 1, 1, 1, 1, 1, 1, 1, \ | |
711 1, 1, 1, 1, 1, 1, 1, 1, \ | |
712 1, 1, 1, 1, 1, 1, 1, 1, \ | |
713 1, 1, 1, 1, 1, 1, 1, 1, \ | |
714 \ | |
111 | 715 1, 1, 1, 1, 1, 1, 1} |
0 | 716 |
111 | 717 /* 1 for registers not available across function calls. |
718 Unlike the above, this need not include the FIXED_REGISTERS, but any | |
719 registers that can be used without being saved. | |
720 The latter must include the registers where values are returned | |
721 and the register where structure-value addresses are passed. | |
722 Aside from that, you can include as many other registers as you like. */ | |
0 | 723 |
111 | 724 #define CALL_REALLY_USED_REGISTERS \ |
725 {1, 1, 1, 1, 1, 1, 1, 1, \ | |
726 1, 1, 1, 1, 1, 1, 1, 1, \ | |
727 0, 0, 0, 0, 0, 0, 0, 0, \ | |
728 0, 0, 0, 0, 0, 0, 0, 0, \ | |
729 \ | |
730 1, 1, 1, 1, 1, 1, 1, 1, \ | |
731 1, 1, 1, 1, 1, 1, 1, 1, \ | |
732 1, 1, 1, 1, 1, 1, 1, 1, \ | |
733 1, 1, 1, 1, 1, 1, 1, 1, \ | |
734 \ | |
735 1, 1, 1, 1, 1, 1, 1, 1, \ | |
736 1, 1, 1, 1, 1, 1, 1, 1, \ | |
737 1, 1, 1, 1, 1, 1, 1, 1, \ | |
738 1, 1, 1, 1, 1, 1, 1, 1, \ | |
739 \ | |
740 1, 1, 1, 1, 1, 1, 1} | |
0 | 741 |
742 /* Due to the ARCH64 discrepancy above we must override this next | |
743 macro too. */ | |
111 | 744 #define REGMODE_NATURAL_SIZE(MODE) sparc_regmode_natural_size (MODE) |
0 | 745 |
746 /* Value is 1 if it is OK to rename a hard register FROM to another hard | |
747 register TO. We cannot rename %g1 as it may be used before the save | |
748 register window instruction in the prologue. */ | |
749 #define HARD_REGNO_RENAME_OK(FROM, TO) ((FROM) != 1) | |
750 | |
751 /* Specify the registers used for certain standard purposes. | |
752 The values of these macros are register numbers. */ | |
753 | |
754 /* Register to use for pushing function arguments. */ | |
755 #define STACK_POINTER_REGNUM 14 | |
756 | |
757 /* The stack bias (amount by which the hardware register is offset by). */ | |
758 #define SPARC_STACK_BIAS ((TARGET_ARCH64 && TARGET_STACK_BIAS) ? 2047 : 0) | |
759 | |
760 /* Actual top-of-stack address is 92/176 greater than the contents of the | |
761 stack pointer register for !v9/v9. That is: | |
762 - !v9: 64 bytes for the in and local registers, 4 bytes for structure return | |
763 address, and 6*4 bytes for the 6 register parameters. | |
764 - v9: 128 bytes for the in and local registers + 6*8 bytes for the integer | |
765 parameter regs. */ | |
766 #define STACK_POINTER_OFFSET (FIRST_PARM_OFFSET(0) + SPARC_STACK_BIAS) | |
767 | |
768 /* Base register for access to local variables of the function. */ | |
769 #define HARD_FRAME_POINTER_REGNUM 30 | |
770 | |
771 /* The soft frame pointer does not have the stack bias applied. */ | |
772 #define FRAME_POINTER_REGNUM 101 | |
773 | |
774 /* Given the stack bias, the stack pointer isn't actually aligned. */ | |
775 #define INIT_EXPANDERS \ | |
776 do { \ | |
777 if (crtl->emit.regno_pointer_align && SPARC_STACK_BIAS) \ | |
778 { \ | |
779 REGNO_POINTER_ALIGN (STACK_POINTER_REGNUM) = BITS_PER_UNIT; \ | |
780 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT; \ | |
781 } \ | |
782 } while (0) | |
783 | |
784 /* Base register for access to arguments of the function. */ | |
785 #define ARG_POINTER_REGNUM FRAME_POINTER_REGNUM | |
786 | |
787 /* Register in which static-chain is passed to a function. This must | |
788 not be a register used by the prologue. */ | |
789 #define STATIC_CHAIN_REGNUM (TARGET_ARCH64 ? 5 : 2) | |
790 | |
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791 /* Register which holds the global offset table, if any. */ |
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792 |
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793 #define GLOBAL_OFFSET_TABLE_REGNUM 23 |
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794 |
0 | 795 /* Register which holds offset table for position-independent |
796 data references. */ | |
797 | |
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798 #define PIC_OFFSET_TABLE_REGNUM \ |
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799 (flag_pic ? GLOBAL_OFFSET_TABLE_REGNUM : INVALID_REGNUM) |
0 | 800 |
801 /* Pick a default value we can notice from override_options: | |
802 !v9: Default is on. | |
803 v9: Default is off. | |
804 Originally it was -1, but later on the container of options changed to | |
805 unsigned byte, so we decided to pick 127 as default value, which does | |
806 reflect an undefined default value in case of 0/1. */ | |
807 | |
808 #define DEFAULT_PCC_STRUCT_RETURN 127 | |
809 | |
810 /* Functions which return large structures get the address | |
811 to place the wanted value at offset 64 from the frame. | |
812 Must reserve 64 bytes for the in and local registers. | |
813 v9: Functions which return large structures get the address to place the | |
814 wanted value from an invisible first argument. */ | |
815 #define STRUCT_VALUE_OFFSET 64 | |
816 | |
817 /* Define the classes of registers for register constraints in the | |
818 machine description. Also define ranges of constants. | |
819 | |
820 One of the classes must always be named ALL_REGS and include all hard regs. | |
821 If there is more than one class, another class must be named NO_REGS | |
822 and contain no registers. | |
823 | |
824 The name GENERAL_REGS must be the name of a class (or an alias for | |
825 another name such as ALL_REGS). This is the class of registers | |
826 that is allowed by "g" or "r" in a register constraint. | |
827 Also, registers outside this class are allocated only when | |
828 instructions express preferences for them. | |
829 | |
830 The classes must be numbered in nondecreasing order; that is, | |
831 a larger-numbered class must never be contained completely | |
832 in a smaller-numbered class. | |
833 | |
834 For any two classes, it is very desirable that there be another | |
835 class that represents their union. */ | |
836 | |
837 /* The SPARC has various kinds of registers: general, floating point, | |
838 and condition codes [well, it has others as well, but none that we | |
839 care directly about]. | |
840 | |
841 For v9 we must distinguish between the upper and lower floating point | |
842 registers because the upper ones can't hold SFmode values. | |
111 | 843 TARGET_HARD_REGNO_MODE_OK won't help here because reload assumes that |
844 register(s) satisfying a group need for a class will also satisfy a | |
845 single need for that class. EXTRA_FP_REGS is a bit of a misnomer as | |
846 it covers all 64 fp regs. | |
0 | 847 |
848 It is important that one class contains all the general and all the standard | |
849 fp regs. Otherwise find_reg() won't properly allocate int regs for moves, | |
850 because reg_class_record() will bias the selection in favor of fp regs, | |
851 because reg_class_subunion[GENERAL_REGS][FP_REGS] will yield FP_REGS, | |
852 because FP_REGS > GENERAL_REGS. | |
853 | |
854 It is also important that one class contain all the general and all | |
855 the fp regs. Otherwise when spilling a DFmode reg, it may be from | |
856 EXTRA_FP_REGS but find_reloads() may use class | |
857 GENERAL_OR_FP_REGS. This will cause allocate_reload_reg() to die | |
858 because the compiler thinks it doesn't have a spill reg when in | |
859 fact it does. | |
860 | |
861 v9 also has 4 floating point condition code registers. Since we don't | |
862 have a class that is the union of FPCC_REGS with either of the others, | |
863 it is important that it appear first. Otherwise the compiler will die | |
864 trying to compile _fixunsdfsi because fix_truncdfsi2 won't match its | |
111 | 865 constraints. */ |
0 | 866 |
867 enum reg_class { NO_REGS, FPCC_REGS, I64_REGS, GENERAL_REGS, FP_REGS, | |
868 EXTRA_FP_REGS, GENERAL_OR_FP_REGS, GENERAL_OR_EXTRA_FP_REGS, | |
869 ALL_REGS, LIM_REG_CLASSES }; | |
870 | |
871 #define N_REG_CLASSES (int) LIM_REG_CLASSES | |
872 | |
873 /* Give names of register classes as strings for dump file. */ | |
874 | |
875 #define REG_CLASS_NAMES \ | |
876 { "NO_REGS", "FPCC_REGS", "I64_REGS", "GENERAL_REGS", "FP_REGS", \ | |
877 "EXTRA_FP_REGS", "GENERAL_OR_FP_REGS", "GENERAL_OR_EXTRA_FP_REGS", \ | |
878 "ALL_REGS" } | |
879 | |
880 /* Define which registers fit in which classes. | |
881 This is an initializer for a vector of HARD_REG_SET | |
882 of length N_REG_CLASSES. */ | |
883 | |
884 #define REG_CLASS_CONTENTS \ | |
885 {{0, 0, 0, 0}, /* NO_REGS */ \ | |
886 {0, 0, 0, 0xf}, /* FPCC_REGS */ \ | |
887 {0xffff, 0, 0, 0}, /* I64_REGS */ \ | |
888 {-1, 0, 0, 0x20}, /* GENERAL_REGS */ \ | |
889 {0, -1, 0, 0}, /* FP_REGS */ \ | |
890 {0, -1, -1, 0}, /* EXTRA_FP_REGS */ \ | |
891 {-1, -1, 0, 0x20}, /* GENERAL_OR_FP_REGS */ \ | |
892 {-1, -1, -1, 0x20}, /* GENERAL_OR_EXTRA_FP_REGS */ \ | |
111 | 893 {-1, -1, -1, 0x7f}} /* ALL_REGS */ |
0 | 894 |
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895 /* The same information, inverted: |
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896 Return the class number of the smallest class containing |
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897 reg number REGNO. This could be a conditional expression |
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898 or could index an array. */ |
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899 |
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900 extern enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER]; |
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901 |
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902 #define REGNO_REG_CLASS(REGNO) sparc_regno_reg_class[(REGNO)] |
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903 |
0 | 904 /* This is the order in which to allocate registers normally. |
905 | |
906 We put %f0-%f7 last among the float registers, so as to make it more | |
907 likely that a pseudo-register which dies in the float return register | |
908 area will get allocated to the float return register, thus saving a move | |
909 instruction at the end of the function. | |
910 | |
911 Similarly for integer return value registers. | |
912 | |
913 We know in this case that we will not end up with a leaf function. | |
914 | |
915 The register allocator is given the global and out registers first | |
916 because these registers are call clobbered and thus less useful to | |
917 global register allocation. | |
918 | |
919 Next we list the local and in registers. They are not call clobbered | |
920 and thus very useful for global register allocation. We list the input | |
921 registers before the locals so that it is more likely the incoming | |
922 arguments received in those registers can just stay there and not be | |
923 reloaded. */ | |
924 | |
925 #define REG_ALLOC_ORDER \ | |
926 { 1, 2, 3, 4, 5, 6, 7, /* %g1-%g7 */ \ | |
927 13, 12, 11, 10, 9, 8, /* %o5-%o0 */ \ | |
928 15, /* %o7 */ \ | |
929 16, 17, 18, 19, 20, 21, 22, 23, /* %l0-%l7 */ \ | |
930 29, 28, 27, 26, 25, 24, 31, /* %i5-%i0,%i7 */\ | |
931 40, 41, 42, 43, 44, 45, 46, 47, /* %f8-%f15 */ \ | |
932 48, 49, 50, 51, 52, 53, 54, 55, /* %f16-%f23 */ \ | |
933 56, 57, 58, 59, 60, 61, 62, 63, /* %f24-%f31 */ \ | |
934 64, 65, 66, 67, 68, 69, 70, 71, /* %f32-%f39 */ \ | |
935 72, 73, 74, 75, 76, 77, 78, 79, /* %f40-%f47 */ \ | |
936 80, 81, 82, 83, 84, 85, 86, 87, /* %f48-%f55 */ \ | |
937 88, 89, 90, 91, 92, 93, 94, 95, /* %f56-%f63 */ \ | |
938 39, 38, 37, 36, 35, 34, 33, 32, /* %f7-%f0 */ \ | |
939 96, 97, 98, 99, /* %fcc0-3 */ \ | |
111 | 940 100, 0, 14, 30, 101, 102 } /* %icc, %g0, %o6, %i6, %sfp, %gsr */ |
0 | 941 |
942 /* This is the order in which to allocate registers for | |
943 leaf functions. If all registers can fit in the global and | |
944 output registers, then we have the possibility of having a leaf | |
945 function. | |
946 | |
947 The macro actually mentioned the input registers first, | |
948 because they get renumbered into the output registers once | |
949 we know really do have a leaf function. | |
950 | |
951 To be more precise, this register allocation order is used | |
952 when %o7 is found to not be clobbered right before register | |
953 allocation. Normally, the reason %o7 would be clobbered is | |
954 due to a call which could not be transformed into a sibling | |
955 call. | |
956 | |
957 As a consequence, it is possible to use the leaf register | |
958 allocation order and not end up with a leaf function. We will | |
959 not get suboptimal register allocation in that case because by | |
960 definition of being potentially leaf, there were no function | |
961 calls. Therefore, allocation order within the local register | |
962 window is not critical like it is when we do have function calls. */ | |
963 | |
964 #define REG_LEAF_ALLOC_ORDER \ | |
965 { 1, 2, 3, 4, 5, 6, 7, /* %g1-%g7 */ \ | |
966 29, 28, 27, 26, 25, 24, /* %i5-%i0 */ \ | |
967 15, /* %o7 */ \ | |
968 13, 12, 11, 10, 9, 8, /* %o5-%o0 */ \ | |
969 16, 17, 18, 19, 20, 21, 22, 23, /* %l0-%l7 */ \ | |
970 40, 41, 42, 43, 44, 45, 46, 47, /* %f8-%f15 */ \ | |
971 48, 49, 50, 51, 52, 53, 54, 55, /* %f16-%f23 */ \ | |
972 56, 57, 58, 59, 60, 61, 62, 63, /* %f24-%f31 */ \ | |
973 64, 65, 66, 67, 68, 69, 70, 71, /* %f32-%f39 */ \ | |
974 72, 73, 74, 75, 76, 77, 78, 79, /* %f40-%f47 */ \ | |
975 80, 81, 82, 83, 84, 85, 86, 87, /* %f48-%f55 */ \ | |
976 88, 89, 90, 91, 92, 93, 94, 95, /* %f56-%f63 */ \ | |
977 39, 38, 37, 36, 35, 34, 33, 32, /* %f7-%f0 */ \ | |
978 96, 97, 98, 99, /* %fcc0-3 */ \ | |
111 | 979 100, 0, 14, 30, 31, 101, 102 } /* %icc, %g0, %o6, %i6, %i7, %sfp, %gsr */ |
0 | 980 |
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981 #define ADJUST_REG_ALLOC_ORDER order_regs_for_local_alloc () |
0 | 982 |
983 extern char sparc_leaf_regs[]; | |
984 #define LEAF_REGISTERS sparc_leaf_regs | |
985 | |
986 extern char leaf_reg_remap[]; | |
987 #define LEAF_REG_REMAP(REGNO) (leaf_reg_remap[REGNO]) | |
988 | |
989 /* The class value for index registers, and the one for base regs. */ | |
990 #define INDEX_REG_CLASS GENERAL_REGS | |
991 #define BASE_REG_CLASS GENERAL_REGS | |
992 | |
993 /* Local macro to handle the two v9 classes of FP regs. */ | |
994 #define FP_REG_CLASS_P(CLASS) ((CLASS) == FP_REGS || (CLASS) == EXTRA_FP_REGS) | |
995 | |
111 | 996 /* Predicate for 2-bit and 5-bit unsigned constants. */ |
997 #define SPARC_IMM2_P(X) (((unsigned HOST_WIDE_INT) (X) & ~0x3) == 0) | |
998 #define SPARC_IMM5_P(X) (((unsigned HOST_WIDE_INT) (X) & ~0x1F) == 0) | |
999 | |
1000 /* Predicates for 5-bit, 10-bit, 11-bit and 13-bit signed constants. */ | |
1001 #define SPARC_SIMM5_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x10 < 0x20) | |
0 | 1002 #define SPARC_SIMM10_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x200 < 0x400) |
1003 #define SPARC_SIMM11_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x400 < 0x800) | |
1004 #define SPARC_SIMM13_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x1000 < 0x2000) | |
1005 | |
1006 /* 10- and 11-bit immediates are only used for a few specific insns. | |
1007 SMALL_INT is used throughout the port so we continue to use it. */ | |
1008 #define SMALL_INT(X) (SPARC_SIMM13_P (INTVAL (X))) | |
1009 | |
1010 /* Predicate for constants that can be loaded with a sethi instruction. | |
1011 This is the general, 64-bit aware, bitwise version that ensures that | |
1012 only constants whose representation fits in the mask | |
1013 | |
1014 0x00000000fffffc00 | |
1015 | |
1016 are accepted. It will reject, for example, negative SImode constants | |
1017 on 64-bit hosts, so correct handling is to mask the value beforehand | |
1018 according to the mode of the instruction. */ | |
1019 #define SPARC_SETHI_P(X) \ | |
1020 (((unsigned HOST_WIDE_INT) (X) \ | |
1021 & ((unsigned HOST_WIDE_INT) 0x3ff - GET_MODE_MASK (SImode) - 1)) == 0) | |
1022 | |
1023 /* Version of the above predicate for SImode constants and below. */ | |
1024 #define SPARC_SETHI32_P(X) \ | |
1025 (SPARC_SETHI_P ((unsigned HOST_WIDE_INT) (X) & GET_MODE_MASK (SImode))) | |
1026 | |
1027 /* Return the maximum number of consecutive registers | |
1028 needed to represent mode MODE in a register of class CLASS. */ | |
1029 /* On SPARC, this is the size of MODE in words. */ | |
1030 #define CLASS_MAX_NREGS(CLASS, MODE) \ | |
1031 (FP_REG_CLASS_P (CLASS) ? (GET_MODE_SIZE (MODE) + 3) / 4 \ | |
1032 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) | |
1033 | |
1034 /* Stack layout; function entry, exit and calling. */ | |
1035 | |
1036 /* Define this if pushing a word on the stack | |
1037 makes the stack pointer a smaller address. */ | |
111 | 1038 #define STACK_GROWS_DOWNWARD 1 |
0 | 1039 |
1040 /* Define this to nonzero if the nominal address of the stack frame | |
1041 is at the high-address end of the local variables; | |
1042 that is, each additional local variable allocated | |
1043 goes at a more negative offset in the frame. */ | |
1044 #define FRAME_GROWS_DOWNWARD 1 | |
1045 | |
1046 /* Offset of first parameter from the argument pointer register value. | |
1047 !v9: This is 64 for the ins and locals, plus 4 for the struct-return reg | |
1048 even if this function isn't going to use it. | |
1049 v9: This is 128 for the ins and locals. */ | |
1050 #define FIRST_PARM_OFFSET(FNDECL) \ | |
1051 (TARGET_ARCH64 ? 16 * UNITS_PER_WORD : STRUCT_VALUE_OFFSET + UNITS_PER_WORD) | |
1052 | |
1053 /* Offset from the argument pointer register value to the CFA. | |
1054 This is different from FIRST_PARM_OFFSET because the register window | |
1055 comes between the CFA and the arguments. */ | |
1056 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0 | |
1057 | |
1058 /* When a parameter is passed in a register, stack space is still | |
1059 allocated for it. | |
1060 !v9: All 6 possible integer registers have backing store allocated. | |
1061 v9: Only space for the arguments passed is allocated. */ | |
1062 /* ??? Ideally, we'd use zero here (as the minimum), but zero has special | |
1063 meaning to the backend. Further, we need to be able to detect if a | |
1064 varargs/unprototyped function is called, as they may want to spill more | |
1065 registers than we've provided space. Ugly, ugly. So for now we retain | |
1066 all 6 slots even for v9. */ | |
1067 #define REG_PARM_STACK_SPACE(DECL) (6 * UNITS_PER_WORD) | |
1068 | |
1069 /* Definitions for register elimination. */ | |
1070 | |
1071 #define ELIMINABLE_REGS \ | |
1072 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
1073 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM} } | |
1074 | |
111 | 1075 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ |
1076 do \ | |
1077 { \ | |
1078 (OFFSET) = sparc_initial_elimination_offset ((TO)); \ | |
1079 } \ | |
1080 while (0) | |
0 | 1081 |
1082 /* Keep the stack pointer constant throughout the function. | |
1083 This is both an optimization and a necessity: longjmp | |
1084 doesn't behave itself when the stack pointer moves within | |
1085 the function! */ | |
1086 #define ACCUMULATE_OUTGOING_ARGS 1 | |
1087 | |
1088 /* Define this macro if the target machine has "register windows". This | |
1089 C expression returns the register number as seen by the called function | |
1090 corresponding to register number OUT as seen by the calling function. | |
1091 Return OUT if register number OUT is not an outbound register. */ | |
1092 | |
1093 #define INCOMING_REGNO(OUT) \ | |
111 | 1094 ((TARGET_FLAT || (OUT) < 8 || (OUT) > 15) ? (OUT) : (OUT) + 16) |
0 | 1095 |
1096 /* Define this macro if the target machine has "register windows". This | |
1097 C expression returns the register number as seen by the calling function | |
1098 corresponding to register number IN as seen by the called function. | |
1099 Return IN if register number IN is not an inbound register. */ | |
1100 | |
1101 #define OUTGOING_REGNO(IN) \ | |
111 | 1102 ((TARGET_FLAT || (IN) < 24 || (IN) > 31) ? (IN) : (IN) - 16) |
0 | 1103 |
1104 /* Define this macro if the target machine has register windows. This | |
1105 C expression returns true if the register is call-saved but is in the | |
1106 register window. */ | |
1107 | |
1108 #define LOCAL_REGNO(REGNO) \ | |
111 | 1109 (!TARGET_FLAT && (REGNO) >= 16 && (REGNO) <= 31) |
0 | 1110 |
1111 /* Define the size of space to allocate for the return value of an | |
1112 untyped_call. */ | |
1113 | |
1114 #define APPLY_RESULT_SIZE (TARGET_ARCH64 ? 24 : 16) | |
1115 | |
1116 /* 1 if N is a possible register number for function argument passing. | |
1117 On SPARC, these are the "output" registers. v9 also uses %f0-%f31. */ | |
1118 | |
1119 #define FUNCTION_ARG_REGNO_P(N) \ | |
111 | 1120 (((N) >= 8 && (N) <= 13) \ |
1121 || (TARGET_ARCH64 && TARGET_FPU && (N) >= 32 && (N) <= 63)) | |
0 | 1122 |
1123 /* Define a data type for recording info about an argument list | |
1124 during the scan of that argument list. This data type should | |
1125 hold all necessary information about the function itself | |
1126 and about the args processed so far, enough to enable macros | |
1127 such as FUNCTION_ARG to determine where the next arg should go. | |
1128 | |
1129 On SPARC (!v9), this is a single integer, which is a number of words | |
1130 of arguments scanned so far (including the invisible argument, | |
1131 if any, which holds the structure-value-address). | |
1132 Thus 7 or more means all following args should go on the stack. | |
1133 | |
1134 For v9, we also need to know whether a prototype is present. */ | |
1135 | |
1136 struct sparc_args { | |
1137 int words; /* number of words passed so far */ | |
1138 int prototype_p; /* nonzero if a prototype is present */ | |
1139 int libcall_p; /* nonzero if a library call */ | |
1140 }; | |
1141 #define CUMULATIVE_ARGS struct sparc_args | |
1142 | |
1143 /* Initialize a variable CUM of type CUMULATIVE_ARGS | |
1144 for a call to a function whose data type is FNTYPE. | |
1145 For a library call, FNTYPE is 0. */ | |
1146 | |
1147 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ | |
1148 init_cumulative_args (& (CUM), (FNTYPE), (LIBNAME), (FNDECL)); | |
1149 | |
1150 | |
1151 /* Generate the special assembly code needed to tell the assembler whatever | |
1152 it might need to know about the return value of a function. | |
1153 | |
1154 For SPARC assemblers, we need to output a .proc pseudo-op which conveys | |
1155 information to the assembler relating to peephole optimization (done in | |
1156 the assembler). */ | |
1157 | |
1158 #define ASM_DECLARE_RESULT(FILE, RESULT) \ | |
1159 fprintf ((FILE), "\t.proc\t0%lo\n", sparc_type_code (TREE_TYPE (RESULT))) | |
1160 | |
1161 /* Output the special assembly code needed to tell the assembler some | |
1162 register is used as global register variable. | |
1163 | |
1164 SPARC 64bit psABI declares registers %g2 and %g3 as application | |
1165 registers and %g6 and %g7 as OS registers. Any object using them | |
1166 should declare (for %g2/%g3 has to, for %g6/%g7 can) that it uses them | |
1167 and how they are used (scratch or some global variable). | |
1168 Linker will then refuse to link together objects which use those | |
1169 registers incompatibly. | |
1170 | |
1171 Unless the registers are used for scratch, two different global | |
1172 registers cannot be declared to the same name, so in the unlikely | |
1173 case of a global register variable occupying more than one register | |
1174 we prefix the second and following registers with .gnu.part1. etc. */ | |
1175 | |
1176 extern GTY(()) char sparc_hard_reg_printed[8]; | |
1177 | |
1178 #ifdef HAVE_AS_REGISTER_PSEUDO_OP | |
1179 #define ASM_DECLARE_REGISTER_GLOBAL(FILE, DECL, REGNO, NAME) \ | |
1180 do { \ | |
1181 if (TARGET_ARCH64) \ | |
1182 { \ | |
111 | 1183 int end = end_hard_regno (DECL_MODE (decl), REGNO); \ |
0 | 1184 int reg; \ |
1185 for (reg = (REGNO); reg < 8 && reg < end; reg++) \ | |
1186 if ((reg & ~1) == 2 || (reg & ~1) == 6) \ | |
1187 { \ | |
1188 if (reg == (REGNO)) \ | |
1189 fprintf ((FILE), "\t.register\t%%g%d, %s\n", reg, (NAME)); \ | |
1190 else \ | |
1191 fprintf ((FILE), "\t.register\t%%g%d, .gnu.part%d.%s\n", \ | |
1192 reg, reg - (REGNO), (NAME)); \ | |
1193 sparc_hard_reg_printed[reg] = 1; \ | |
1194 } \ | |
1195 } \ | |
1196 } while (0) | |
1197 #endif | |
1198 | |
1199 | |
1200 /* Emit rtl for profiling. */ | |
1201 #define PROFILE_HOOK(LABEL) sparc_profile_hook (LABEL) | |
1202 | |
1203 /* All the work done in PROFILE_HOOK, but still required. */ | |
1204 #define FUNCTION_PROFILER(FILE, LABELNO) do { } while (0) | |
1205 | |
1206 /* Set the name of the mcount function for the system. */ | |
1207 #define MCOUNT_FUNCTION "*mcount" | |
1208 | |
1209 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, | |
1210 the stack pointer does not matter. The value is tested only in | |
111 | 1211 functions that have frame pointers. */ |
1212 #define EXIT_IGNORE_STACK 1 | |
0 | 1213 |
1214 /* Length in units of the trampoline for entering a nested function. */ | |
1215 #define TRAMPOLINE_SIZE (TARGET_ARCH64 ? 32 : 16) | |
1216 | |
111 | 1217 /* Alignment required for trampolines, in bits. */ |
1218 #define TRAMPOLINE_ALIGNMENT 128 | |
0 | 1219 |
1220 /* Generate RTL to flush the register windows so as to make arbitrary frames | |
1221 available. */ | |
111 | 1222 #define SETUP_FRAME_ADDRESSES() \ |
1223 do { \ | |
1224 if (!TARGET_FLAT) \ | |
1225 emit_insn (gen_flush_register_windows ());\ | |
1226 } while (0) | |
0 | 1227 |
1228 /* Given an rtx for the address of a frame, | |
1229 return an rtx for the address of the word in the frame | |
1230 that holds the dynamic chain--the previous frame's address. */ | |
1231 #define DYNAMIC_CHAIN_ADDRESS(frame) \ | |
111 | 1232 plus_constant (Pmode, frame, 14 * UNITS_PER_WORD + SPARC_STACK_BIAS) |
0 | 1233 |
1234 /* Given an rtx for the frame pointer, | |
1235 return an rtx for the address of the frame. */ | |
111 | 1236 #define FRAME_ADDR_RTX(frame) plus_constant (Pmode, frame, SPARC_STACK_BIAS) |
0 | 1237 |
1238 /* The return address isn't on the stack, it is in a register, so we can't | |
1239 access it from the current frame pointer. We can access it from the | |
1240 previous frame pointer though by reading a value from the register window | |
1241 save area. */ | |
111 | 1242 #define RETURN_ADDR_IN_PREVIOUS_FRAME 1 |
0 | 1243 |
1244 /* This is the offset of the return address to the true next instruction to be | |
1245 executed for the current function. */ | |
1246 #define RETURN_ADDR_OFFSET \ | |
1247 (8 + 4 * (! TARGET_ARCH64 && cfun->returns_struct)) | |
1248 | |
1249 /* The current return address is in %i7. The return address of anything | |
1250 farther back is in the register window save area at [%fp+60]. */ | |
1251 /* ??? This ignores the fact that the actual return address is +8 for normal | |
1252 returns, and +12 for structure returns. */ | |
111 | 1253 #define RETURN_ADDR_REGNUM 31 |
0 | 1254 #define RETURN_ADDR_RTX(count, frame) \ |
1255 ((count == -1) \ | |
111 | 1256 ? gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM) \ |
0 | 1257 : gen_rtx_MEM (Pmode, \ |
111 | 1258 memory_address (Pmode, plus_constant (Pmode, frame, \ |
0 | 1259 15 * UNITS_PER_WORD \ |
1260 + SPARC_STACK_BIAS)))) | |
1261 | |
1262 /* Before the prologue, the return address is %o7 + 8. OK, sometimes it's | |
1263 +12, but always using +8 is close enough for frame unwind purposes. | |
1264 Actually, just using %o7 is close enough for unwinding, but %o7+8 | |
1265 is something you can return to. */ | |
111 | 1266 #define INCOMING_RETURN_ADDR_REGNUM 15 |
0 | 1267 #define INCOMING_RETURN_ADDR_RTX \ |
111 | 1268 plus_constant (word_mode, \ |
1269 gen_rtx_REG (word_mode, INCOMING_RETURN_ADDR_REGNUM), 8) | |
1270 #define DWARF_FRAME_RETURN_COLUMN \ | |
1271 DWARF_FRAME_REGNUM (INCOMING_RETURN_ADDR_REGNUM) | |
0 | 1272 |
1273 /* The offset from the incoming value of %sp to the top of the stack frame | |
1274 for the current function. On sparc64, we have to account for the stack | |
1275 bias if present. */ | |
1276 #define INCOMING_FRAME_SP_OFFSET SPARC_STACK_BIAS | |
1277 | |
1278 /* Describe how we implement __builtin_eh_return. */ | |
111 | 1279 #define EH_RETURN_REGNUM 1 |
0 | 1280 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 24 : INVALID_REGNUM) |
111 | 1281 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, EH_RETURN_REGNUM) |
1282 | |
1283 /* Define registers used by the epilogue and return instruction. */ | |
1284 #define EPILOGUE_USES(REGNO) \ | |
1285 ((REGNO) == RETURN_ADDR_REGNUM \ | |
1286 || (TARGET_FLAT \ | |
1287 && epilogue_completed \ | |
1288 && (REGNO) == INCOMING_RETURN_ADDR_REGNUM) \ | |
1289 || (crtl->calls_eh_return && (REGNO) == EH_RETURN_REGNUM)) | |
0 | 1290 |
1291 /* Select a format to encode pointers in exception handling data. CODE | |
1292 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is | |
1293 true if the symbol may be affected by dynamic relocations. | |
1294 | |
1295 If assembler and linker properly support .uaword %r_disp32(foo), | |
1296 then use PC relative 32-bit relocations instead of absolute relocs | |
1297 for shared libraries. On sparc64, use pc relative 32-bit relocs even | |
1298 for binaries, to save memory. | |
1299 | |
1300 binutils 2.12 would emit a R_SPARC_DISP32 dynamic relocation if the | |
1301 symbol %r_disp32() is against was not local, but .hidden. In that | |
1302 case, we have to use DW_EH_PE_absptr for pic personality. */ | |
1303 #ifdef HAVE_AS_SPARC_UA_PCREL | |
1304 #ifdef HAVE_AS_SPARC_UA_PCREL_HIDDEN | |
1305 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \ | |
1306 (flag_pic \ | |
1307 ? (GLOBAL ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4\ | |
1308 : ((TARGET_ARCH64 && ! GLOBAL) \ | |
1309 ? (DW_EH_PE_pcrel | DW_EH_PE_sdata4) \ | |
1310 : DW_EH_PE_absptr)) | |
1311 #else | |
1312 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \ | |
1313 (flag_pic \ | |
1314 ? (GLOBAL ? DW_EH_PE_absptr : (DW_EH_PE_pcrel | DW_EH_PE_sdata4)) \ | |
1315 : ((TARGET_ARCH64 && ! GLOBAL) \ | |
1316 ? (DW_EH_PE_pcrel | DW_EH_PE_sdata4) \ | |
1317 : DW_EH_PE_absptr)) | |
1318 #endif | |
1319 | |
1320 /* Emit a PC-relative relocation. */ | |
1321 #define ASM_OUTPUT_DWARF_PCREL(FILE, SIZE, LABEL) \ | |
1322 do { \ | |
1323 fputs (integer_asm_op (SIZE, FALSE), FILE); \ | |
1324 fprintf (FILE, "%%r_disp%d(", SIZE * 8); \ | |
1325 assemble_name (FILE, LABEL); \ | |
1326 fputc (')', FILE); \ | |
1327 } while (0) | |
1328 #endif | |
1329 | |
1330 /* Addressing modes, and classification of registers for them. */ | |
1331 | |
1332 /* Macros to check register numbers against specific register classes. */ | |
1333 | |
1334 /* These assume that REGNO is a hard or pseudo reg number. | |
1335 They give nonzero only if REGNO is a hard reg of the suitable class | |
1336 or a pseudo reg currently allocated to a suitable hard reg. | |
1337 Since they use reg_renumber, they are safe only once reg_renumber | |
111 | 1338 has been allocated, which happens in reginfo.c during register |
1339 allocation. */ | |
0 | 1340 |
1341 #define REGNO_OK_FOR_INDEX_P(REGNO) \ | |
111 | 1342 (SPARC_INT_REG_P (REGNO) || SPARC_INT_REG_P (reg_renumber[REGNO]) \ |
1343 || (REGNO) == FRAME_POINTER_REGNUM \ | |
0 | 1344 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM) |
1345 | |
1346 #define REGNO_OK_FOR_BASE_P(REGNO) REGNO_OK_FOR_INDEX_P (REGNO) | |
1347 | |
1348 #define REGNO_OK_FOR_FP_P(REGNO) \ | |
1349 (((unsigned) (REGNO) - 32 < (TARGET_V9 ? (unsigned)64 : (unsigned)32)) \ | |
1350 || ((unsigned) reg_renumber[REGNO] - 32 < (TARGET_V9 ? (unsigned)64 : (unsigned)32))) | |
111 | 1351 |
0 | 1352 #define REGNO_OK_FOR_CCFP_P(REGNO) \ |
1353 (TARGET_V9 \ | |
1354 && (((unsigned) (REGNO) - 96 < (unsigned)4) \ | |
1355 || ((unsigned) reg_renumber[REGNO] - 96 < (unsigned)4))) | |
1356 | |
1357 /* Maximum number of registers that can appear in a valid memory address. */ | |
1358 | |
1359 #define MAX_REGS_PER_ADDRESS 2 | |
1360 | |
1361 /* Recognize any constant value that is a valid address. | |
1362 When PIC, we do not accept an address that would require a scratch reg | |
1363 to load into a register. */ | |
1364 | |
1365 #define CONSTANT_ADDRESS_P(X) constant_address_p (X) | |
1366 | |
1367 /* Define this, so that when PIC, reload won't try to reload invalid | |
1368 addresses which require two reload registers. */ | |
1369 | |
1370 #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X) | |
1371 | |
1372 /* Should gcc use [%reg+%lo(xx)+offset] addresses? */ | |
1373 | |
1374 #ifdef HAVE_AS_OFFSETABLE_LO10 | |
1375 #define USE_AS_OFFSETABLE_LO10 1 | |
1376 #else | |
1377 #define USE_AS_OFFSETABLE_LO10 0 | |
1378 #endif | |
1379 | |
1380 /* Try a machine-dependent way of reloading an illegitimate address | |
1381 operand. If we find one, push the reload and jump to WIN. This | |
67
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1382 macro is used in only one place: `find_reloads_address' in reload.c. */ |
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1383 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \ |
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1384 do { \ |
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1385 int win; \ |
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1386 (X) = sparc_legitimize_reload_address ((X), (MODE), (OPNUM), \ |
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1387 (int)(TYPE), (IND_LEVELS), &win); \ |
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1388 if (win) \ |
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1389 goto WIN; \ |
0 | 1390 } while (0) |
1391 | |
1392 /* Specify the machine mode that this machine uses | |
1393 for the index in the tablejump instruction. */ | |
1394 /* If we ever implement any of the full models (such as CM_FULLANY), | |
1395 this has to be DImode in that case */ | |
1396 #ifdef HAVE_GAS_SUBSECTION_ORDERING | |
1397 #define CASE_VECTOR_MODE \ | |
1398 (! TARGET_PTR64 ? SImode : flag_pic ? SImode : TARGET_CM_MEDLOW ? SImode : DImode) | |
1399 #else | |
1400 /* If assembler does not have working .subsection -1, we use DImode for pic, as otherwise | |
1401 we have to sign extend which slows things down. */ | |
1402 #define CASE_VECTOR_MODE \ | |
1403 (! TARGET_PTR64 ? SImode : flag_pic ? DImode : TARGET_CM_MEDLOW ? SImode : DImode) | |
1404 #endif | |
1405 | |
1406 /* Define this as 1 if `char' should by default be signed; else as 0. */ | |
1407 #define DEFAULT_SIGNED_CHAR 1 | |
1408 | |
1409 /* Max number of bytes we can move from memory to memory | |
1410 in one reasonably fast instruction. */ | |
1411 #define MOVE_MAX 8 | |
1412 | |
1413 /* If a memory-to-memory move would take MOVE_RATIO or more simple | |
1414 move-instruction pairs, we will do a movmem or libcall instead. */ | |
1415 | |
1416 #define MOVE_RATIO(speed) ((speed) ? 8 : 3) | |
1417 | |
1418 /* Define if operations between registers always perform the operation | |
1419 on the full register even if a narrower mode is specified. */ | |
111 | 1420 #define WORD_REGISTER_OPERATIONS 1 |
0 | 1421 |
1422 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD | |
1423 will either zero-extend or sign-extend. The value of this macro should | |
1424 be the code that says which one of the two operations is implicitly | |
1425 done, UNKNOWN if none. */ | |
1426 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND | |
1427 | |
1428 /* Nonzero if access to memory by bytes is slow and undesirable. | |
1429 For RISC chips, it means that access to memory by bytes is no | |
1430 better than access by words when possible, so grab a whole word | |
1431 and maybe make use of that. */ | |
1432 #define SLOW_BYTE_ACCESS 1 | |
1433 | |
1434 /* Define this to be nonzero if shift instructions ignore all but the low-order | |
1435 few bits. */ | |
1436 #define SHIFT_COUNT_TRUNCATED 1 | |
1437 | |
111 | 1438 /* For SImode, we make sure the top 32-bits of the register are clear and |
1439 then we subtract 32 from the lzd instruction result. */ | |
1440 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ | |
1441 ((VALUE) = ((MODE) == SImode ? 32 : 64), 1) | |
0 | 1442 |
1443 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, | |
1444 return the mode to be used for the comparison. For floating-point, | |
111 | 1445 CCFP[E]mode is used. CCNZmode should be used when the first operand |
0 | 1446 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special |
1447 processing is needed. */ | |
1448 #define SELECT_CC_MODE(OP,X,Y) select_cc_mode ((OP), (X), (Y)) | |
1449 | |
1450 /* Return nonzero if MODE implies a floating point inequality can be | |
1451 reversed. For SPARC this is always true because we have a full | |
1452 compliment of ordered and unordered comparisons, but until generic | |
1453 code knows how to reverse it correctly we keep the old definition. */ | |
1454 #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode && (MODE) != CCFPmode) | |
1455 | |
1456 /* A function address in a call instruction for indexing purposes. */ | |
1457 #define FUNCTION_MODE Pmode | |
1458 | |
1459 /* Define this if addresses of constant functions | |
1460 shouldn't be put through pseudo regs where they can be cse'd. | |
1461 Desirable on machines where ordinary constants are expensive | |
1462 but a CALL with constant address is cheap. */ | |
111 | 1463 #define NO_FUNCTION_CSE 1 |
0 | 1464 |
1465 /* The _Q_* comparison libcalls return booleans. */ | |
1466 #define FLOAT_LIB_COMPARE_RETURNS_BOOL(MODE, COMPARISON) ((MODE) == TFmode) | |
1467 | |
1468 /* Assume by default that the _Qp_* 64-bit libcalls are implemented such | |
1469 that the inputs are fully consumed before the output memory is clobbered. */ | |
1470 | |
1471 #define TARGET_BUGGY_QP_LIB 0 | |
1472 | |
1473 /* Assume by default that we do not have the Solaris-specific conversion | |
1474 routines nor 64-bit integer multiply and divide routines. */ | |
1475 | |
1476 #define SUN_CONVERSION_LIBFUNCS 0 | |
1477 #define DITF_CONVERSION_LIBFUNCS 0 | |
1478 #define SUN_INTEGER_MULTIPLY_64 0 | |
1479 | |
1480 /* Provide the cost of a branch. For pre-v9 processors we use | |
1481 a value of 3 to take into account the potential annulling of | |
1482 the delay slot (which ends up being a bubble in the pipeline slot) | |
1483 plus a cycle to take into consideration the instruction cache | |
1484 effects. | |
1485 | |
1486 On v9 and later, which have branch prediction facilities, we set | |
1487 it to the depth of the pipeline as that is the cost of a | |
1488 mispredicted branch. | |
1489 | |
1490 On Niagara, normal branches insert 3 bubbles into the pipe | |
1491 and annulled branches insert 4 bubbles. | |
1492 | |
111 | 1493 On Niagara-2 and Niagara-3, a not-taken branch costs 1 cycle whereas |
1494 a taken branch costs 6 cycles. | |
1495 | |
1496 The T4 Supplement specifies the branch latency at 2 cycles. | |
1497 The M7 Supplement specifies the branch latency at 1 cycle. */ | |
0 | 1498 |
1499 #define BRANCH_COST(speed_p, predictable_p) \ | |
1500 ((sparc_cpu == PROCESSOR_V9 \ | |
1501 || sparc_cpu == PROCESSOR_ULTRASPARC) \ | |
1502 ? 7 \ | |
1503 : (sparc_cpu == PROCESSOR_ULTRASPARC3 \ | |
1504 ? 9 \ | |
1505 : (sparc_cpu == PROCESSOR_NIAGARA \ | |
1506 ? 4 \ | |
111 | 1507 : ((sparc_cpu == PROCESSOR_NIAGARA2 \ |
1508 || sparc_cpu == PROCESSOR_NIAGARA3) \ | |
0 | 1509 ? 5 \ |
111 | 1510 : (sparc_cpu == PROCESSOR_NIAGARA4 \ |
1511 ? 2 \ | |
1512 : (sparc_cpu == PROCESSOR_NIAGARA7 \ | |
1513 ? 1 \ | |
1514 : 3)))))) | |
0 | 1515 |
1516 /* Control the assembler format that we output. */ | |
1517 | |
1518 /* A C string constant describing how to begin a comment in the target | |
1519 assembler language. The compiler assumes that the comment will end at | |
1520 the end of the line. */ | |
1521 | |
1522 #define ASM_COMMENT_START "!" | |
1523 | |
1524 /* Output to assembler file text saying following lines | |
1525 may contain character constants, extra white space, comments, etc. */ | |
1526 | |
1527 #define ASM_APP_ON "" | |
1528 | |
1529 /* Output to assembler file text saying following lines | |
1530 no longer contain unusual constructs. */ | |
1531 | |
1532 #define ASM_APP_OFF "" | |
1533 | |
1534 /* How to refer to registers in assembler output. | |
1535 This sequence is indexed by compiler's hard-register-number (see above). */ | |
1536 | |
1537 #define REGISTER_NAMES \ | |
1538 {"%g0", "%g1", "%g2", "%g3", "%g4", "%g5", "%g6", "%g7", \ | |
1539 "%o0", "%o1", "%o2", "%o3", "%o4", "%o5", "%sp", "%o7", \ | |
1540 "%l0", "%l1", "%l2", "%l3", "%l4", "%l5", "%l6", "%l7", \ | |
1541 "%i0", "%i1", "%i2", "%i3", "%i4", "%i5", "%fp", "%i7", \ | |
1542 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7", \ | |
1543 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15", \ | |
1544 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23", \ | |
1545 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31", \ | |
1546 "%f32", "%f33", "%f34", "%f35", "%f36", "%f37", "%f38", "%f39", \ | |
1547 "%f40", "%f41", "%f42", "%f43", "%f44", "%f45", "%f46", "%f47", \ | |
1548 "%f48", "%f49", "%f50", "%f51", "%f52", "%f53", "%f54", "%f55", \ | |
1549 "%f56", "%f57", "%f58", "%f59", "%f60", "%f61", "%f62", "%f63", \ | |
111 | 1550 "%fcc0", "%fcc1", "%fcc2", "%fcc3", "%icc", "%sfp", "%gsr" } |
0 | 1551 |
1552 /* Define additional names for use in asm clobbers and asm declarations. */ | |
1553 | |
1554 #define ADDITIONAL_REGISTER_NAMES \ | |
1555 {{"ccr", SPARC_ICC_REG}, {"cc", SPARC_ICC_REG}} | |
1556 | |
1557 /* On Sun 4, this limit is 2048. We use 1000 to be safe, since the length | |
1558 can run past this up to a continuation point. Once we used 1500, but | |
1559 a single entry in C++ can run more than 500 bytes, due to the length of | |
1560 mangled symbol names. dbxout.c should really be fixed to do | |
1561 continuations when they are actually needed instead of trying to | |
1562 guess... */ | |
1563 #define DBX_CONTIN_LENGTH 1000 | |
1564 | |
1565 /* This is how to output a command to make the user-level label named NAME | |
1566 defined for reference from other files. */ | |
1567 | |
1568 /* Globalizing directive for a label. */ | |
1569 #define GLOBAL_ASM_OP "\t.global " | |
1570 | |
1571 /* The prefix to add to user-visible assembler symbols. */ | |
1572 | |
1573 #define USER_LABEL_PREFIX "_" | |
1574 | |
1575 /* This is how to store into the string LABEL | |
1576 the symbol_ref name of an internal numbered label where | |
1577 PREFIX is the class of label and NUM is the number within the class. | |
1578 This is suitable for output with `assemble_name'. */ | |
1579 | |
1580 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ | |
1581 sprintf ((LABEL), "*%s%ld", (PREFIX), (long)(NUM)) | |
1582 | |
1583 /* This is how we hook in and defer the case-vector until the end of | |
1584 the function. */ | |
1585 #define ASM_OUTPUT_ADDR_VEC(LAB,VEC) \ | |
1586 sparc_defer_case_vector ((LAB),(VEC), 0) | |
1587 | |
1588 #define ASM_OUTPUT_ADDR_DIFF_VEC(LAB,VEC) \ | |
1589 sparc_defer_case_vector ((LAB),(VEC), 1) | |
1590 | |
1591 /* This is how to output an element of a case-vector that is absolute. */ | |
1592 | |
1593 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ | |
1594 do { \ | |
1595 char label[30]; \ | |
1596 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \ | |
1597 if (CASE_VECTOR_MODE == SImode) \ | |
1598 fprintf (FILE, "\t.word\t"); \ | |
1599 else \ | |
1600 fprintf (FILE, "\t.xword\t"); \ | |
1601 assemble_name (FILE, label); \ | |
1602 fputc ('\n', FILE); \ | |
1603 } while (0) | |
1604 | |
1605 /* This is how to output an element of a case-vector that is relative. | |
1606 (SPARC uses such vectors only when generating PIC.) */ | |
1607 | |
1608 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ | |
1609 do { \ | |
1610 char label[30]; \ | |
1611 ASM_GENERATE_INTERNAL_LABEL (label, "L", (VALUE)); \ | |
1612 if (CASE_VECTOR_MODE == SImode) \ | |
1613 fprintf (FILE, "\t.word\t"); \ | |
1614 else \ | |
1615 fprintf (FILE, "\t.xword\t"); \ | |
1616 assemble_name (FILE, label); \ | |
1617 ASM_GENERATE_INTERNAL_LABEL (label, "L", (REL)); \ | |
1618 fputc ('-', FILE); \ | |
1619 assemble_name (FILE, label); \ | |
1620 fputc ('\n', FILE); \ | |
1621 } while (0) | |
1622 | |
1623 /* This is what to output before and after case-vector (both | |
1624 relative and absolute). If .subsection -1 works, we put case-vectors | |
1625 at the beginning of the current section. */ | |
1626 | |
1627 #ifdef HAVE_GAS_SUBSECTION_ORDERING | |
1628 | |
1629 #define ASM_OUTPUT_ADDR_VEC_START(FILE) \ | |
1630 fprintf(FILE, "\t.subsection\t-1\n") | |
1631 | |
1632 #define ASM_OUTPUT_ADDR_VEC_END(FILE) \ | |
1633 fprintf(FILE, "\t.previous\n") | |
1634 | |
1635 #endif | |
1636 | |
1637 /* This is how to output an assembler line | |
1638 that says to advance the location counter | |
1639 to a multiple of 2**LOG bytes. */ | |
1640 | |
1641 #define ASM_OUTPUT_ALIGN(FILE,LOG) \ | |
1642 if ((LOG) != 0) \ | |
1643 fprintf (FILE, "\t.align %d\n", (1<<(LOG))) | |
1644 | |
1645 #define ASM_OUTPUT_SKIP(FILE,SIZE) \ | |
111 | 1646 fprintf (FILE, "\t.skip " HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE)) |
0 | 1647 |
1648 /* This says how to output an assembler line | |
1649 to define a global common symbol. */ | |
1650 | |
1651 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ | |
1652 ( fputs ("\t.common ", (FILE)), \ | |
1653 assemble_name ((FILE), (NAME)), \ | |
111 | 1654 fprintf ((FILE), "," HOST_WIDE_INT_PRINT_UNSIGNED",\"bss\"\n", (SIZE))) |
0 | 1655 |
1656 /* This says how to output an assembler line to define a local common | |
1657 symbol. */ | |
1658 | |
1659 #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGNED) \ | |
1660 ( fputs ("\t.reserve ", (FILE)), \ | |
1661 assemble_name ((FILE), (NAME)), \ | |
111 | 1662 fprintf ((FILE), "," HOST_WIDE_INT_PRINT_UNSIGNED",\"bss\",%u\n", \ |
0 | 1663 (SIZE), ((ALIGNED) / BITS_PER_UNIT))) |
1664 | |
1665 /* A C statement (sans semicolon) to output to the stdio stream | |
1666 FILE the assembler definition of uninitialized global DECL named | |
1667 NAME whose size is SIZE bytes and alignment is ALIGN bytes. | |
1668 Try to use asm_output_aligned_bss to implement this macro. */ | |
1669 | |
1670 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \ | |
1671 do { \ | |
1672 ASM_OUTPUT_ALIGNED_LOCAL (FILE, NAME, SIZE, ALIGN); \ | |
1673 } while (0) | |
1674 | |
1675 /* Output #ident as a .ident. */ | |
1676 | |
111 | 1677 #undef TARGET_ASM_OUTPUT_IDENT |
1678 #define TARGET_ASM_OUTPUT_IDENT default_asm_output_ident_directive | |
0 | 1679 |
1680 /* Prettify the assembly. */ | |
1681 | |
1682 extern int sparc_indent_opcode; | |
1683 | |
1684 #define ASM_OUTPUT_OPCODE(FILE, PTR) \ | |
1685 do { \ | |
1686 if (sparc_indent_opcode) \ | |
1687 { \ | |
1688 putc (' ', FILE); \ | |
1689 sparc_indent_opcode = 0; \ | |
1690 } \ | |
1691 } while (0) | |
1692 | |
1693 /* TLS support defaulting to original Sun flavor. GNU extensions | |
1694 must be activated in separate configuration files. */ | |
1695 #ifdef HAVE_AS_TLS | |
1696 #define TARGET_TLS 1 | |
1697 #else | |
1698 #define TARGET_TLS 0 | |
1699 #endif | |
1700 | |
1701 #define TARGET_SUN_TLS TARGET_TLS | |
1702 #define TARGET_GNU_TLS 0 | |
1703 | |
111 | 1704 #ifdef HAVE_AS_FMAF_HPC_VIS3 |
1705 #define AS_NIAGARA3_FLAG "d" | |
1706 #else | |
1707 #define AS_NIAGARA3_FLAG "b" | |
1708 #endif | |
1709 | |
1710 #ifdef HAVE_AS_SPARC4 | |
1711 #define AS_NIAGARA4_FLAG "-xarch=sparc4" | |
1712 #else | |
1713 #define AS_NIAGARA4_FLAG "-Av9" AS_NIAGARA3_FLAG | |
1714 #endif | |
1715 | |
1716 #ifdef HAVE_AS_SPARC5_VIS4 | |
1717 #define AS_NIAGARA7_FLAG "-xarch=sparc5" | |
1718 #else | |
1719 #define AS_NIAGARA7_FLAG AS_NIAGARA4_FLAG | |
1720 #endif | |
1721 | |
1722 #ifdef HAVE_AS_SPARC6 | |
1723 #define AS_M8_FLAG "-xarch=sparc6" | |
1724 #else | |
1725 #define AS_M8_FLAG AS_NIAGARA7_FLAG | |
1726 #endif | |
1727 | |
1728 #ifdef HAVE_AS_LEON | |
1729 #define AS_LEON_FLAG "-Aleon" | |
1730 #define AS_LEONV7_FLAG "-Aleon" | |
1731 #else | |
1732 #define AS_LEON_FLAG "-Av8" | |
1733 #define AS_LEONV7_FLAG "-Av7" | |
1734 #endif | |
0 | 1735 |
1736 /* We use gcc _mcount for profiling. */ | |
1737 #define NO_PROFILE_COUNTERS 0 | |
111 | 1738 |
1739 /* Debug support */ | |
1740 #define MASK_DEBUG_OPTIONS 0x01 /* debug option handling */ | |
1741 #define MASK_DEBUG_ALL MASK_DEBUG_OPTIONS | |
1742 | |
1743 #define TARGET_DEBUG_OPTIONS (sparc_debug & MASK_DEBUG_OPTIONS) | |
1744 | |
1745 /* By default, use the weakest memory model for the cpu. */ | |
1746 #ifndef SUBTARGET_DEFAULT_MEMORY_MODEL | |
1747 #define SUBTARGET_DEFAULT_MEMORY_MODEL SMM_DEFAULT | |
1748 #endif | |
1749 | |
1750 /* Define this to 1 if the FE_EXCEPT values defined in fenv.h start at 1. */ | |
1751 #define SPARC_LOW_FE_EXCEPT_VALUES 0 | |
1752 | |
1753 #define TARGET_SUPPORTS_WIDE_INT 1 |