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1 ;; GCC machine description for Tilera TILE-Gx synchronization
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2 ;; instructions.
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3 ;; Copyright (C) 2011-2017 Free Software Foundation, Inc.
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4 ;; Contributed by Walter Lee (walt@tilera.com)
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5 ;;
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6 ;; This file is part of GCC.
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7 ;;
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8 ;; GCC is free software; you can redistribute it and/or modify it
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9 ;; under the terms of the GNU General Public License as published
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10 ;; by the Free Software Foundation; either version 3, or (at your
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11 ;; option) any later version.
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12 ;;
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13 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
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14 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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15 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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16 ;; License for more details.
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17 ;;
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18 ;; You should have received a copy of the GNU General Public License
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19 ;; along with GCC; see the file COPYING3. If not see
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20 ;; <http://www.gnu.org/licenses/>.
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21
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22 (define_code_iterator fetchop [plus ior and])
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23 (define_code_attr fetchop_name [(plus "add") (ior "or") (and "and")])
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24
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25 (define_insn "mtspr_cmpexch<mode>"
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26 [(set (reg:I48MODE TILEGX_CMPEXCH_REG)
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27 (unspec_volatile:I48MODE
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28 [(match_operand:I48MODE 0 "reg_or_0_operand" "rO")]
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29 UNSPEC_SPR_MOVE))]
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30 ""
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31 "mtspr\tCMPEXCH_VALUE, %r0"
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32 [(set_attr "type" "X1")])
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33
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34
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35 (define_expand "atomic_compare_and_swap<mode>"
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36 [(match_operand:DI 0 "register_operand" "") ;; bool output
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37 (match_operand:I48MODE 1 "register_operand" "") ;; val output
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38 (match_operand:I48MODE 2 "nonautoincmem_operand" "") ;; memory
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39 (match_operand:I48MODE 3 "reg_or_0_operand" "") ;; expected value
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40 (match_operand:I48MODE 4 "reg_or_0_operand" "") ;; desired value
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41 (match_operand:SI 5 "const_int_operand" "") ;; is_weak
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42 (match_operand:SI 6 "const_int_operand" "") ;; mod_s
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43 (match_operand:SI 7 "const_int_operand" "")] ;; mod_f
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44 ""
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45 {
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46 enum memmodel mod_s = (enum memmodel) INTVAL (operands[6]);
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47
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48 if (operands[3] != const0_rtx)
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49 operands[3] = force_reg (<MODE>mode, operands[3]);
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50 if (operands[4] != const0_rtx)
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51 operands[4] = force_reg (<MODE>mode, operands[4]);
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52
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53 tilegx_pre_atomic_barrier (mod_s);
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54 emit_insn (gen_mtspr_cmpexch<mode> (operands[3]));
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55 emit_insn (gen_atomic_compare_and_swap_bare<mode> (operands[1], operands[2],
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56 operands[4]));
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57 tilegx_post_atomic_barrier (mod_s);
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58 emit_insn (gen_insn_cmpeq_<mode>di (operands[0], operands[1], operands[3]));
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59 DONE;
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60 })
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61
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62
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63 (define_insn "atomic_compare_and_swap_bare<mode>"
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64 [(set (match_operand:I48MODE 0 "register_operand" "=r")
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65 (match_operand:I48MODE 1 "nonautoincmem_operand" "+U"))
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66 (set (match_dup 1)
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67 (unspec_volatile:I48MODE
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68 [(match_dup 1)
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69 (reg:I48MODE TILEGX_CMPEXCH_REG)
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70 (match_operand:I48MODE 2 "reg_or_0_operand" "rO")]
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71 UNSPEC_CMPXCHG))]
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72 ""
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73 "cmpexch<four_if_si>\t%0, %1, %r2"
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74 [(set_attr "type" "X1_remote")])
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75
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76
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77 (define_expand "atomic_exchange<mode>"
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78 [(match_operand:I48MODE 0 "register_operand" "") ;; result
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79 (match_operand:I48MODE 1 "nonautoincmem_operand" "") ;; memory
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80 (match_operand:I48MODE 2 "reg_or_0_operand" "") ;; input
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81 (match_operand:SI 3 "const_int_operand" "")] ;; model
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82 ""
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83 {
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84 enum memmodel model = (enum memmodel) INTVAL (operands[3]);
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85
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86 tilegx_pre_atomic_barrier (model);
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87 emit_insn (gen_atomic_exchange_bare<mode> (operands[0], operands[1],
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88 operands[2]));
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89 tilegx_post_atomic_barrier (model);
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90 DONE;
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91 })
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92
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93
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94 (define_insn "atomic_exchange_bare<mode>"
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95 [(set (match_operand:I48MODE 0 "register_operand" "=r")
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96 (match_operand:I48MODE 1 "nonautoincmem_operand" "+U"))
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97 (set (match_dup 1)
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98 (unspec_volatile:I48MODE
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99 [(match_operand:I48MODE 2 "reg_or_0_operand" "rO")]
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100 UNSPEC_XCHG))]
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101 ""
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102 "exch<four_if_si>\t%0, %1, %r2"
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103 [(set_attr "type" "X1_remote")])
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104
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105
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106 (define_expand "atomic_fetch_<fetchop_name><mode>"
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107 [(match_operand:I48MODE 0 "register_operand" "") ;; result
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108 (match_operand:I48MODE 1 "nonautoincmem_operand" "") ;; memory
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109 (unspec_volatile:I48MODE
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110 [(fetchop:I48MODE
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111 (match_dup 1)
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112 (match_operand:I48MODE 2 "reg_or_0_operand" ""))] ;; value
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113 UNSPEC_ATOMIC)
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114 (match_operand:SI 3 "const_int_operand" "")] ;; model
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115 ""
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116 {
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117 enum memmodel model = (enum memmodel) INTVAL (operands[3]);
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118
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119 tilegx_pre_atomic_barrier (model);
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120 emit_insn (gen_atomic_fetch_<fetchop_name>_bare<mode> (operands[0],
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121 operands[1],
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122 operands[2]));
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123 tilegx_post_atomic_barrier (model);
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124 DONE;
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125 })
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126
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127
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128 (define_insn "atomic_fetch_<fetchop_name>_bare<mode>"
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129 [(set (match_operand:I48MODE 0 "register_operand" "=r")
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130 (match_operand:I48MODE 1 "nonautoincmem_operand" "+U"))
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131 (set (match_dup 1)
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132 (unspec_volatile:I48MODE
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133 [(fetchop:I48MODE
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134 (match_dup 1)
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135 (match_operand:I48MODE 2 "reg_or_0_operand" "rO"))]
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136 UNSPEC_ATOMIC))]
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137 ""
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138 "fetch<fetchop_name><four_if_si>\t%0, %1, %r2"
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139 [(set_attr "type" "X1_remote")])
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140
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141
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142 (define_expand "atomic_fetch_sub<mode>"
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143 [(match_operand:I48MODE 0 "register_operand" "") ;; result
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144 (match_operand:I48MODE 1 "nonautoincmem_operand" "") ;; memory
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145 (unspec_volatile:I48MODE
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146 [(minus:I48MODE
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147 (match_dup 1)
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148 (match_operand:I48MODE 2 "reg_or_0_operand" ""))] ;; value
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149 UNSPEC_ATOMIC)
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150 (match_operand:SI 3 "const_int_operand" "")] ;; model
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151 ""
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152 {
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153 rtx addend;
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154 enum memmodel model = (enum memmodel) INTVAL (operands[3]);
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155
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156 if (operands[2] != const0_rtx)
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157 {
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158 addend = gen_reg_rtx (<MODE>mode);
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159 emit_move_insn (addend,
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160 gen_rtx_MINUS (<MODE>mode, const0_rtx, operands[2]));
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161 }
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162 else
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163 addend = operands[2];
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164
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165 tilegx_pre_atomic_barrier (model);
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166 emit_insn (gen_atomic_fetch_add_bare<mode> (operands[0],
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167 operands[1],
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168 addend));
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169 tilegx_post_atomic_barrier (model);
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170 DONE;
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171 })
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172
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173
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174 (define_expand "atomic_test_and_set"
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175 [(match_operand:QI 0 "register_operand" "") ;; bool output
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176 (match_operand:QI 1 "nonautoincmem_operand" "+U") ;; memory
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177 (match_operand:SI 2 "const_int_operand" "")] ;; model
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178 ""
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179 {
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180 rtx addr, aligned_addr, aligned_mem, offset, word, shmt, tmp;
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181 rtx result = operands[0];
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182 rtx mem = operands[1];
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183 enum memmodel model = (enum memmodel) INTVAL (operands[2]);
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184
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185 addr = force_reg (Pmode, XEXP (mem, 0));
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186
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187 aligned_addr = gen_reg_rtx (Pmode);
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188 emit_move_insn (aligned_addr, gen_rtx_AND (Pmode, addr, GEN_INT (-8)));
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189
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190 aligned_mem = change_address (mem, DImode, aligned_addr);
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191 set_mem_alias_set (aligned_mem, 0);
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192
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193 tmp = gen_reg_rtx (Pmode);
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194 if (BYTES_BIG_ENDIAN)
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195 {
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196 emit_move_insn (gen_lowpart (DImode, tmp),
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197 gen_rtx_NOT (DImode, gen_lowpart (DImode, addr)));
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198 }
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199 else
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200 {
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201 tmp = addr;
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202 }
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203
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204 offset = gen_reg_rtx (DImode);
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205 emit_move_insn (offset, gen_rtx_AND (DImode, gen_lowpart (DImode, tmp),
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206 GEN_INT (7)));
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207
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208 tmp = gen_reg_rtx (DImode);
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209 emit_move_insn (tmp, GEN_INT (1));
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210
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211 shmt = gen_reg_rtx (DImode);
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212 emit_move_insn (shmt, gen_rtx_ASHIFT (DImode, offset, GEN_INT (3)));
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213
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214 word = gen_reg_rtx (DImode);
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215 emit_move_insn (word, gen_rtx_ASHIFT (DImode, tmp,
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216 gen_lowpart (SImode, shmt)));
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217
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218 tmp = gen_reg_rtx (DImode);
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219 tilegx_pre_atomic_barrier (model);
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220 emit_insn (gen_atomic_fetch_or_baredi (tmp, aligned_mem, word));
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221 tilegx_post_atomic_barrier (model);
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222
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223 emit_move_insn (gen_lowpart (DImode, result),
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224 gen_rtx_LSHIFTRT (DImode, tmp,
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225 gen_lowpart (SImode, shmt)));
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226 DONE;
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227 })
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