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111
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1 /* IR-agnostic target query functions relating to optabs
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2 Copyright (C) 1987-2017 Free Software Foundation, Inc.
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3
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4 This file is part of GCC.
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5
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6 GCC is free software; you can redistribute it and/or modify it under
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7 the terms of the GNU General Public License as published by the Free
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8 Software Foundation; either version 3, or (at your option) any later
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9 version.
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10
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11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
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12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
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13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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14 for more details.
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15
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16 You should have received a copy of the GNU General Public License
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17 along with GCC; see the file COPYING3. If not see
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18 <http://www.gnu.org/licenses/>. */
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19
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20
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21 #include "config.h"
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22 #include "system.h"
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23 #include "coretypes.h"
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24 #include "target.h"
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25 #include "insn-codes.h"
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26 #include "optabs-query.h"
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27 #include "optabs-libfuncs.h"
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28 #include "insn-config.h"
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29 #include "rtl.h"
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30 #include "recog.h"
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31
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32 struct target_optabs default_target_optabs;
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33 struct target_optabs *this_fn_optabs = &default_target_optabs;
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34 #if SWITCHABLE_TARGET
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35 struct target_optabs *this_target_optabs = &default_target_optabs;
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36 #endif
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37
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38 /* Return the insn used to perform conversion OP from mode FROM_MODE
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39 to mode TO_MODE; return CODE_FOR_nothing if the target does not have
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40 such an insn, or if it is unsuitable for optimization type OPT_TYPE. */
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41
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42 insn_code
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43 convert_optab_handler (convert_optab optab, machine_mode to_mode,
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44 machine_mode from_mode, optimization_type opt_type)
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45 {
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46 insn_code icode = convert_optab_handler (optab, to_mode, from_mode);
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47 if (icode == CODE_FOR_nothing
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48 || !targetm.optab_supported_p (optab, to_mode, from_mode, opt_type))
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49 return CODE_FOR_nothing;
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50 return icode;
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51 }
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52
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53 /* Return the insn used to implement mode MODE of OP; return
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54 CODE_FOR_nothing if the target does not have such an insn,
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55 or if it is unsuitable for optimization type OPT_TYPE. */
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56
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57 insn_code
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58 direct_optab_handler (convert_optab optab, machine_mode mode,
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59 optimization_type opt_type)
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60 {
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61 insn_code icode = direct_optab_handler (optab, mode);
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62 if (icode == CODE_FOR_nothing
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63 || !targetm.optab_supported_p (optab, mode, mode, opt_type))
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64 return CODE_FOR_nothing;
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65 return icode;
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66 }
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67
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68 /* Enumerates the possible types of structure operand to an
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69 extraction_insn. */
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70 enum extraction_type { ET_unaligned_mem, ET_reg };
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71
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72 /* Check whether insv, extv or extzv pattern ICODE can be used for an
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73 insertion or extraction of type TYPE on a structure of mode MODE.
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74 Return true if so and fill in *INSN accordingly. STRUCT_OP is the
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75 operand number of the structure (the first sign_extract or zero_extract
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76 operand) and FIELD_OP is the operand number of the field (the other
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77 side of the set from the sign_extract or zero_extract). */
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78
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79 static bool
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80 get_traditional_extraction_insn (extraction_insn *insn,
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81 enum extraction_type type,
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82 machine_mode mode,
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83 enum insn_code icode,
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84 int struct_op, int field_op)
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85 {
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86 const struct insn_data_d *data = &insn_data[icode];
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87
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88 machine_mode struct_mode = data->operand[struct_op].mode;
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89 if (struct_mode == VOIDmode)
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90 struct_mode = word_mode;
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91 if (mode != struct_mode)
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92 return false;
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93
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94 machine_mode field_mode = data->operand[field_op].mode;
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95 if (field_mode == VOIDmode)
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96 field_mode = word_mode;
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97
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98 machine_mode pos_mode = data->operand[struct_op + 2].mode;
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99 if (pos_mode == VOIDmode)
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100 pos_mode = word_mode;
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101
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102 insn->icode = icode;
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103 insn->field_mode = as_a <scalar_int_mode> (field_mode);
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104 if (type == ET_unaligned_mem)
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105 insn->struct_mode = byte_mode;
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106 else if (struct_mode == BLKmode)
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107 insn->struct_mode = opt_scalar_int_mode ();
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108 else
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109 insn->struct_mode = as_a <scalar_int_mode> (struct_mode);
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110 insn->pos_mode = as_a <scalar_int_mode> (pos_mode);
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111 return true;
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112 }
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113
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114 /* Return true if an optab exists to perform an insertion or extraction
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115 of type TYPE in mode MODE. Describe the instruction in *INSN if so.
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116
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117 REG_OPTAB is the optab to use for register structures and
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118 MISALIGN_OPTAB is the optab to use for misaligned memory structures.
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119 POS_OP is the operand number of the bit position. */
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120
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121 static bool
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122 get_optab_extraction_insn (struct extraction_insn *insn,
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123 enum extraction_type type,
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124 machine_mode mode, direct_optab reg_optab,
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125 direct_optab misalign_optab, int pos_op)
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126 {
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127 direct_optab optab = (type == ET_unaligned_mem ? misalign_optab : reg_optab);
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128 enum insn_code icode = direct_optab_handler (optab, mode);
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129 if (icode == CODE_FOR_nothing)
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130 return false;
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131
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132 const struct insn_data_d *data = &insn_data[icode];
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133
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134 machine_mode pos_mode = data->operand[pos_op].mode;
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135 if (pos_mode == VOIDmode)
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136 pos_mode = word_mode;
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137
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138 insn->icode = icode;
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139 insn->field_mode = as_a <scalar_int_mode> (mode);
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140 if (type == ET_unaligned_mem)
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141 insn->struct_mode = opt_scalar_int_mode ();
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142 else
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143 insn->struct_mode = insn->field_mode;
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144 insn->pos_mode = as_a <scalar_int_mode> (pos_mode);
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145 return true;
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146 }
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147
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148 /* Return true if an instruction exists to perform an insertion or
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149 extraction (PATTERN says which) of type TYPE in mode MODE.
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150 Describe the instruction in *INSN if so. */
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151
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152 static bool
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153 get_extraction_insn (extraction_insn *insn,
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154 enum extraction_pattern pattern,
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155 enum extraction_type type,
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156 machine_mode mode)
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157 {
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158 switch (pattern)
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159 {
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160 case EP_insv:
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161 if (targetm.have_insv ()
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162 && get_traditional_extraction_insn (insn, type, mode,
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163 targetm.code_for_insv, 0, 3))
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164 return true;
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165 return get_optab_extraction_insn (insn, type, mode, insv_optab,
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166 insvmisalign_optab, 2);
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167
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168 case EP_extv:
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169 if (targetm.have_extv ()
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170 && get_traditional_extraction_insn (insn, type, mode,
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171 targetm.code_for_extv, 1, 0))
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172 return true;
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173 return get_optab_extraction_insn (insn, type, mode, extv_optab,
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174 extvmisalign_optab, 3);
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175
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176 case EP_extzv:
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177 if (targetm.have_extzv ()
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178 && get_traditional_extraction_insn (insn, type, mode,
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179 targetm.code_for_extzv, 1, 0))
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180 return true;
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181 return get_optab_extraction_insn (insn, type, mode, extzv_optab,
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182 extzvmisalign_optab, 3);
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183
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184 default:
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185 gcc_unreachable ();
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186 }
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187 }
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188
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189 /* Return true if an instruction exists to access a field of mode
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190 FIELDMODE in a structure that has STRUCT_BITS significant bits.
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191 Describe the "best" such instruction in *INSN if so. PATTERN and
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192 TYPE describe the type of insertion or extraction we want to perform.
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193
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194 For an insertion, the number of significant structure bits includes
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195 all bits of the target. For an extraction, it need only include the
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196 most significant bit of the field. Larger widths are acceptable
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197 in both cases. */
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198
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199 static bool
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200 get_best_extraction_insn (extraction_insn *insn,
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201 enum extraction_pattern pattern,
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202 enum extraction_type type,
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203 unsigned HOST_WIDE_INT struct_bits,
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204 machine_mode field_mode)
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205 {
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206 opt_scalar_int_mode mode_iter;
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207 FOR_EACH_MODE_FROM (mode_iter, smallest_int_mode_for_size (struct_bits))
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208 {
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209 scalar_int_mode mode = mode_iter.require ();
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210 if (get_extraction_insn (insn, pattern, type, mode))
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211 {
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212 FOR_EACH_MODE_FROM (mode_iter, mode)
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213 {
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214 mode = mode_iter.require ();
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215 if (GET_MODE_SIZE (mode) > GET_MODE_SIZE (field_mode)
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216 || TRULY_NOOP_TRUNCATION_MODES_P (insn->field_mode,
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217 field_mode))
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218 break;
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219 get_extraction_insn (insn, pattern, type, mode);
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220 }
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221 return true;
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222 }
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223 }
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224 return false;
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225 }
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226
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227 /* Return true if an instruction exists to access a field of mode
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228 FIELDMODE in a register structure that has STRUCT_BITS significant bits.
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229 Describe the "best" such instruction in *INSN if so. PATTERN describes
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230 the type of insertion or extraction we want to perform.
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231
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232 For an insertion, the number of significant structure bits includes
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233 all bits of the target. For an extraction, it need only include the
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234 most significant bit of the field. Larger widths are acceptable
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235 in both cases. */
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236
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237 bool
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238 get_best_reg_extraction_insn (extraction_insn *insn,
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239 enum extraction_pattern pattern,
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240 unsigned HOST_WIDE_INT struct_bits,
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241 machine_mode field_mode)
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242 {
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243 return get_best_extraction_insn (insn, pattern, ET_reg, struct_bits,
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244 field_mode);
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245 }
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246
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247 /* Return true if an instruction exists to access a field of BITSIZE
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248 bits starting BITNUM bits into a memory structure. Describe the
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249 "best" such instruction in *INSN if so. PATTERN describes the type
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250 of insertion or extraction we want to perform and FIELDMODE is the
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251 natural mode of the extracted field.
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252
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253 The instructions considered here only access bytes that overlap
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254 the bitfield; they do not touch any surrounding bytes. */
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255
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256 bool
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257 get_best_mem_extraction_insn (extraction_insn *insn,
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258 enum extraction_pattern pattern,
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259 HOST_WIDE_INT bitsize, HOST_WIDE_INT bitnum,
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260 machine_mode field_mode)
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261 {
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262 unsigned HOST_WIDE_INT struct_bits = (bitnum % BITS_PER_UNIT
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263 + bitsize
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264 + BITS_PER_UNIT - 1);
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265 struct_bits -= struct_bits % BITS_PER_UNIT;
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266 return get_best_extraction_insn (insn, pattern, ET_unaligned_mem,
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267 struct_bits, field_mode);
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268 }
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269
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270 /* Return the insn code used to extend FROM_MODE to TO_MODE.
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271 UNSIGNEDP specifies zero-extension instead of sign-extension. If
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272 no such operation exists, CODE_FOR_nothing will be returned. */
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273
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274 enum insn_code
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275 can_extend_p (machine_mode to_mode, machine_mode from_mode,
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276 int unsignedp)
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277 {
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278 if (unsignedp < 0 && targetm.have_ptr_extend ())
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279 return targetm.code_for_ptr_extend;
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280
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281 convert_optab tab = unsignedp ? zext_optab : sext_optab;
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282 return convert_optab_handler (tab, to_mode, from_mode);
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283 }
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284
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285 /* Return the insn code to convert fixed-point mode FIXMODE to floating-point
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286 mode FLTMODE, or CODE_FOR_nothing if no such instruction exists.
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287 UNSIGNEDP specifies whether FIXMODE is unsigned. */
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288
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289 enum insn_code
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290 can_float_p (machine_mode fltmode, machine_mode fixmode,
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291 int unsignedp)
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292 {
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293 convert_optab tab = unsignedp ? ufloat_optab : sfloat_optab;
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294 return convert_optab_handler (tab, fltmode, fixmode);
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295 }
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296
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297 /* Return the insn code to convert floating-point mode FLTMODE to fixed-point
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298 mode FIXMODE, or CODE_FOR_nothing if no such instruction exists.
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299 UNSIGNEDP specifies whether FIXMODE is unsigned.
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300
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301 On a successful return, set *TRUNCP_PTR to true if it is necessary to
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302 output an explicit FTRUNC before the instruction. */
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303
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304 enum insn_code
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305 can_fix_p (machine_mode fixmode, machine_mode fltmode,
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306 int unsignedp, bool *truncp_ptr)
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307 {
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308 convert_optab tab;
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309 enum insn_code icode;
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310
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311 tab = unsignedp ? ufixtrunc_optab : sfixtrunc_optab;
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312 icode = convert_optab_handler (tab, fixmode, fltmode);
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313 if (icode != CODE_FOR_nothing)
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314 {
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315 *truncp_ptr = false;
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316 return icode;
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317 }
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318
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319 /* FIXME: This requires a port to define both FIX and FTRUNC pattern
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320 for this to work. We need to rework the fix* and ftrunc* patterns
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321 and documentation. */
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322 tab = unsignedp ? ufix_optab : sfix_optab;
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323 icode = convert_optab_handler (tab, fixmode, fltmode);
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324 if (icode != CODE_FOR_nothing
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325 && optab_handler (ftrunc_optab, fltmode) != CODE_FOR_nothing)
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326 {
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327 *truncp_ptr = true;
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328 return icode;
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329 }
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330
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331 return CODE_FOR_nothing;
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332 }
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333
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334 /* Return nonzero if a conditional move of mode MODE is supported.
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335
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336 This function is for combine so it can tell whether an insn that looks
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337 like a conditional move is actually supported by the hardware. If we
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338 guess wrong we lose a bit on optimization, but that's it. */
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339 /* ??? sparc64 supports conditionally moving integers values based on fp
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340 comparisons, and vice versa. How do we handle them? */
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341
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342 bool
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343 can_conditionally_move_p (machine_mode mode)
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344 {
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345 return direct_optab_handler (movcc_optab, mode) != CODE_FOR_nothing;
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346 }
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347
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348 /* Return true if VEC_PERM_EXPR of arbitrary input vectors can be
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349 expanded using SIMD extensions of the CPU. SEL may be NULL, which
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350 stands for an unknown constant. Note that additional permutations
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351 representing whole-vector shifts may also be handled via the vec_shr
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352 optab, but only where the second input vector is entirely constant
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353 zeroes; this case is not dealt with here. */
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354
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355 bool
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356 can_vec_perm_p (machine_mode mode, bool variable, vec_perm_indices *sel)
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357 {
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358 machine_mode qimode;
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359
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360 /* If the target doesn't implement a vector mode for the vector type,
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361 then no operations are supported. */
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362 if (!VECTOR_MODE_P (mode))
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363 return false;
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364
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365 if (!variable)
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366 {
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367 if (direct_optab_handler (vec_perm_const_optab, mode) != CODE_FOR_nothing
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368 && (sel == NULL
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369 || targetm.vectorize.vec_perm_const_ok == NULL
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370 || targetm.vectorize.vec_perm_const_ok (mode, *sel)))
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371 return true;
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372 }
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373
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374 if (direct_optab_handler (vec_perm_optab, mode) != CODE_FOR_nothing)
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375 return true;
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376
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377 /* We allow fallback to a QI vector mode, and adjust the mask. */
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378 if (GET_MODE_INNER (mode) == QImode
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379 || !mode_for_vector (QImode, GET_MODE_SIZE (mode)).exists (&qimode)
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380 || !VECTOR_MODE_P (qimode))
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381 return false;
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382
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383 /* ??? For completeness, we ought to check the QImode version of
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384 vec_perm_const_optab. But all users of this implicit lowering
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385 feature implement the variable vec_perm_optab. */
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386 if (direct_optab_handler (vec_perm_optab, qimode) == CODE_FOR_nothing)
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387 return false;
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388
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389 /* In order to support the lowering of variable permutations,
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390 we need to support shifts and adds. */
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391 if (variable)
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392 {
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393 if (GET_MODE_UNIT_SIZE (mode) > 2
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394 && optab_handler (ashl_optab, mode) == CODE_FOR_nothing
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395 && optab_handler (vashl_optab, mode) == CODE_FOR_nothing)
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396 return false;
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397 if (optab_handler (add_optab, qimode) == CODE_FOR_nothing)
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398 return false;
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399 }
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400
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401 return true;
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402 }
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403
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404 /* Like optab_handler, but for widening_operations that have a
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405 TO_MODE and a FROM_MODE. */
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406
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407 enum insn_code
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408 widening_optab_handler (optab op, machine_mode to_mode,
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409 machine_mode from_mode)
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410 {
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411 unsigned scode = (op << 16) | to_mode;
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412 if (to_mode != from_mode && from_mode != VOIDmode)
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413 {
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414 /* ??? Why does find_widening_optab_handler_and_mode attempt to
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415 widen things that can't be widened? E.g. add_optab... */
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416 if (op > LAST_CONV_OPTAB)
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417 return CODE_FOR_nothing;
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418 scode |= from_mode << 8;
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419 }
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420 return raw_optab_handler (scode);
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421 }
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422
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423 /* Find a widening optab even if it doesn't widen as much as we want.
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424 E.g. if from_mode is HImode, and to_mode is DImode, and there is no
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425 direct HI->SI insn, then return SI->DI, if that exists.
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426 If PERMIT_NON_WIDENING is non-zero then this can be used with
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427 non-widening optabs also. */
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428
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429 enum insn_code
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430 find_widening_optab_handler_and_mode (optab op, machine_mode to_mode,
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431 machine_mode from_mode,
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432 int permit_non_widening,
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433 machine_mode *found_mode)
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434 {
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435 for (; (permit_non_widening || from_mode != to_mode)
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436 && GET_MODE_SIZE (from_mode) <= GET_MODE_SIZE (to_mode)
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437 && from_mode != VOIDmode;
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438 from_mode = GET_MODE_WIDER_MODE (from_mode).else_void ())
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439 {
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440 enum insn_code handler = widening_optab_handler (op, to_mode,
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441 from_mode);
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442
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443 if (handler != CODE_FOR_nothing)
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444 {
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445 if (found_mode)
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446 *found_mode = from_mode;
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447 return handler;
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|
448 }
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449 }
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450
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451 return CODE_FOR_nothing;
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|
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452 }
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453
|
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|
454 /* Return non-zero if a highpart multiply is supported of can be synthisized.
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455 For the benefit of expand_mult_highpart, the return value is 1 for direct,
|
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456 2 for even/odd widening, and 3 for hi/lo widening. */
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|
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457
|
|
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458 int
|
|
|
459 can_mult_highpart_p (machine_mode mode, bool uns_p)
|
|
|
460 {
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|
|
461 optab op;
|
|
|
462 unsigned i, nunits;
|
|
|
463
|
|
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464 op = uns_p ? umul_highpart_optab : smul_highpart_optab;
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|
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465 if (optab_handler (op, mode) != CODE_FOR_nothing)
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|
|
466 return 1;
|
|
|
467
|
|
|
468 /* If the mode is an integral vector, synth from widening operations. */
|
|
|
469 if (GET_MODE_CLASS (mode) != MODE_VECTOR_INT)
|
|
|
470 return 0;
|
|
|
471
|
|
|
472 nunits = GET_MODE_NUNITS (mode);
|
|
|
473
|
|
|
474 op = uns_p ? vec_widen_umult_even_optab : vec_widen_smult_even_optab;
|
|
|
475 if (optab_handler (op, mode) != CODE_FOR_nothing)
|
|
|
476 {
|
|
|
477 op = uns_p ? vec_widen_umult_odd_optab : vec_widen_smult_odd_optab;
|
|
|
478 if (optab_handler (op, mode) != CODE_FOR_nothing)
|
|
|
479 {
|
|
|
480 auto_vec_perm_indices sel (nunits);
|
|
|
481 for (i = 0; i < nunits; ++i)
|
|
|
482 sel.quick_push (!BYTES_BIG_ENDIAN
|
|
|
483 + (i & ~1)
|
|
|
484 + ((i & 1) ? nunits : 0));
|
|
|
485 if (can_vec_perm_p (mode, false, &sel))
|
|
|
486 return 2;
|
|
|
487 }
|
|
|
488 }
|
|
|
489
|
|
|
490 op = uns_p ? vec_widen_umult_hi_optab : vec_widen_smult_hi_optab;
|
|
|
491 if (optab_handler (op, mode) != CODE_FOR_nothing)
|
|
|
492 {
|
|
|
493 op = uns_p ? vec_widen_umult_lo_optab : vec_widen_smult_lo_optab;
|
|
|
494 if (optab_handler (op, mode) != CODE_FOR_nothing)
|
|
|
495 {
|
|
|
496 auto_vec_perm_indices sel (nunits);
|
|
|
497 for (i = 0; i < nunits; ++i)
|
|
|
498 sel.quick_push (2 * i + (BYTES_BIG_ENDIAN ? 0 : 1));
|
|
|
499 if (can_vec_perm_p (mode, false, &sel))
|
|
|
500 return 3;
|
|
|
501 }
|
|
|
502 }
|
|
|
503
|
|
|
504 return 0;
|
|
|
505 }
|
|
|
506
|
|
|
507 /* Return true if target supports vector masked load/store for mode. */
|
|
|
508
|
|
|
509 bool
|
|
|
510 can_vec_mask_load_store_p (machine_mode mode,
|
|
|
511 machine_mode mask_mode,
|
|
|
512 bool is_load)
|
|
|
513 {
|
|
|
514 optab op = is_load ? maskload_optab : maskstore_optab;
|
|
|
515 machine_mode vmode;
|
|
|
516 unsigned int vector_sizes;
|
|
|
517
|
|
|
518 /* If mode is vector mode, check it directly. */
|
|
|
519 if (VECTOR_MODE_P (mode))
|
|
|
520 return convert_optab_handler (op, mode, mask_mode) != CODE_FOR_nothing;
|
|
|
521
|
|
|
522 /* Otherwise, return true if there is some vector mode with
|
|
|
523 the mask load/store supported. */
|
|
|
524
|
|
|
525 /* See if there is any chance the mask load or store might be
|
|
|
526 vectorized. If not, punt. */
|
|
|
527 scalar_mode smode;
|
|
|
528 if (!is_a <scalar_mode> (mode, &smode))
|
|
|
529 return false;
|
|
|
530
|
|
|
531 vmode = targetm.vectorize.preferred_simd_mode (smode);
|
|
|
532 if (!VECTOR_MODE_P (vmode))
|
|
|
533 return false;
|
|
|
534
|
|
|
535 if ((targetm.vectorize.get_mask_mode
|
|
|
536 (GET_MODE_NUNITS (vmode), GET_MODE_SIZE (vmode)).exists (&mask_mode))
|
|
|
537 && convert_optab_handler (op, vmode, mask_mode) != CODE_FOR_nothing)
|
|
|
538 return true;
|
|
|
539
|
|
|
540 vector_sizes = targetm.vectorize.autovectorize_vector_sizes ();
|
|
|
541 while (vector_sizes != 0)
|
|
|
542 {
|
|
|
543 unsigned int cur = 1 << floor_log2 (vector_sizes);
|
|
|
544 vector_sizes &= ~cur;
|
|
|
545 if (cur <= GET_MODE_SIZE (smode))
|
|
|
546 continue;
|
|
|
547 unsigned int nunits = cur / GET_MODE_SIZE (smode);
|
|
|
548 if (mode_for_vector (smode, nunits).exists (&vmode)
|
|
|
549 && VECTOR_MODE_P (vmode)
|
|
|
550 && targetm.vectorize.get_mask_mode (nunits, cur).exists (&mask_mode)
|
|
|
551 && convert_optab_handler (op, vmode, mask_mode) != CODE_FOR_nothing)
|
|
|
552 return true;
|
|
|
553 }
|
|
|
554 return false;
|
|
|
555 }
|
|
|
556
|
|
|
557 /* Return true if there is a compare_and_swap pattern. */
|
|
|
558
|
|
|
559 bool
|
|
|
560 can_compare_and_swap_p (machine_mode mode, bool allow_libcall)
|
|
|
561 {
|
|
|
562 enum insn_code icode;
|
|
|
563
|
|
|
564 /* Check for __atomic_compare_and_swap. */
|
|
|
565 icode = direct_optab_handler (atomic_compare_and_swap_optab, mode);
|
|
|
566 if (icode != CODE_FOR_nothing)
|
|
|
567 return true;
|
|
|
568
|
|
|
569 /* Check for __sync_compare_and_swap. */
|
|
|
570 icode = optab_handler (sync_compare_and_swap_optab, mode);
|
|
|
571 if (icode != CODE_FOR_nothing)
|
|
|
572 return true;
|
|
|
573 if (allow_libcall && optab_libfunc (sync_compare_and_swap_optab, mode))
|
|
|
574 return true;
|
|
|
575
|
|
|
576 /* No inline compare and swap. */
|
|
|
577 return false;
|
|
|
578 }
|
|
|
579
|
|
|
580 /* Return true if an atomic exchange can be performed. */
|
|
|
581
|
|
|
582 bool
|
|
|
583 can_atomic_exchange_p (machine_mode mode, bool allow_libcall)
|
|
|
584 {
|
|
|
585 enum insn_code icode;
|
|
|
586
|
|
|
587 /* Check for __atomic_exchange. */
|
|
|
588 icode = direct_optab_handler (atomic_exchange_optab, mode);
|
|
|
589 if (icode != CODE_FOR_nothing)
|
|
|
590 return true;
|
|
|
591
|
|
|
592 /* Don't check __sync_test_and_set, as on some platforms that
|
|
|
593 has reduced functionality. Targets that really do support
|
|
|
594 a proper exchange should simply be updated to the __atomics. */
|
|
|
595
|
|
|
596 return can_compare_and_swap_p (mode, allow_libcall);
|
|
|
597 }
|
|
|
598
|
|
|
599 /* Return true if an atomic load can be performed without falling back to
|
|
|
600 a compare-and-swap. */
|
|
|
601
|
|
|
602 bool
|
|
|
603 can_atomic_load_p (machine_mode mode)
|
|
|
604 {
|
|
|
605 enum insn_code icode;
|
|
|
606
|
|
|
607 /* Does the target supports the load directly? */
|
|
|
608 icode = direct_optab_handler (atomic_load_optab, mode);
|
|
|
609 if (icode != CODE_FOR_nothing)
|
|
|
610 return true;
|
|
|
611
|
|
|
612 /* If the size of the object is greater than word size on this target,
|
|
|
613 then we assume that a load will not be atomic. Also see
|
|
|
614 expand_atomic_load. */
|
|
|
615 return GET_MODE_PRECISION (mode) <= BITS_PER_WORD;
|
|
|
616 }
|
|
|
617
|
|
|
618 /* Determine whether "1 << x" is relatively cheap in word_mode. */
|
|
|
619
|
|
|
620 bool
|
|
|
621 lshift_cheap_p (bool speed_p)
|
|
|
622 {
|
|
|
623 /* FIXME: This should be made target dependent via this "this_target"
|
|
|
624 mechanism, similar to e.g. can_copy_init_p in gcse.c. */
|
|
|
625 static bool init[2] = { false, false };
|
|
|
626 static bool cheap[2] = { true, true };
|
|
|
627
|
|
|
628 /* If the targer has no lshift in word_mode, the operation will most
|
|
|
629 probably not be cheap. ??? Does GCC even work for such targets? */
|
|
|
630 if (optab_handler (ashl_optab, word_mode) == CODE_FOR_nothing)
|
|
|
631 return false;
|
|
|
632
|
|
|
633 if (!init[speed_p])
|
|
|
634 {
|
|
|
635 rtx reg = gen_raw_REG (word_mode, 10000);
|
|
|
636 int cost = set_src_cost (gen_rtx_ASHIFT (word_mode, const1_rtx, reg),
|
|
|
637 word_mode, speed_p);
|
|
|
638 cheap[speed_p] = cost < COSTS_N_INSNS (3);
|
|
|
639 init[speed_p] = true;
|
|
|
640 }
|
|
|
641
|
|
|
642 return cheap[speed_p];
|
|
|
643 }
|
