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111
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1 /* PR debug/44832 */
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2 /* { dg-do compile } */
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3 /* { dg-options "-O2 -fcompare-debug" } */
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4 /* { dg-options "-O2 -fcompare-debug -fno-short-enums" {target short_enums} } */
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5 /* { dg-require-effective-target int32plus } */
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6
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7 struct rtx_def;
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8 typedef struct rtx_def *rtx;
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9 typedef const struct rtx_def *const_rtx;
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10 struct rtvec_def;
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11 typedef struct rtvec_def *rtvec;
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12 extern int ix86_isa_flags;
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13
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14 enum machine_mode
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15 {
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16 VOIDmode,
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17 V8HImode,
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18 V16QImode,
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19 V4SImode,
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20 V2DImode,
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21 V32QImode,
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22 MAX_MACHINE_MODE,
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23
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24 NUM_MACHINE_MODES = MAX_MACHINE_MODE
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25 };
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26 extern unsigned char mode_size[NUM_MACHINE_MODES];
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27 extern const unsigned char mode_inner[NUM_MACHINE_MODES];
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28 extern const unsigned char mode_nunits[NUM_MACHINE_MODES];
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29 enum rtx_code {
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30
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31 CONST_INT ,
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32
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33 CONST_FIXED ,
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34
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35 CONST_DOUBLE
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36
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37 };
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38 union rtunion_def
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39 {
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40 rtvec rt_rtvec;
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41 };
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42 typedef union rtunion_def rtunion;
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43 struct rtx_def {
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44
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45 __extension__ enum rtx_code code: 16;
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46
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47 __extension__ enum machine_mode mode : 8;
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48
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49 union u {
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50 rtunion fld[1];
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51 } u;
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52 };
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53 struct rtvec_def {
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54 rtx elem[1];
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55 };
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56 extern int rtx_equal_p (const_rtx, const_rtx);
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57 extern rtx gen_reg_rtx (enum machine_mode);
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58
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59 extern void
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60 ix86_expand_vector_init_concat (enum machine_mode mode,
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61 rtx target, rtx *ops, int n);
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62
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63 static void
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64 ix86_expand_vector_init_general (unsigned char mmx_ok, enum machine_mode mode,
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65 rtx target, rtx vals)
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66 {
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67 rtx ops[32], op0, op1;
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68 enum machine_mode half_mode = VOIDmode;
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69 int n, i;
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70
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71 switch (mode)
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72 {
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73 case V4SImode:
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74 case V2DImode:
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75 n = mode_nunits[mode];
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76 ix86_expand_vector_init_concat (mode, target, ops, n);
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77 return;
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78
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79 case V32QImode:
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80 goto half;
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81 half:
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82 {
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83 typedef int eger;
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84 if (mode != V4SImode)
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85 ops[0] = 0;
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86 }
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87 n = mode_nunits[mode];
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88 for (i = 0; i < n; i++)
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89 ops[i] = (((((vals)->u.fld[0]).rt_rtvec))->elem[i]);
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90 op0 = gen_reg_rtx (VOIDmode);
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91 return;
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92
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93 case V16QImode:
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94 if (!((ix86_isa_flags & (1 << 19)) != 0))
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95 break;
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96
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97 case V8HImode:
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98 if (!((ix86_isa_flags & (1 << 17)) != 0))
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99 break;
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100
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101 n = mode_nunits[mode];
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102 for (i = 0; i < n; i++)
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103 ops[i] = (((((vals)->u.fld[0]).rt_rtvec))->elem[i]);
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104 return;
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105
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106 default:
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107 ;
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108 }
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109
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110 {
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111 int n_words;
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112
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113 n_words = ((unsigned short) mode_size[mode]) / 4;
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114
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115 if (n_words == 4)
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116 ix86_expand_vector_init_general (0, V4SImode, 0, 0);
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117 }
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118 }
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119
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120
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121 void
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122 ix86_expand_vector_init (unsigned char mmx_ok, rtx target, rtx vals)
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123 {
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124 enum machine_mode mode = ((enum machine_mode) (target)->mode);
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125 enum machine_mode inner_mode = ((enum machine_mode) mode_inner[mode]);
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126 int n_elts = mode_nunits[mode];
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127 int n_var = 0, one_var = -1;
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128 unsigned char all_same = 1, all_const_zero = 1;
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129 int i;
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130 rtx x;
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131
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132 for (i = 0; i < n_elts; ++i)
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133 {
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134 x = (((((vals)->u.fld[0]).rt_rtvec))->elem[i]);
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135 if (!((((enum rtx_code) (x)->code) == CONST_INT)
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136 || ((enum rtx_code) (x)->code) == CONST_DOUBLE
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137 || ((enum rtx_code) (x)->code) == CONST_FIXED))
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138 n_var++, one_var = i;
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139 else
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140 all_const_zero = 0;
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141 if (i > 0 && !rtx_equal_p (x, (((((vals)->u.fld[0]).rt_rtvec))->elem[0])))
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142 all_same = 0;
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143 }
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144
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145
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146 if (n_var == 0)
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147 {
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148 return;
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149 }
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150
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151 if (all_same)
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152 return;
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153
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154 if (n_var == 1)
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155 {
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156 if (all_const_zero)
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157 return;
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158
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159 }
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160
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161 ix86_expand_vector_init_general (mmx_ok, mode, target, vals);
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162 }
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