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1 ;; tsv110 pipeline description
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2 ;; Copyright (C) 2018-2020 Free Software Foundation, Inc.
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3 ;;
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4 ;; This file is part of GCC.
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5 ;;
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6 ;; GCC is free software; you can redistribute it and/or modify it
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7 ;; under the terms of the GNU General Public License as published by
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8 ;; the Free Software Foundation; either version 3, or (at your option)
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9 ;; any later version.
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10 ;;
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11 ;; GCC is distributed in the hope that it will be useful, but
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12 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
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13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 ;; General Public License for more details.
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15 ;;
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16 ;; You should have received a copy of the GNU General Public License
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17 ;; along with GCC; see the file COPYING3. If not see
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18 ;; <http://www.gnu.org/licenses/>.
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19
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20 (define_automaton "tsv110")
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21
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22 (define_attr "tsv110_neon_type"
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23 "neon_arith_acc, neon_arith_acc_q,
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24 neon_arith_basic, neon_arith_complex,
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25 neon_reduc_add_acc, neon_multiply, neon_multiply_q,
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26 neon_multiply_long, neon_mla, neon_mla_q, neon_mla_long,
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27 neon_sat_mla_long, neon_shift_acc, neon_shift_imm_basic,
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28 neon_shift_imm_complex,
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29 neon_shift_reg_basic, neon_shift_reg_basic_q, neon_shift_reg_complex,
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30 neon_shift_reg_complex_q, neon_fp_negabs, neon_fp_arith,
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31 neon_fp_arith_q, neon_fp_reductions_q, neon_fp_cvt_int,
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32 neon_fp_cvt_int_q, neon_fp_cvt16, neon_fp_minmax, neon_fp_mul,
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33 neon_fp_mul_q, neon_fp_mla, neon_fp_mla_q, neon_fp_recpe_rsqrte,
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34 neon_fp_recpe_rsqrte_q, neon_fp_recps_rsqrts, neon_fp_recps_rsqrts_q,
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35 neon_bitops, neon_bitops_q, neon_from_gp,
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36 neon_from_gp_q, neon_move, neon_tbl3_tbl4, neon_zip_q, neon_to_gp,
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37 neon_load_a, neon_load_b, neon_load_c, neon_load_d, neon_load_e,
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38 neon_load_f, neon_store_a, neon_store_b, neon_store_complex,
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39 unknown"
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40 (cond [
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41 (eq_attr "type" "neon_arith_acc, neon_reduc_add_acc,\
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42 neon_reduc_add_acc_q")
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43 (const_string "neon_arith_acc")
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44 (eq_attr "type" "neon_arith_acc_q")
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45 (const_string "neon_arith_acc_q")
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46 (eq_attr "type" "neon_abs,neon_abs_q,neon_add, neon_add_q, neon_add_long,\
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47 neon_add_widen, neon_neg, neon_neg_q,\
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48 neon_reduc_add, neon_reduc_add_q,\
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49 neon_reduc_add_long, neon_sub, neon_sub_q,\
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50 neon_sub_long, neon_sub_widen, neon_logic,\
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51 neon_logic_q, neon_tst, neon_tst_q,\
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52 neon_compare, neon_compare_q,\
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53 neon_compare_zero, neon_compare_zero_q,\
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54 neon_minmax, neon_minmax_q, neon_reduc_minmax,\
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55 neon_reduc_minmax_q")
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56 (const_string "neon_arith_basic")
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57 (eq_attr "type" "neon_add_halve_narrow_q,\
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58 neon_add_halve, neon_add_halve_q,\
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59 neon_sub_halve, neon_sub_halve_q, neon_qabs,\
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60 neon_qabs_q, neon_qadd, neon_qadd_q, neon_qneg,\
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61 neon_qneg_q, neon_qsub, neon_qsub_q,\
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62 neon_sub_halve_narrow_q")
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63 (const_string "neon_arith_complex")
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64
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65 (eq_attr "type" "neon_mul_b, neon_mul_h, neon_mul_s,\
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66 neon_mul_h_scalar, neon_mul_s_scalar,\
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67 neon_sat_mul_b, neon_sat_mul_h,\
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68 neon_sat_mul_s, neon_sat_mul_h_scalar,\
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69 neon_sat_mul_s_scalar,\
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70 neon_mul_b_long, neon_mul_h_long,\
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71 neon_mul_s_long,\
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72 neon_mul_h_scalar_long, neon_mul_s_scalar_long,\
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73 neon_sat_mul_b_long, neon_sat_mul_h_long,\
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74 neon_sat_mul_s_long, neon_sat_mul_h_scalar_long,\
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75 neon_sat_mul_s_scalar_long,\
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76 neon_mla_b, neon_mla_h, neon_mla_s,\
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77 neon_mla_h_scalar, neon_mla_s_scalar,\
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78 neon_mla_b_long, neon_mla_h_long,\
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79 neon_mla_s_long,\
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80 neon_mla_h_scalar_long, neon_mla_s_scalar_long,\
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81 neon_sat_mla_b_long, neon_sat_mla_h_long,\
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82 neon_sat_mla_s_long, neon_sat_mla_h_scalar_long,\
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83 neon_sat_mla_s_scalar_long")
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84 (const_string "neon_multiply")
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85 (eq_attr "type" "neon_mul_b_q, neon_mul_h_q, neon_mul_s_q,\
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86 neon_mul_h_scalar_q, neon_mul_s_scalar_q,\
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87 neon_sat_mul_b_q, neon_sat_mul_h_q,\
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88 neon_sat_mul_s_q, neon_sat_mul_h_scalar_q,\
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89 neon_sat_mul_s_scalar_q,\
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90 neon_mla_b_q, neon_mla_h_q, neon_mla_s_q,\
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91 neon_mla_h_scalar_q, neon_mla_s_scalar_q")
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92 (const_string "neon_multiply_q")
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93
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94 (eq_attr "type" "neon_shift_acc, neon_shift_acc_q")
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95 (const_string "neon_shift_acc")
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96 (eq_attr "type" "neon_shift_imm, neon_shift_imm_q,\
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97 neon_shift_imm_narrow_q, neon_shift_imm_long")
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98 (const_string "neon_shift_imm_basic")
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99 (eq_attr "type" "neon_sat_shift_imm, neon_sat_shift_imm_q,\
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100 neon_sat_shift_imm_narrow_q")
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101 (const_string "neon_shift_imm_complex")
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102 (eq_attr "type" "neon_shift_reg")
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103 (const_string "neon_shift_reg_basic")
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104 (eq_attr "type" "neon_shift_reg_q")
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105 (const_string "neon_shift_reg_basic_q")
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106 (eq_attr "type" "neon_sat_shift_reg")
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107 (const_string "neon_shift_reg_complex")
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108 (eq_attr "type" "neon_sat_shift_reg_q")
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109 (const_string "neon_shift_reg_complex_q")
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110
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111 (eq_attr "type" "neon_fp_neg_s, neon_fp_neg_s_q,\
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112 neon_fp_abs_s, neon_fp_abs_s_q,\
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113 neon_fp_neg_d, neon_fp_neg_d_q,\
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114 neon_fp_abs_d, neon_fp_abs_d_q,\
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115 neon_fp_minmax_s,neon_fp_minmax_d,\
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116 neon_fp_reduc_minmax_s,neon_fp_reduc_minmax_d")
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117 (const_string "neon_fp_negabs")
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118 (eq_attr "type" "neon_fp_addsub_s, neon_fp_abd_s,\
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119 neon_fp_reduc_add_s, neon_fp_compare_s,\
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120 neon_fp_round_s,\
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121 neon_fp_addsub_d, neon_fp_abd_d,\
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122 neon_fp_reduc_add_d, neon_fp_compare_d,\
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123 neon_fp_round_d")
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124 (const_string "neon_fp_arith")
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125 (eq_attr "type" "neon_fp_addsub_s_q, neon_fp_abd_s_q,\
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126 neon_fp_reduc_add_s_q, neon_fp_compare_s_q,\
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127 neon_fp_minmax_s_q, neon_fp_round_s_q,\
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128 neon_fp_addsub_d_q, neon_fp_abd_d_q,\
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129 neon_fp_reduc_add_d_q, neon_fp_compare_d_q,\
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130 neon_fp_minmax_d_q, neon_fp_round_d_q")
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131 (const_string "neon_fp_arith_q")
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132 (eq_attr "type" "neon_fp_reduc_minmax_s_q,\
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133 neon_fp_reduc_minmax_d_q,\
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134 neon_fp_reduc_add_s_q, neon_fp_reduc_add_d_q")
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135 (const_string "neon_fp_reductions_q")
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136 (eq_attr "type" "neon_fp_to_int_s, neon_int_to_fp_s,\
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137 neon_fp_to_int_d, neon_int_to_fp_d")
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138 (const_string "neon_fp_cvt_int")
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139 (eq_attr "type" "neon_fp_to_int_s_q, neon_int_to_fp_s_q,\
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140 neon_fp_to_int_d_q, neon_int_to_fp_d_q")
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141 (const_string "neon_fp_cvt_int_q")
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142 (eq_attr "type" "neon_fp_cvt_narrow_s_q, neon_fp_cvt_widen_h")
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143 (const_string "neon_fp_cvt16")
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144 (eq_attr "type" "neon_fp_mul_s, neon_fp_mul_s_scalar,\
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145 neon_fp_mul_d")
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146 (const_string "neon_fp_mul")
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147 (eq_attr "type" "neon_fp_mul_s_q, neon_fp_mul_s_scalar_q,\
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148 neon_fp_mul_d_q, neon_fp_mul_d_scalar_q")
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149 (const_string "neon_fp_mul_q")
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150 (eq_attr "type" "neon_fp_mla_s, neon_fp_mla_s_scalar,\
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151 neon_fp_mla_d")
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152 (const_string "neon_fp_mla")
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153 (eq_attr "type" "neon_fp_mla_s_q, neon_fp_mla_s_scalar_q,
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154 neon_fp_mla_d_q, neon_fp_mla_d_scalar_q")
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155 (const_string "neon_fp_mla_q")
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156 (eq_attr "type" "neon_fp_recpe_s, neon_fp_rsqrte_s,\
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157 neon_fp_recpx_s,\
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158 neon_fp_recpe_d, neon_fp_rsqrte_d,\
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159 neon_fp_recpx_d")
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160 (const_string "neon_fp_recpe_rsqrte")
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161 (eq_attr "type" "neon_fp_recpe_s_q, neon_fp_rsqrte_s_q,\
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162 neon_fp_recpx_s_q,\
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163 neon_fp_recpe_d_q, neon_fp_rsqrte_d_q,\
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164 neon_fp_recpx_d_q")
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165 (const_string "neon_fp_recpe_rsqrte_q")
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166 (eq_attr "type" "neon_fp_recps_s, neon_fp_rsqrts_s,\
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167 neon_fp_recps_d, neon_fp_rsqrts_d")
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168 (const_string "neon_fp_recps_rsqrts")
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169 (eq_attr "type" "neon_fp_recps_s_q, neon_fp_rsqrts_s_q,\
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170 neon_fp_recps_d_q, neon_fp_rsqrts_d_q")
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171 (const_string "neon_fp_recps_rsqrts_q")
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172 (eq_attr "type" "neon_bsl, neon_cls, neon_cnt,\
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173 neon_rev, neon_permute, neon_rbit,\
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174 neon_tbl1, neon_tbl2, neon_zip,\
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175 neon_dup, neon_dup_q, neon_ext, neon_ext_q,\
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176 neon_move, neon_move_q, neon_move_narrow_q")
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177 (const_string "neon_bitops")
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178 (eq_attr "type" "neon_bsl_q, neon_cls_q, neon_cnt_q,\
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179 neon_rev_q, neon_permute_q, neon_rbit_q")
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180 (const_string "neon_bitops_q")
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181 (eq_attr "type" "neon_from_gp,f_mcr,f_mcrr")
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182 (const_string "neon_from_gp")
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183 (eq_attr "type" "neon_from_gp_q")
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184 (const_string "neon_from_gp_q")
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185
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186 (eq_attr "type" "f_loads, f_loadd,\
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187 neon_load1_1reg, neon_load1_1reg_q,\
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188 neon_load1_2reg, neon_load1_2reg_q")
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189 (const_string "neon_load_a")
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190 (eq_attr "type" "neon_load1_3reg, neon_load1_3reg_q,\
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191 neon_load1_4reg, neon_load1_4reg_q")
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192 (const_string "neon_load_b")
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193 (eq_attr "type" "neon_load1_one_lane, neon_load1_one_lane_q,\
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194 neon_load1_all_lanes, neon_load1_all_lanes_q,\
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195 neon_load2_2reg, neon_load2_2reg_q,\
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196 neon_load2_all_lanes, neon_load2_all_lanes_q")
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197 (const_string "neon_load_c")
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198 (eq_attr "type" "neon_load2_4reg, neon_load2_4reg_q,\
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199 neon_load3_3reg, neon_load3_3reg_q,\
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200 neon_load3_one_lane, neon_load3_one_lane_q,\
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201 neon_load4_4reg, neon_load4_4reg_q")
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202 (const_string "neon_load_d")
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203 (eq_attr "type" "neon_load2_one_lane, neon_load2_one_lane_q,\
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204 neon_load3_all_lanes, neon_load3_all_lanes_q,\
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205 neon_load4_all_lanes, neon_load4_all_lanes_q")
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206 (const_string "neon_load_e")
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207 (eq_attr "type" "neon_load4_one_lane, neon_load4_one_lane_q")
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208 (const_string "neon_load_f")
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209
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210 (eq_attr "type" "f_stores, f_stored,\
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211 neon_store1_1reg")
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212 (const_string "neon_store_a")
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213 (eq_attr "type" "neon_store1_2reg, neon_store1_1reg_q")
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214 (const_string "neon_store_b")
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215 (eq_attr "type" "neon_store1_3reg, neon_store1_3reg_q,\
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216 neon_store3_3reg, neon_store3_3reg_q,\
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217 neon_store2_4reg, neon_store2_4reg_q,\
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218 neon_store4_4reg, neon_store4_4reg_q,\
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219 neon_store2_2reg, neon_store2_2reg_q,\
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220 neon_store3_one_lane, neon_store3_one_lane_q,\
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221 neon_store4_one_lane, neon_store4_one_lane_q,\
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222 neon_store1_4reg, neon_store1_4reg_q,\
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223 neon_store1_one_lane, neon_store1_one_lane_q,\
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224 neon_store2_one_lane, neon_store2_one_lane_q")
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225 (const_string "neon_store_complex")]
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226 (const_string "unknown")))
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227
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228 ;; The tsv110 core is modelled as issues pipeline that has
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229 ;; the following functional units.
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230 ;; 1. Three pipelines for integer operations: ALU1, ALU2, ALU3
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231
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232 (define_cpu_unit "tsv110_alu1_issue" "tsv110")
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233 (define_reservation "tsv110_alu1" "tsv110_alu1_issue")
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234
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235 (define_cpu_unit "tsv110_alu2_issue" "tsv110")
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236 (define_reservation "tsv110_alu2" "tsv110_alu2_issue")
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237
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238 (define_cpu_unit "tsv110_alu3_issue" "tsv110")
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239 (define_reservation "tsv110_alu3" "tsv110_alu3_issue")
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240
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241 ;; 2. One pipeline for complex integer operations: MDU
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242
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243 (define_cpu_unit "tsv110_mdu_issue" "tsv110")
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244 (define_reservation "tsv110_mdu" "tsv110_mdu_issue")
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245
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246 ;; 3. Two asymmetric pipelines for Asimd and FP operations: FSU1, FSU2
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247 (define_automaton "tsv110_fsu")
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248
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249 (define_cpu_unit "tsv110_fsu1_issue"
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250 "tsv110_fsu")
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251 (define_cpu_unit "tsv110_fsu2_issue"
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252 "tsv110_fsu")
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253
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254 (define_reservation "tsv110_fsu1" "tsv110_fsu1_issue")
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255 (define_reservation "tsv110_fsu2" "tsv110_fsu2_issue")
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256
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257 ;; 4. Two pipeline for branch operations but same with alu2 and alu3: BRU1, BRU2
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258
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259 ;; 5. Two pipelines for load and store operations: LS1, LS2.
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260
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261 (define_cpu_unit "tsv110_ls1_issue" "tsv110")
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262 (define_cpu_unit "tsv110_ls2_issue" "tsv110")
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263 (define_reservation "tsv110_ls1" "tsv110_ls1_issue")
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264 (define_reservation "tsv110_ls2" "tsv110_ls2_issue")
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265
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266 ;; Block all issue queues.
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267
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268 (define_reservation "tsv110_block" "tsv110_fsu1_issue + tsv110_fsu2_issue
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269 + tsv110_mdu_issue + tsv110_alu1_issue
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270 + tsv110_alu2_issue + tsv110_alu3_issue + tsv110_ls1_issue + tsv110_ls2_issue")
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271
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272 ;; Simple Execution Unit:
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273 ;;
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274 ;; Simple ALU without shift
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275 (define_insn_reservation "tsv110_alu" 1
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276 (and (eq_attr "tune" "tsv110")
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277 (eq_attr "type" "alu_imm,logic_imm,\
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278 alu_sreg,logic_reg,\
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279 adc_imm,adc_reg,\
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280 adr,bfm,clz,rbit,rev,\
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281 shift_imm,shift_reg,\
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282 mov_imm,mov_reg,\
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283 mvn_imm,mvn_reg,\
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284 mrs,multiple"))
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285 "tsv110_alu1|tsv110_alu2|tsv110_alu3")
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286
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287 (define_insn_reservation "tsv110_alus" 1
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288 (and (eq_attr "tune" "tsv110")
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289 (eq_attr "type" "alus_imm,logics_imm,\
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290 alus_sreg,logics_reg,\
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291 adcs_imm,adcs_reg"))
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292 "tsv110_alu2|tsv110_alu3")
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293
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294 ;; ALU ops with shift
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295 (define_insn_reservation "tsv110_alu_shift" 2
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296 (and (eq_attr "tune" "tsv110")
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297 (eq_attr "type" "extend,\
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298 alu_shift_imm,alu_shift_reg,\
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299 crc,logic_shift_imm,logic_shift_reg,\
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300 mov_shift,mvn_shift,\
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301 mov_shift_reg,mvn_shift_reg"))
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302 "tsv110_mdu")
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303
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304 (define_insn_reservation "tsv110_alus_shift" 2
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305 (and (eq_attr "tune" "tsv110")
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306 (eq_attr "type" "alus_shift_imm,alus_shift_reg,\
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307 logics_shift_imm,logics_shift_reg"))
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308 "tsv110_alu2|tsv110_alu3")
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309
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310 ;; Multiplies instructions
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311 (define_insn_reservation "tsv110_mult" 3
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312 (and (eq_attr "tune" "tsv110")
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313 (ior (eq_attr "mul32" "yes")
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314 (eq_attr "widen_mul64" "yes")))
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315 "tsv110_mdu")
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316
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317 ;; Integer divide
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318 (define_insn_reservation "tsv110_div" 10
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319 (and (eq_attr "tune" "tsv110")
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320 (eq_attr "type" "udiv,sdiv"))
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321 "tsv110_mdu")
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322
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323 ;; Block all issue pipes for a cycle
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324 (define_insn_reservation "tsv110_block" 1
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325 (and (eq_attr "tune" "tsv110")
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326 (eq_attr "type" "block"))
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327 "tsv110_block")
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328
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329 ;; Branch execution Unit
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330 ;;
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331 ;; Branches take two issue slot.
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332 ;; No latency as there is no result
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333 (define_insn_reservation "tsv110_branch" 0
|
|
334 (and (eq_attr "tune" "tsv110")
|
|
335 (eq_attr "type" "branch"))
|
|
336 "tsv110_alu2|tsv110_alu3")
|
|
337
|
|
338 ;; Load-store execution Unit
|
|
339 ;;
|
|
340 ;; Loads of up to two words.
|
|
341 (define_insn_reservation "tsv110_load1" 4
|
|
342 (and (eq_attr "tune" "tsv110")
|
|
343 (eq_attr "type" "load_4,load_8"))
|
|
344 "tsv110_ls1|tsv110_ls2")
|
|
345
|
|
346 ;; Stores of up to two words.
|
|
347 (define_insn_reservation "tsv110_store1" 0
|
|
348 (and (eq_attr "tune" "tsv110")
|
|
349 (eq_attr "type" "store_4,store_8"))
|
|
350 "tsv110_ls1|tsv110_ls2")
|
|
351
|
|
352 ;; Advanced SIMD Unit - Integer Arithmetic Instructions.
|
|
353
|
|
354 (define_insn_reservation "tsv110_neon_abd_aba" 4
|
|
355 (and (eq_attr "tune" "tsv110")
|
|
356 (eq_attr "type" "neon_abd,neon_arith_acc"))
|
|
357 "tsv110_fsu1|tsv110_fsu2")
|
|
358
|
|
359 (define_insn_reservation "tsv110_neon_abd_aba_q" 4
|
|
360 (and (eq_attr "tune" "tsv110")
|
|
361 (eq_attr "type" "neon_arith_acc_q"))
|
|
362 "tsv110_fsu1|tsv110_fsu2")
|
|
363
|
|
364 (define_insn_reservation "tsv110_neon_arith_basic" 2
|
|
365 (and (eq_attr "tune" "tsv110")
|
|
366 (eq_attr "tsv110_neon_type" "neon_arith_basic"))
|
|
367 "tsv110_fsu1|tsv110_fsu2")
|
|
368
|
|
369 (define_insn_reservation "tsv110_neon_arith_complex" 4
|
|
370 (and (eq_attr "tune" "tsv110")
|
|
371 (eq_attr "tsv110_neon_type" "neon_arith_complex"))
|
|
372 "tsv110_fsu1|tsv110_fsu2")
|
|
373
|
|
374 ;; Integer Multiply Instructions.
|
|
375 ;; D-form
|
|
376 (define_insn_reservation "tsv110_neon_multiply" 4
|
|
377 (and (eq_attr "tune" "tsv110")
|
|
378 (eq_attr "tsv110_neon_type" "neon_multiply"))
|
|
379 "tsv110_fsu1")
|
|
380
|
|
381 (define_insn_reservation "tsv110_neon_multiply_dlong" 2
|
|
382 (and (eq_attr "tune" "tsv110")
|
|
383 (eq_attr "type" "neon_mul_d_long"))
|
|
384 "tsv110_fsu1")
|
|
385
|
|
386 ;; Q-form
|
|
387 (define_insn_reservation "tsv110_neon_multiply_q" 8
|
|
388 (and (eq_attr "tune" "tsv110")
|
|
389 (eq_attr "tsv110_neon_type" "neon_multiply_q"))
|
|
390 "tsv110_fsu1")
|
|
391
|
|
392 ;; Integer Shift Instructions.
|
|
393
|
|
394 (define_insn_reservation
|
|
395 "tsv110_neon_shift_acc" 4
|
|
396 (and (eq_attr "tune" "tsv110")
|
|
397 (eq_attr "tsv110_neon_type" "neon_shift_acc,\
|
|
398 neon_shift_imm_basic,neon_shift_imm_complex,neon_shift_reg_basic,\
|
|
399 neon_shift_reg_complex"))
|
|
400 "tsv110_fsu1")
|
|
401
|
|
402 (define_insn_reservation
|
|
403 "tsv110_neon_shift_acc_q" 4
|
|
404 (and (eq_attr "tune" "tsv110")
|
|
405 (eq_attr "tsv110_neon_type" "neon_shift_reg_basic_q,\
|
|
406 neon_shift_reg_complex_q"))
|
|
407 "tsv110_fsu1")
|
|
408
|
|
409 ;; Floating Point Instructions.
|
|
410
|
|
411 (define_insn_reservation
|
|
412 "tsv110_neon_fp_negabs" 2
|
|
413 (and (eq_attr "tune" "tsv110")
|
|
414 (eq_attr "tsv110_neon_type" "neon_fp_negabs"))
|
|
415 "(tsv110_fsu1|tsv110_fsu2)")
|
|
416
|
|
417 (define_insn_reservation
|
|
418 "tsv110_neon_fp_arith" 4
|
|
419 (and (eq_attr "tune" "tsv110")
|
|
420 (eq_attr "tsv110_neon_type" "neon_fp_arith"))
|
|
421 "(tsv110_fsu1|tsv110_fsu2)")
|
|
422
|
|
423 (define_insn_reservation
|
|
424 "tsv110_neon_fp_arith_q" 4
|
|
425 (and (eq_attr "tune" "tsv110")
|
|
426 (eq_attr "tsv110_neon_type" "neon_fp_arith_q"))
|
|
427 "tsv110_fsu1|tsv110_fsu2")
|
|
428
|
|
429 (define_insn_reservation
|
|
430 "tsv110_neon_fp_minmax_q" 2
|
|
431 (and (eq_attr "tune" "tsv110")
|
|
432 (eq_attr "type" "neon_fp_minmax_s_q,neon_fp_minmax_d_q"))
|
|
433 "tsv110_fsu1|tsv110_fsu2")
|
|
434
|
|
435 (define_insn_reservation
|
|
436 "tsv110_neon_fp_reductions_q" 4
|
|
437 (and (eq_attr "tune" "tsv110")
|
|
438 (eq_attr "tsv110_neon_type" "neon_fp_reductions_q"))
|
|
439 "tsv110_fsu1|tsv110_fsu2")
|
|
440
|
|
441 (define_insn_reservation
|
|
442 "tsv110_neon_fp_cvt_int" 2
|
|
443 (and (eq_attr "tune" "tsv110")
|
|
444 (eq_attr "tsv110_neon_type" "neon_fp_cvt_int,neon_fp_cvt_int_q"))
|
|
445 "tsv110_fsu1|tsv110_fsu2")
|
|
446
|
|
447 (define_insn_reservation
|
|
448 "tsv110_neon_fp_mul" 5
|
|
449 (and (eq_attr "tune" "tsv110")
|
|
450 (eq_attr "tsv110_neon_type" "neon_fp_mul"))
|
|
451 "tsv110_fsu1|tsv110_fsu2")
|
|
452
|
|
453 (define_insn_reservation
|
|
454 "tsv110_neon_fp_mul_q" 5
|
|
455 (and (eq_attr "tune" "tsv110")
|
|
456 (eq_attr "tsv110_neon_type" "neon_fp_mul_q"))
|
|
457 "tsv110_fsu1|tsv110_fsu2")
|
|
458
|
|
459 (define_insn_reservation
|
|
460 "tsv110_neon_fp_mla" 7
|
|
461 (and (eq_attr "tune" "tsv110")
|
|
462 (eq_attr "tsv110_neon_type" "neon_fp_mla,\
|
|
463 neon_fp_recps_rsqrts"))
|
|
464 "tsv110_fsu1|tsv110_fsu2")
|
|
465
|
|
466 (define_insn_reservation
|
|
467 "tsv110_neon_fp_recpe_rsqrte" 3
|
|
468 (and (eq_attr "tune" "tsv110")
|
|
469 (eq_attr "tsv110_neon_type" "neon_fp_recpe_rsqrte"))
|
|
470 "tsv110_fsu1|tsv110_fsu2")
|
|
471
|
|
472 (define_insn_reservation
|
|
473 "tsv110_neon_fp_mla_q" 7
|
|
474 (and (eq_attr "tune" "tsv110")
|
|
475 (eq_attr "tsv110_neon_type" "neon_fp_mla_q,\
|
|
476 neon_fp_recps_rsqrts_q"))
|
|
477 "tsv110_fsu1|tsv110_fsu2")
|
|
478
|
|
479 (define_insn_reservation
|
|
480 "tsv110_neon_fp_recpe_rsqrte_q" 3
|
|
481 (and (eq_attr "tune" "tsv110")
|
|
482 (eq_attr "tsv110_neon_type" "neon_fp_recpe_rsqrte_q"))
|
|
483 "tsv110_fsu1|tsv110_fsu2")
|
|
484
|
|
485 ;; Miscellaneous Instructions.
|
|
486
|
|
487 (define_insn_reservation
|
|
488 "tsv110_neon_bitops" 2
|
|
489 (and (eq_attr "tune" "tsv110")
|
|
490 (eq_attr "tsv110_neon_type" "neon_bitops"))
|
|
491 "tsv110_fsu1|tsv110_fsu2")
|
|
492
|
|
493 (define_insn_reservation
|
|
494 "tsv110_neon_dup" 2
|
|
495 (and (eq_attr "tune" "tsv110")
|
|
496 (eq_attr "type" "neon_from_gp,f_mcr"))
|
|
497 "tsv110_fsu1|tsv110_fsu2")
|
|
498
|
|
499 (define_insn_reservation
|
|
500 "tsv110_neon_mov" 2
|
|
501 (and (eq_attr "tune" "tsv110")
|
|
502 (eq_attr "type" "f_mcrr"))
|
|
503 "tsv110_fsu1|tsv110_fsu2")
|
|
504
|
|
505 (define_insn_reservation
|
|
506 "tsv110_neon_bitops_q" 2
|
|
507 (and (eq_attr "tune" "tsv110")
|
|
508 (eq_attr "tsv110_neon_type" "neon_bitops_q"))
|
|
509 "tsv110_fsu1|tsv110_fsu2")
|
|
510
|
|
511 (define_insn_reservation
|
|
512 "tsv110_neon_from_gp_q" 4
|
|
513 (and (eq_attr "tune" "tsv110")
|
|
514 (eq_attr "tsv110_neon_type" "neon_from_gp_q"))
|
|
515 "(tsv110_alu1+tsv110_fsu1)|(tsv110_alu1+tsv110_fsu2)")
|
|
516
|
|
517 (define_insn_reservation
|
|
518 "tsv110_neon_to_gp" 3
|
|
519 (and (eq_attr "tune" "tsv110")
|
|
520 (eq_attr "type" "neon_to_gp,neon_to_gp_q"))
|
|
521 "tsv110_fsu1")
|
|
522
|
|
523 ;; Load Instructions.
|
|
524
|
|
525 (define_insn_reservation
|
|
526 "tsv110_neon_ld1_lane" 8
|
|
527 (and (eq_attr "tune" "tsv110")
|
|
528 (eq_attr "type" "neon_load1_one_lane,neon_load1_one_lane_q,\
|
|
529 neon_load1_all_lanes,neon_load1_all_lanes_q"))
|
|
530 "(tsv110_ls1 + tsv110_fsu1)|(tsv110_ls1 + tsv110_fsu2)|(tsv110_ls2 + tsv110_fsu1)|(tsv110_ls2 + tsv110_fsu2)")
|
|
531
|
|
532 (define_insn_reservation
|
|
533 "tsv110_neon_ld1_reg1" 6
|
|
534 (and (eq_attr "tune" "tsv110")
|
|
535 (eq_attr "type" "f_loads,f_loadd,neon_load1_1reg,neon_load1_1reg_q"))
|
|
536 "tsv110_ls1|tsv110_ls2")
|
|
537
|
|
538 (define_insn_reservation
|
|
539 "tsv110_neon_ld1_reg2" 6
|
|
540 (and (eq_attr "tune" "tsv110")
|
|
541 (eq_attr "type" "neon_load1_2reg,neon_load1_2reg_q"))
|
|
542 "tsv110_ls1|tsv110_ls2")
|
|
543
|
|
544 (define_insn_reservation
|
|
545 "tsv110_neon_ld1_reg3" 7
|
|
546 (and (eq_attr "tune" "tsv110")
|
|
547 (eq_attr "type" "neon_load1_3reg,neon_load1_3reg_q"))
|
|
548 "tsv110_ls1|tsv110_ls2")
|
|
549
|
|
550 (define_insn_reservation
|
|
551 "tsv110_neon_ld1_reg4" 7
|
|
552 (and (eq_attr "tune" "tsv110")
|
|
553 (eq_attr "type" "neon_load1_4reg,neon_load1_4reg_q"))
|
|
554 "tsv110_ls1|tsv110_ls2")
|
|
555
|
|
556 (define_insn_reservation
|
|
557 "tsv110_neon_ld2" 8
|
|
558 (and (eq_attr "tune" "tsv110")
|
|
559 (eq_attr "type" "neon_load1_2reg,neon_load1_2reg_q,\
|
|
560 neon_load2_2reg,neon_load2_2reg_q,neon_load2_all_lanes,\
|
|
561 neon_load2_all_lanes_q,neon_load2_one_lane,neon_load2_one_lane_q"))
|
|
562 "(tsv110_ls1 + tsv110_fsu1)|(tsv110_ls1 + tsv110_fsu2)|(tsv110_ls2 + tsv110_fsu1)|(tsv110_ls2 + tsv110_fsu2)")
|
|
563
|
|
564 (define_insn_reservation
|
|
565 "tsv110_neon_ld3" 9
|
|
566 (and (eq_attr "tune" "tsv110")
|
|
567 (eq_attr "type" "neon_load3_3reg,neon_load3_3reg_q,\
|
|
568 neon_load3_one_lane,neon_load3_one_lane_q,\
|
|
569 neon_load3_all_lanes,neon_load3_all_lanes_q"))
|
|
570 "(tsv110_ls1 + tsv110_fsu1)|(tsv110_ls1 + tsv110_fsu2)|(tsv110_ls2 + tsv110_fsu1)|(tsv110_ls2 + tsv110_fsu2)")
|
|
571
|
|
572 (define_insn_reservation
|
|
573 "tsv110_neon_ld4_lane" 9
|
|
574 (and (eq_attr "tune" "tsv110")
|
|
575 (eq_attr "type" "neon_load4_all_lanes,neon_load4_all_lanes_q,\
|
|
576 neon_load4_one_lane,neon_load4_one_lane_q"))
|
|
577 "(tsv110_ls1 + tsv110_fsu1)|(tsv110_ls1 + tsv110_fsu2)|(tsv110_ls2 + tsv110_fsu1)|(tsv110_ls2 + tsv110_fsu2)")
|
|
578
|
|
579 (define_insn_reservation
|
|
580 "tsv110_neon_ld4_reg" 11
|
|
581 (and (eq_attr "tune" "tsv110")
|
|
582 (eq_attr "type" "neon_load4_all_lanes,neon_load4_all_lanes_q,\
|
|
583 neon_load4_one_lane,neon_load4_one_lane_q"))
|
|
584 "(tsv110_ls1 + tsv110_fsu1)|(tsv110_ls1 + tsv110_fsu2)|(tsv110_ls2 + tsv110_fsu1)|(tsv110_ls2 + tsv110_fsu2)")
|
|
585
|
|
586 ;; Store Instructions.
|
|
587
|
|
588 (define_insn_reservation
|
|
589 "tsv110_neon_store_a" 0
|
|
590 (and (eq_attr "tune" "tsv110")
|
|
591 (eq_attr "tsv110_neon_type" "neon_store_a"))
|
|
592 "tsv110_fsu1|tsv110_fsu2")
|
|
593
|
|
594 (define_insn_reservation
|
|
595 "tsv110_neon_store_b" 0
|
|
596 (and (eq_attr "tune" "tsv110")
|
|
597 (eq_attr "tsv110_neon_type" "neon_store_b"))
|
|
598 "tsv110_fsu1|tsv110_fsu2")
|
|
599
|
|
600 ;; These block issue for a number of cycles proportional to the number
|
|
601 ;; of 64-bit chunks they will store, we don't attempt to model that
|
|
602 ;; precisely, treat them as blocking execution for two cycles when
|
|
603 ;; issued.
|
|
604 (define_insn_reservation
|
|
605 "tsv110_neon_store_complex" 0
|
|
606 (and (eq_attr "tune" "tsv110")
|
|
607 (eq_attr "tsv110_neon_type" "neon_store_complex"))
|
|
608 "tsv110_block*2")
|
|
609
|
|
610 ;; Floating-Point Operations.
|
|
611
|
|
612 (define_insn_reservation "tsv110_fp_const" 2
|
|
613 (and (eq_attr "tune" "tsv110")
|
|
614 (eq_attr "type" "fconsts,fconstd,fmov"))
|
|
615 "tsv110_fsu1|tsv110_fsu2")
|
|
616
|
|
617 (define_insn_reservation "tsv110_fp_add_sub" 5
|
|
618 (and (eq_attr "tune" "tsv110")
|
|
619 (eq_attr "type" "fadds,faddd,fmuls,fmuld"))
|
|
620 "tsv110_fsu1|tsv110_fsu2")
|
|
621
|
|
622 (define_insn_reservation "tsv110_fp_mac" 7
|
|
623 (and (eq_attr "tune" "tsv110")
|
|
624 (eq_attr "type" "fmacs,ffmas,fmacd,ffmad"))
|
|
625 "tsv110_fsu1|tsv110_fsu2")
|
|
626
|
|
627 (define_insn_reservation "tsv110_fp_cvt" 3
|
|
628 (and (eq_attr "tune" "tsv110")
|
|
629 (eq_attr "type" "f_cvt"))
|
|
630 "tsv110_fsu1|tsv110_fsu2")
|
|
631
|
|
632 (define_insn_reservation "tsv110_fp_cvtf2i" 4
|
|
633 (and (eq_attr "tune" "tsv110")
|
|
634 (eq_attr "type" "f_cvtf2i"))
|
|
635 "tsv110_fsu1")
|
|
636
|
|
637 (define_insn_reservation "tsv110_fp_cvti2f" 5
|
|
638 (and (eq_attr "tune" "tsv110")
|
|
639 (eq_attr "type" "f_cvti2f"))
|
|
640 "(tsv110_alu1+tsv110_fsu1)|(tsv110_alu1+tsv110_fsu2)")
|
|
641
|
|
642 (define_insn_reservation "tsv110_fp_cmp" 4
|
|
643 (and (eq_attr "tune" "tsv110")
|
|
644 (eq_attr "type" "fcmps,fcmpd"))
|
|
645 "tsv110_fsu1|tsv110_fsu2")
|
|
646
|
|
647 (define_insn_reservation "tsv110_fp_arith" 2
|
|
648 (and (eq_attr "tune" "tsv110")
|
|
649 (eq_attr "type" "ffariths,ffarithd"))
|
|
650 "tsv110_fsu1|tsv110_fsu2")
|
|
651
|
|
652 (define_insn_reservation "tsv110_fp_divs" 12
|
|
653 (and (eq_attr "tune" "tsv110")
|
|
654 (eq_attr "type" "fdivs,neon_fp_div_s,fdivd,neon_fp_div_d,\
|
|
655 neon_fp_div_s_q,neon_fp_div_d_q"))
|
|
656 "tsv110_fsu1")
|
|
657
|
|
658 (define_insn_reservation "tsv110_fp_sqrts" 24
|
|
659 (and (eq_attr "tune" "tsv110")
|
|
660 (eq_attr "type" "fsqrts,neon_fp_sqrt_s,fsqrtd,neon_fp_sqrt_d,\
|
|
661 neon_fp_sqrt_s_q,neon_fp_sqrt_d_q"))
|
|
662 "tsv110_fsu2")
|
|
663
|
|
664 (define_insn_reservation "tsv110_crypto_aes" 3
|
|
665 (and (eq_attr "tune" "tsv110")
|
|
666 (eq_attr "type" "crypto_aese,crypto_aesmc"))
|
|
667 "tsv110_fsu1")
|
|
668
|
|
669 (define_insn_reservation "tsv110_crypto_sha1_fast" 2
|
|
670 (and (eq_attr "tune" "tsv110")
|
|
671 (eq_attr "type" "crypto_sha1_fast,crypto_sha1_xor"))
|
|
672 "(tsv110_fsu1|tsv110_fsu2)")
|
|
673
|
|
674 (define_insn_reservation "tsv110_crypto_sha256_fast" 2
|
|
675 (and (eq_attr "tune" "tsv110")
|
|
676 (eq_attr "type" "crypto_sha256_fast"))
|
|
677 "tsv110_fsu1")
|
|
678
|
|
679 (define_insn_reservation "tsv110_crypto_complex" 5
|
|
680 (and (eq_attr "tune" "tsv110")
|
|
681 (eq_attr "type" "crypto_sha1_slow,crypto_sha256_slow"))
|
|
682 "tsv110_fsu1")
|
|
683
|
|
684 ;; We lie with calls. They take up all issue slots, but are otherwise
|
|
685 ;; not harmful.
|
|
686 (define_insn_reservation "tsv110_call" 1
|
|
687 (and (eq_attr "tune" "tsv110")
|
|
688 (eq_attr "type" "call"))
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|
689 "tsv110_alu1_issue+tsv110_alu2_issue+tsv110_alu3_issue+tsv110_fsu1_issue+tsv110_fsu2_issue\
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690 +tsv110_mdu_issue+tsv110_ls1_issue+tsv110_ls2_issue"
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691 )
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692
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693 ;; Simple execution unit bypasses
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694 (define_bypass 1 "tsv110_alu"
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695 "tsv110_alu,tsv110_alu_shift")
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696 (define_bypass 2 "tsv110_alu_shift"
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697 "tsv110_alu,tsv110_alu_shift")
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698
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699 ;; An MLA or a MUL can feed a dependent MLA.
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700 (define_bypass 3 "tsv110_neon_*mla*,tsv110_neon_*mul*"
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701 "tsv110_neon_*mla*")
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702
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703 ;; We don't need to care about control hazards, either the branch is
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704 ;; predicted in which case we pay no penalty, or the branch is
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705 ;; mispredicted in which case instruction scheduling will be unlikely to
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706 ;; help.
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707 (define_bypass 1 "tsv110_*"
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708 "tsv110_call,tsv110_branch")
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