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1 ;; Machine description of the Synopsys DesignWare ARC cpu for GNU C compiler
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2 ;; Copyright (C) 2007-2020 Free Software Foundation, Inc.
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111
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3
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4 ;; This file is part of GCC.
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5
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6 ;; GCC is free software; you can redistribute it and/or modify
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7 ;; it under the terms of the GNU General Public License as published by
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8 ;; the Free Software Foundation; either version 3, or (at your option)
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9 ;; any later version.
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10
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11 ;; GCC is distributed in the hope that it will be useful,
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12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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14 ;; GNU General Public License for more details.
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15
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16 ;; You should have received a copy of the GNU General Public License
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17 ;; along with GCC; see the file COPYING3. If not see
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18 ;; <http://www.gnu.org/licenses/>.
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19
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20 (define_c_enum "unspec" [
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21 ;; Va, Vb, Vc builtins
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22 UNSPEC_ARC_SIMD_VADDAW
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23 UNSPEC_ARC_SIMD_VADDW
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24 UNSPEC_ARC_SIMD_VAVB
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25 UNSPEC_ARC_SIMD_VAVRB
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26 UNSPEC_ARC_SIMD_VDIFAW
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27 UNSPEC_ARC_SIMD_VDIFW
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28 UNSPEC_ARC_SIMD_VMAXAW
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29 UNSPEC_ARC_SIMD_VMAXW
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30 UNSPEC_ARC_SIMD_VMINAW
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31 UNSPEC_ARC_SIMD_VMINW
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32 UNSPEC_ARC_SIMD_VMULAW
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33 UNSPEC_ARC_SIMD_VMULFAW
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34 UNSPEC_ARC_SIMD_VMULFW
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35 UNSPEC_ARC_SIMD_VMULW
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36 UNSPEC_ARC_SIMD_VSUBAW
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37 UNSPEC_ARC_SIMD_VSUBW
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38 UNSPEC_ARC_SIMD_VSUMMW
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39 UNSPEC_ARC_SIMD_VAND
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40 UNSPEC_ARC_SIMD_VANDAW
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41 UNSPEC_ARC_SIMD_VBIC
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42 UNSPEC_ARC_SIMD_VBICAW
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43 UNSPEC_ARC_SIMD_VOR
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44 UNSPEC_ARC_SIMD_VXOR
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45 UNSPEC_ARC_SIMD_VXORAW
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46 UNSPEC_ARC_SIMD_VEQW
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47 UNSPEC_ARC_SIMD_VLEW
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48 UNSPEC_ARC_SIMD_VLTW
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49 UNSPEC_ARC_SIMD_VNEW
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50 UNSPEC_ARC_SIMD_VMR1AW
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51 UNSPEC_ARC_SIMD_VMR1W
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52 UNSPEC_ARC_SIMD_VMR2AW
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53 UNSPEC_ARC_SIMD_VMR2W
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54 UNSPEC_ARC_SIMD_VMR3AW
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55 UNSPEC_ARC_SIMD_VMR3W
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56 UNSPEC_ARC_SIMD_VMR4AW
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57 UNSPEC_ARC_SIMD_VMR4W
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58 UNSPEC_ARC_SIMD_VMR5AW
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59 UNSPEC_ARC_SIMD_VMR5W
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60 UNSPEC_ARC_SIMD_VMR6AW
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61 UNSPEC_ARC_SIMD_VMR6W
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62 UNSPEC_ARC_SIMD_VMR7AW
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63 UNSPEC_ARC_SIMD_VMR7W
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64 UNSPEC_ARC_SIMD_VMRB
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65 UNSPEC_ARC_SIMD_VH264F
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66 UNSPEC_ARC_SIMD_VH264FT
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67 UNSPEC_ARC_SIMD_VH264FW
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68 UNSPEC_ARC_SIMD_VVC1F
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69 UNSPEC_ARC_SIMD_VVC1FT
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70 ;; Va, Vb, rc/limm builtins
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71 UNSPEC_ARC_SIMD_VBADDW
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72 UNSPEC_ARC_SIMD_VBMAXW
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73 UNSPEC_ARC_SIMD_VBMINW
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74 UNSPEC_ARC_SIMD_VBMULAW
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75 UNSPEC_ARC_SIMD_VBMULFW
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76 UNSPEC_ARC_SIMD_VBMULW
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77 UNSPEC_ARC_SIMD_VBRSUBW
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78 UNSPEC_ARC_SIMD_VBSUBW
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79
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80 ;; Va, Vb, Ic builtins
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81 UNSPEC_ARC_SIMD_VASRW
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82 UNSPEC_ARC_SIMD_VSR8
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83 UNSPEC_ARC_SIMD_VSR8AW
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84
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85 ;; Va, Vb, Ic builtins
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86 UNSPEC_ARC_SIMD_VASRRWi
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87 UNSPEC_ARC_SIMD_VASRSRWi
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88 UNSPEC_ARC_SIMD_VASRWi
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89 UNSPEC_ARC_SIMD_VASRPWBi
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90 UNSPEC_ARC_SIMD_VASRRPWBi
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91 UNSPEC_ARC_SIMD_VSR8AWi
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92 UNSPEC_ARC_SIMD_VSR8i
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93
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94 ;; Va, Vb, u8 (simm) builtins
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95 UNSPEC_ARC_SIMD_VMVAW
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96 UNSPEC_ARC_SIMD_VMVW
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97 UNSPEC_ARC_SIMD_VMVZW
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98 UNSPEC_ARC_SIMD_VD6TAPF
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99
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100 ;; Va, rlimm, u8 (simm) builtins
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101 UNSPEC_ARC_SIMD_VMOVAW
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102 UNSPEC_ARC_SIMD_VMOVW
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103 UNSPEC_ARC_SIMD_VMOVZW
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104
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105 ;; Va, Vb builtins
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106 UNSPEC_ARC_SIMD_VABSAW
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107 UNSPEC_ARC_SIMD_VABSW
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108 UNSPEC_ARC_SIMD_VADDSUW
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109 UNSPEC_ARC_SIMD_VSIGNW
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110 UNSPEC_ARC_SIMD_VEXCH1
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111 UNSPEC_ARC_SIMD_VEXCH2
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112 UNSPEC_ARC_SIMD_VEXCH4
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113 UNSPEC_ARC_SIMD_VUPBAW
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114 UNSPEC_ARC_SIMD_VUPBW
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115 UNSPEC_ARC_SIMD_VUPSBAW
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116 UNSPEC_ARC_SIMD_VUPSBW
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117
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118 UNSPEC_ARC_SIMD_VDIRUN
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119 UNSPEC_ARC_SIMD_VDORUN
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120 UNSPEC_ARC_SIMD_VDIWR
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121 UNSPEC_ARC_SIMD_VDOWR
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122
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123 UNSPEC_ARC_SIMD_VREC
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124 UNSPEC_ARC_SIMD_VRUN
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125 UNSPEC_ARC_SIMD_VRECRUN
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126 UNSPEC_ARC_SIMD_VENDREC
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127
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128 UNSPEC_ARC_SIMD_VCAST
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129 UNSPEC_ARC_SIMD_VINTI
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130 ])
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131
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132 ;; Scheduler descriptions for the simd instructions
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133 (define_insn_reservation "simd_lat_0_insn" 1
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134 (eq_attr "type" "simd_dma, simd_vstore, simd_vcontrol")
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135 "issue+simd_unit")
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136
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137 (define_insn_reservation "simd_lat_1_insn" 2
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138 (eq_attr "type" "simd_vcompare, simd_vlogic,
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139 simd_vmove_else_zero, simd_varith_1cycle")
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140 "issue+simd_unit, nothing")
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141
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142 (define_insn_reservation "simd_lat_2_insn" 3
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143 (eq_attr "type" "simd_valign, simd_vpermute,
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144 simd_vpack, simd_varith_2cycle")
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145 "issue+simd_unit, nothing*2")
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146
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147 (define_insn_reservation "simd_lat_3_insn" 4
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148 (eq_attr "type" "simd_valign_with_acc, simd_vpack_with_acc,
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149 simd_vlogic_with_acc, simd_vload128,
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150 simd_vmove_with_acc, simd_vspecial_3cycle,
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151 simd_varith_with_acc")
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152 "issue+simd_unit, nothing*3")
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153
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154 (define_insn_reservation "simd_lat_4_insn" 5
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155 (eq_attr "type" "simd_vload, simd_vmove, simd_vspecial_4cycle")
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156 "issue+simd_unit, nothing*4")
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157
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158 (define_expand "movv8hi"
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159 [(set (match_operand:V8HI 0 "general_operand" "")
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160 (match_operand:V8HI 1 "general_operand" ""))]
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161 ""
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162 "
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163 {
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164 /* Everything except mem = const or mem = mem can be done easily. */
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165
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166 if (GET_CODE (operands[0]) == MEM && GET_CODE(operands[1]) == MEM)
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167 operands[1] = force_reg (V8HImode, operands[1]);
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168 }")
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169
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170 ;; This pattern should appear before the movv8hi_insn pattern
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171 (define_insn "vld128_insn"
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172 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
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173 (mem:V8HI (plus:SI (zero_extend:SI (vec_select:HI (match_operand:V8HI 1 "vector_register_operand" "v")
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174 (parallel [(match_operand:SI 2 "immediate_operand" "L")])))
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175 (match_operand:SI 3 "immediate_operand" "P"))))]
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176 "TARGET_SIMD_SET"
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177 "vld128 %0, [i%2, %3]"
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178 [(set_attr "type" "simd_vload128")
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179 (set_attr "length" "4")
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180 (set_attr "cond" "nocond")]
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181 )
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182
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183 (define_insn "vst128_insn"
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184 [(set (mem:V8HI (plus:SI (zero_extend:SI (vec_select:HI (match_operand:V8HI 0 "vector_register_operand" "v")
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185 (parallel [(match_operand:SI 1 "immediate_operand" "L")])))
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186 (match_operand:SI 2 "immediate_operand" "P")))
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187 (match_operand:V8HI 3 "vector_register_operand" "=v"))]
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188 "TARGET_SIMD_SET"
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189 "vst128 %3, [i%1, %2]"
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190 [(set_attr "type" "simd_vstore")
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191 (set_attr "length" "4")
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192 (set_attr "cond" "nocond")]
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193 )
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194
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195 (define_insn "vst64_insn"
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196 [(set (mem:V4HI
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197 (plus:SI
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198 (zero_extend:SI
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199 (vec_select:HI (match_operand:V8HI 0 "vector_register_operand" "v")
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200 (parallel
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201 [(match_operand:SI 1 "immediate_operand" "L")])))
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202 (match_operand:SI 2 "immediate_operand" "P")))
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203 (vec_select:V4HI
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204 (match_operand:V8HI 3 "vector_register_operand" "=v")
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205 (parallel [(const_int 0) (const_int 1) (const_int 2) (const_int 3)])))]
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206 "TARGET_SIMD_SET"
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207 "vst64 %3, [i%1, %2]"
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208 [(set_attr "type" "simd_vstore")
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209 (set_attr "length" "4")
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210 (set_attr "cond" "nocond")]
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211 )
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212
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213 (define_insn "movv8hi_insn"
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214 [(set (match_operand:V8HI 0 "vector_register_or_memory_operand" "=v,m,v")
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215 (match_operand:V8HI 1 "vector_register_or_memory_operand" "m,v,v"))]
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216 "TARGET_SIMD_SET && !(GET_CODE (operands[0]) == MEM && GET_CODE(operands[1]) == MEM)"
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217 "@
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218 vld128r %0, %1
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219 vst128r %1, %0
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220 vmvzw %0,%1,0xffff"
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221 [(set_attr "type" "simd_vload128,simd_vstore,simd_vmove_else_zero")
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222 (set_attr "length" "8,8,4")
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223 (set_attr "cond" "nocond, nocond, nocond")])
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224
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225 (define_insn "movti_insn"
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226 [(set (match_operand:TI 0 "vector_register_or_memory_operand" "=v,m,v")
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227 (match_operand:TI 1 "vector_register_or_memory_operand" "m,v,v"))]
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228 ""
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229 "@
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230 vld128r %0, %1
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231 vst128r %1, %0
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232 vmvzw %0,%1,0xffff"
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233 [(set_attr "type" "simd_vload128,simd_vstore,simd_vmove_else_zero")
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234 (set_attr "length" "8,8,4")
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235 (set_attr "cond" "nocond, nocond, nocond")])
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236
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237 ;; (define_insn "*movv8hi_insn_rr"
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238 ;; [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
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239 ;; (match_operand:V8HI 1 "vector_register_operand" "v"))]
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240 ;; ""
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241 ;; "mov reg,reg"
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242 ;; [(set_attr "length" "8")
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243 ;; (set_attr "type" "move")])
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244
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245 ;; (define_insn "*movv8_out"
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246 ;; [(set (match_operand:V8HI 0 "memory_operand" "=m")
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247 ;; (match_operand:V8HI 1 "vector_register_operand" "v"))]
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248 ;; ""
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249 ;; "mov out"
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250 ;; [(set_attr "length" "8")
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251 ;; (set_attr "type" "move")])
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252
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253
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254 ;; (define_insn "addv8hi3"
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255 ;; [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
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256 ;; (plus:V8HI (match_operand:V8HI 1 "vector_register_operand" "v")
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257 ;; (match_operand:V8HI 2 "vector_register_operand" "v")))]
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258 ;; "TARGET_SIMD_SET"
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259 ;; "vaddw %0, %1, %2"
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260 ;; [(set_attr "length" "8")
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261 ;; (set_attr "cond" "nocond")])
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262
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263 ;; (define_insn "vaddw_insn"
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264 ;; [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
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265 ;; (unspec [(match_operand:V8HI 1 "vector_register_operand" "v")
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266 ;; (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VADDW))]
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267 ;; "TARGET_SIMD_SET"
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268 ;; "vaddw %0, %1, %2"
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269 ;; [(set_attr "length" "8")
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270 ;; (set_attr "cond" "nocond")])
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271
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272 ;; V V V Insns
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273 (define_insn "vaddaw_insn"
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274 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
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275 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
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276 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VADDAW))]
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277 "TARGET_SIMD_SET"
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278 "vaddaw %0, %1, %2"
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279 [(set_attr "type" "simd_varith_with_acc")
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280 (set_attr "length" "4")
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281 (set_attr "cond" "nocond")])
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282
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283 (define_insn "vaddw_insn"
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284 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
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285 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
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286 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VADDW))]
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287 "TARGET_SIMD_SET"
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288 "vaddw %0, %1, %2"
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289 [(set_attr "type" "simd_varith_1cycle")
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290 (set_attr "length" "4")
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291 (set_attr "cond" "nocond")])
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292
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293 (define_insn "vavb_insn"
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294 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
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295 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
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296 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VAVB))]
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297 "TARGET_SIMD_SET"
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298 "vavb %0, %1, %2"
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299 [(set_attr "type" "simd_varith_1cycle")
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300 (set_attr "length" "4")
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301 (set_attr "cond" "nocond")])
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302
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303 (define_insn "vavrb_insn"
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304 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
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305 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
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306 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VAVRB))]
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307 "TARGET_SIMD_SET"
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308 "vavrb %0, %1, %2"
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309 [(set_attr "type" "simd_varith_1cycle")
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310 (set_attr "length" "4")
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311 (set_attr "cond" "nocond")])
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312
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313 (define_insn "vdifaw_insn"
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314 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
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315 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
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316 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VDIFAW))]
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317 "TARGET_SIMD_SET"
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318 "vdifaw %0, %1, %2"
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319 [(set_attr "type" "simd_varith_with_acc")
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320 (set_attr "length" "4")
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321 (set_attr "cond" "nocond")])
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322
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323 (define_insn "vdifw_insn"
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324 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
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325 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
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326 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VDIFW))]
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327 "TARGET_SIMD_SET"
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328 "vdifw %0, %1, %2"
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329 [(set_attr "type" "simd_varith_1cycle")
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330 (set_attr "length" "4")
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331 (set_attr "cond" "nocond")])
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332
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333 (define_insn "vmaxaw_insn"
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334 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
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335 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
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336 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMAXAW))]
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337 "TARGET_SIMD_SET"
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338 "vmaxaw %0, %1, %2"
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339 [(set_attr "type" "simd_varith_with_acc")
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340 (set_attr "length" "4")
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341 (set_attr "cond" "nocond")])
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342
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343 (define_insn "vmaxw_insn"
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344 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
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345 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
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346 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMAXW))]
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347 "TARGET_SIMD_SET"
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348 "vmaxw %0, %1, %2"
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349 [(set_attr "type" "simd_varith_1cycle")
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350 (set_attr "length" "4")
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351 (set_attr "cond" "nocond")])
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352
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353 (define_insn "vminaw_insn"
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354 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
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355 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
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356 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMINAW))]
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357 "TARGET_SIMD_SET"
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358 "vminaw %0, %1, %2"
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359 [(set_attr "type" "simd_varith_with_acc")
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360 (set_attr "length" "4")
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361 (set_attr "cond" "nocond")])
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362
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363 (define_insn "vminw_insn"
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364 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
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365 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
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366 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMINW))]
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367 "TARGET_SIMD_SET"
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368 "vminw %0, %1, %2"
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369 [(set_attr "type" "simd_varith_1cycle")
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370 (set_attr "length" "4")
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371 (set_attr "cond" "nocond")])
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372
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373 (define_insn "vmulaw_insn"
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374 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
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375 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
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376 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMULAW))]
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377 "TARGET_SIMD_SET"
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378 "vmulaw %0, %1, %2"
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379 [(set_attr "type" "simd_varith_with_acc")
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380 (set_attr "length" "4")
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381 (set_attr "cond" "nocond")])
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382
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|
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383 (define_insn "vmulfaw_insn"
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384 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
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|
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385 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
|
|
|
386 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMULFAW))]
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387 "TARGET_SIMD_SET"
|
|
|
388 "vmulfaw %0, %1, %2"
|
|
|
389 [(set_attr "type" "simd_varith_with_acc")
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|
390 (set_attr "length" "4")
|
|
|
391 (set_attr "cond" "nocond")])
|
|
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392
|
|
|
393 (define_insn "vmulfw_insn"
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|
|
394 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
|
|
|
395 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
|
|
|
396 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMULFW))]
|
|
|
397 "TARGET_SIMD_SET"
|
|
|
398 "vmulfw %0, %1, %2"
|
|
|
399 [(set_attr "type" "simd_varith_2cycle")
|
|
|
400 (set_attr "length" "4")
|
|
|
401 (set_attr "cond" "nocond")])
|
|
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402
|
|
|
403 (define_insn "vmulw_insn"
|
|
|
404 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
|
|
|
405 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
|
|
|
406 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMULW))]
|
|
|
407 "TARGET_SIMD_SET"
|
|
|
408 "vmulw %0, %1, %2"
|
|
|
409 [(set_attr "type" "simd_varith_2cycle")
|
|
|
410 (set_attr "length" "4")
|
|
|
411 (set_attr "cond" "nocond")])
|
|
|
412
|
|
|
413 (define_insn "vsubaw_insn"
|
|
|
414 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
|
|
|
415 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
|
|
|
416 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VSUBAW))]
|
|
|
417 "TARGET_SIMD_SET"
|
|
|
418 "vsubaw %0, %1, %2"
|
|
|
419 [(set_attr "type" "simd_varith_with_acc")
|
|
|
420 (set_attr "length" "4")
|
|
|
421 (set_attr "cond" "nocond")])
|
|
|
422
|
|
|
423 (define_insn "vsubw_insn"
|
|
|
424 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
|
|
|
425 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
|
|
|
426 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VSUBW))]
|
|
|
427 "TARGET_SIMD_SET"
|
|
|
428 "vsubw %0, %1, %2"
|
|
|
429 [(set_attr "type" "simd_varith_1cycle")
|
|
|
430 (set_attr "length" "4")
|
|
|
431 (set_attr "cond" "nocond")])
|
|
|
432
|
|
|
433 (define_insn "vsummw_insn"
|
|
|
434 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
|
|
|
435 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
|
|
|
436 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VSUMMW))]
|
|
|
437 "TARGET_SIMD_SET"
|
|
|
438 "vsummw %0, %1, %2"
|
|
|
439 [(set_attr "type" "simd_varith_2cycle")
|
|
|
440 (set_attr "length" "4")
|
|
|
441 (set_attr "cond" "nocond")])
|
|
|
442
|
|
|
443 (define_insn "vand_insn"
|
|
|
444 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
|
|
|
445 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
|
|
|
446 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VAND))]
|
|
|
447 "TARGET_SIMD_SET"
|
|
|
448 "vand %0, %1, %2"
|
|
|
449 [(set_attr "type" "simd_vlogic")
|
|
|
450 (set_attr "length" "4")
|
|
|
451 (set_attr "cond" "nocond")])
|
|
|
452
|
|
|
453 (define_insn "vandaw_insn"
|
|
|
454 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
|
|
|
455 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
|
|
|
456 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VANDAW))]
|
|
|
457 "TARGET_SIMD_SET"
|
|
|
458 "vandaw %0, %1, %2"
|
|
|
459 [(set_attr "type" "simd_vlogic_with_acc")
|
|
|
460 (set_attr "length" "4")
|
|
|
461 (set_attr "cond" "nocond")])
|
|
|
462
|
|
|
463 (define_insn "vbic_insn"
|
|
|
464 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
|
|
|
465 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
|
|
|
466 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VBIC))]
|
|
|
467 "TARGET_SIMD_SET"
|
|
|
468 "vbic %0, %1, %2"
|
|
|
469 [(set_attr "type" "simd_vlogic")
|
|
|
470 (set_attr "length" "4")
|
|
|
471 (set_attr "cond" "nocond")])
|
|
|
472
|
|
|
473 (define_insn "vbicaw_insn"
|
|
|
474 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
|
|
|
475 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
|
|
|
476 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VBICAW))]
|
|
|
477 "TARGET_SIMD_SET"
|
|
|
478 "vbicaw %0, %1, %2"
|
|
|
479 [(set_attr "type" "simd_vlogic_with_acc")
|
|
|
480 (set_attr "length" "4")
|
|
|
481 (set_attr "cond" "nocond")])
|
|
|
482
|
|
|
483 (define_insn "vor_insn"
|
|
|
484 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
|
|
|
485 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
|
|
|
486 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VOR))]
|
|
|
487 "TARGET_SIMD_SET"
|
|
|
488 "vor %0, %1, %2"
|
|
|
489 [(set_attr "type" "simd_vlogic")
|
|
|
490 (set_attr "length" "4")
|
|
|
491 (set_attr "cond" "nocond")])
|
|
|
492
|
|
|
493 (define_insn "vxor_insn"
|
|
|
494 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
|
|
|
495 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
|
|
|
496 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VXOR))]
|
|
|
497 "TARGET_SIMD_SET"
|
|
|
498 "vxor %0, %1, %2"
|
|
|
499 [(set_attr "type" "simd_vlogic")
|
|
|
500 (set_attr "length" "4")
|
|
|
501 (set_attr "cond" "nocond")])
|
|
|
502
|
|
|
503 (define_insn "vxoraw_insn"
|
|
|
504 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
|
|
|
505 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
|
|
|
506 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VXORAW))]
|
|
|
507 "TARGET_SIMD_SET"
|
|
|
508 "vxoraw %0, %1, %2"
|
|
|
509 [(set_attr "type" "simd_vlogic_with_acc")
|
|
|
510 (set_attr "length" "4")
|
|
|
511 (set_attr "cond" "nocond")])
|
|
|
512
|
|
|
513 (define_insn "veqw_insn"
|
|
|
514 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
|
|
|
515 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
|
|
|
516 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VEQW))]
|
|
|
517 "TARGET_SIMD_SET"
|
|
|
518 "veqw %0, %1, %2"
|
|
|
519 [(set_attr "type" "simd_vcompare")
|
|
|
520 (set_attr "length" "4")
|
|
|
521 (set_attr "cond" "nocond")])
|
|
|
522
|
|
|
523 (define_insn "vlew_insn"
|
|
|
524 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
|
|
|
525 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
|
|
|
526 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VLEW))]
|
|
|
527 "TARGET_SIMD_SET"
|
|
|
528 "vlew %0, %1, %2"
|
|
|
529 [(set_attr "type" "simd_vcompare")
|
|
|
530 (set_attr "length" "4")
|
|
|
531 (set_attr "cond" "nocond")])
|
|
|
532
|
|
|
533 (define_insn "vltw_insn"
|
|
|
534 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
|
|
|
535 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
|
|
|
536 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VLTW))]
|
|
|
537 "TARGET_SIMD_SET"
|
|
|
538 "vltw %0, %1, %2"
|
|
|
539 [(set_attr "type" "simd_vcompare")
|
|
|
540 (set_attr "length" "4")
|
|
|
541 (set_attr "cond" "nocond")])
|
|
|
542
|
|
|
543 (define_insn "vnew_insn"
|
|
|
544 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
|
|
|
545 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
|
|
|
546 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VNEW))]
|
|
|
547 "TARGET_SIMD_SET"
|
|
|
548 "vnew %0, %1, %2"
|
|
|
549 [(set_attr "type" "simd_vcompare")
|
|
|
550 (set_attr "length" "4")
|
|
|
551 (set_attr "cond" "nocond")])
|
|
|
552
|
|
|
553 (define_insn "vmr1aw_insn"
|
|
|
554 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
|
|
|
555 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
|
|
|
556 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMR1AW))]
|
|
|
557 "TARGET_SIMD_SET"
|
|
|
558 "vmr1aw %0, %1, %2"
|
|
|
559 [(set_attr "type" "simd_valign_with_acc")
|
|
|
560 (set_attr "length" "4")
|
|
|
561 (set_attr "cond" "nocond")])
|
|
|
562
|
|
|
563 (define_insn "vmr1w_insn"
|
|
|
564 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
|
|
|
565 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
|
|
|
566 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMR1W))]
|
|
|
567 "TARGET_SIMD_SET"
|
|
|
568 "vmr1w %0, %1, %2"
|
|
|
569 [(set_attr "type" "simd_valign")
|
|
|
570 (set_attr "length" "4")
|
|
|
571 (set_attr "cond" "nocond")])
|
|
|
572
|
|
|
573 (define_insn "vmr2aw_insn"
|
|
|
574 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
|
|
|
575 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
|
|
|
576 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMR2AW))]
|
|
|
577 "TARGET_SIMD_SET"
|
|
|
578 "vmr2aw %0, %1, %2"
|
|
|
579 [(set_attr "type" "simd_valign_with_acc")
|
|
|
580 (set_attr "length" "4")
|
|
|
581 (set_attr "cond" "nocond")])
|
|
|
582
|
|
|
583 (define_insn "vmr2w_insn"
|
|
|
584 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
|
|
|
585 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
|
|
|
586 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMR2W))]
|
|
|
587 "TARGET_SIMD_SET"
|
|
|
588 "vmr2w %0, %1, %2"
|
|
|
589 [(set_attr "type" "simd_valign")
|
|
|
590 (set_attr "length" "4")
|
|
|
591 (set_attr "cond" "nocond")])
|
|
|
592
|
|
|
593 (define_insn "vmr3aw_insn"
|
|
|
594 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
|
|
|
595 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
|
|
|
596 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMR3AW))]
|
|
|
597 "TARGET_SIMD_SET"
|
|
|
598 "vmr3aw %0, %1, %2"
|
|
|
599 [(set_attr "type" "simd_valign_with_acc")
|
|
|
600 (set_attr "length" "4")
|
|
|
601 (set_attr "cond" "nocond")])
|
|
|
602
|
|
|
603 (define_insn "vmr3w_insn"
|
|
|
604 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
|
|
|
605 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
|
|
|
606 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMR3W))]
|
|
|
607 "TARGET_SIMD_SET"
|
|
|
608 "vmr3w %0, %1, %2"
|
|
|
609 [(set_attr "type" "simd_valign")
|
|
|
610 (set_attr "length" "4")
|
|
|
611 (set_attr "cond" "nocond")])
|
|
|
612
|
|
|
613 (define_insn "vmr4aw_insn"
|
|
|
614 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
|
|
|
615 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
|
|
|
616 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMR4AW))]
|
|
|
617 "TARGET_SIMD_SET"
|
|
|
618 "vmr4aw %0, %1, %2"
|
|
|
619 [(set_attr "type" "simd_valign_with_acc")
|
|
|
620 (set_attr "length" "4")
|
|
|
621 (set_attr "cond" "nocond")])
|
|
|
622
|
|
|
623 (define_insn "vmr4w_insn"
|
|
|
624 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
|
|
|
625 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
|
|
|
626 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMR4W))]
|
|
|
627 "TARGET_SIMD_SET"
|
|
|
628 "vmr4w %0, %1, %2"
|
|
|
629 [(set_attr "type" "simd_valign")
|
|
|
630 (set_attr "length" "4")
|
|
|
631 (set_attr "cond" "nocond")])
|
|
|
632
|
|
|
633 (define_insn "vmr5aw_insn"
|
|
|
634 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
|
|
|
635 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
|
|
|
636 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMR5AW))]
|
|
|
637 "TARGET_SIMD_SET"
|
|
|
638 "vmr5aw %0, %1, %2"
|
|
|
639 [(set_attr "type" "simd_valign_with_acc")
|
|
|
640 (set_attr "length" "4")
|
|
|
641 (set_attr "cond" "nocond")])
|
|
|
642
|
|
|
643 (define_insn "vmr5w_insn"
|
|
|
644 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
|
|
|
645 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
|
|
|
646 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMR5W))]
|
|
|
647 "TARGET_SIMD_SET"
|
|
|
648 "vmr5w %0, %1, %2"
|
|
|
649 [(set_attr "type" "simd_valign")
|
|
|
650 (set_attr "length" "4")
|
|
|
651 (set_attr "cond" "nocond")])
|
|
|
652
|
|
|
653 (define_insn "vmr6aw_insn"
|
|
|
654 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
|
|
|
655 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
|
|
|
656 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMR6AW))]
|
|
|
657 "TARGET_SIMD_SET"
|
|
|
658 "vmr6aw %0, %1, %2"
|
|
|
659 [(set_attr "type" "simd_valign_with_acc")
|
|
|
660 (set_attr "length" "4")
|
|
|
661 (set_attr "cond" "nocond")])
|
|
|
662
|
|
|
663 (define_insn "vmr6w_insn"
|
|
|
664 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
|
|
|
665 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
|
|
|
666 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMR6W))]
|
|
|
667 "TARGET_SIMD_SET"
|
|
|
668 "vmr6w %0, %1, %2"
|
|
|
669 [(set_attr "type" "simd_valign")
|
|
|
670 (set_attr "length" "4")
|
|
|
671 (set_attr "cond" "nocond")])
|
|
|
672
|
|
|
673 (define_insn "vmr7aw_insn"
|
|
|
674 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
|
|
|
675 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
|
|
|
676 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMR7AW))]
|
|
|
677 "TARGET_SIMD_SET"
|
|
|
678 "vmr7aw %0, %1, %2"
|
|
|
679 [(set_attr "type" "simd_valign_with_acc")
|
|
|
680 (set_attr "length" "4")
|
|
|
681 (set_attr "cond" "nocond")])
|
|
|
682
|
|
|
683 (define_insn "vmr7w_insn"
|
|
|
684 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
|
|
|
685 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
|
|
|
686 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMR7W))]
|
|
|
687 "TARGET_SIMD_SET"
|
|
|
688 "vmr7w %0, %1, %2"
|
|
|
689 [(set_attr "type" "simd_valign")
|
|
|
690 (set_attr "length" "4")
|
|
|
691 (set_attr "cond" "nocond")])
|
|
|
692
|
|
|
693 (define_insn "vmrb_insn"
|
|
|
694 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
|
|
|
695 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
|
|
|
696 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VMRB))]
|
|
|
697 "TARGET_SIMD_SET"
|
|
|
698 "vmrb %0, %1, %2"
|
|
|
699 [(set_attr "type" "simd_valign")
|
|
|
700 (set_attr "length" "4")
|
|
|
701 (set_attr "cond" "nocond")])
|
|
|
702
|
|
|
703 (define_insn "vh264f_insn"
|
|
|
704 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
|
|
|
705 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
|
|
|
706 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VH264F))]
|
|
|
707 "TARGET_SIMD_SET"
|
|
|
708 "vh264f %0, %1, %2"
|
|
|
709 [(set_attr "type" "simd_vspecial_3cycle")
|
|
|
710 (set_attr "length" "4")
|
|
|
711 (set_attr "cond" "nocond")])
|
|
|
712
|
|
|
713 (define_insn "vh264ft_insn"
|
|
|
714 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
|
|
|
715 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
|
|
|
716 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VH264FT))]
|
|
|
717 "TARGET_SIMD_SET"
|
|
|
718 "vh264ft %0, %1, %2"
|
|
|
719 [(set_attr "type" "simd_vspecial_3cycle")
|
|
|
720 (set_attr "length" "4")
|
|
|
721 (set_attr "cond" "nocond")])
|
|
|
722
|
|
|
723 (define_insn "vh264fw_insn"
|
|
|
724 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
|
|
|
725 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
|
|
|
726 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VH264FW))]
|
|
|
727 "TARGET_SIMD_SET"
|
|
|
728 "vh264fw %0, %1, %2"
|
|
|
729 [(set_attr "type" "simd_vspecial_3cycle")
|
|
|
730 (set_attr "length" "4")
|
|
|
731 (set_attr "cond" "nocond")])
|
|
|
732
|
|
|
733 (define_insn "vvc1f_insn"
|
|
|
734 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
|
|
|
735 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
|
|
|
736 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VVC1F))]
|
|
|
737 "TARGET_SIMD_SET"
|
|
|
738 "vvc1f %0, %1, %2"
|
|
|
739 [(set_attr "type" "simd_vspecial_3cycle")
|
|
|
740 (set_attr "length" "4")
|
|
|
741 (set_attr "cond" "nocond")])
|
|
|
742
|
|
|
743 (define_insn "vvc1ft_insn"
|
|
|
744 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
|
|
|
745 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
|
|
|
746 (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VVC1FT))]
|
|
|
747 "TARGET_SIMD_SET"
|
|
|
748 "vvc1ft %0, %1, %2"
|
|
|
749 [(set_attr "type" "simd_vspecial_3cycle")
|
|
|
750 (set_attr "length" "4")
|
|
|
751 (set_attr "cond" "nocond")])
|
|
|
752
|
|
|
753
|
|
|
754
|
|
|
755 ;;---
|
|
|
756 ;; V V r/limm Insns
|
|
|
757
|
|
|
758 ;; (define_insn "vbaddw_insn"
|
|
|
759 ;; [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
|
|
|
760 ;; (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
|
|
|
761 ;; (match_operand:SI 2 "nonmemory_operand" "rCal")] UNSPEC_ARC_SIMD_VBADDW))]
|
|
|
762 ;; "TARGET_SIMD_SET"
|
|
|
763 ;; "vbaddw %0, %1, %2"
|
|
|
764 ;; [(set_attr "length" "4")
|
|
|
765 ;; (set_attr "cond" "nocond")])
|
|
|
766
|
|
|
767 (define_insn "vbaddw_insn"
|
|
|
768 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
|
|
|
769 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
|
|
|
770 (match_operand:SI 2 "nonmemory_operand" "r")] UNSPEC_ARC_SIMD_VBADDW))]
|
|
|
771 "TARGET_SIMD_SET"
|
|
|
772 "vbaddw %0, %1, %2"
|
|
|
773 [(set_attr "type" "simd_varith_1cycle")
|
|
|
774 (set_attr "length" "4")
|
|
|
775 (set_attr "cond" "nocond")])
|
|
|
776
|
|
|
777 (define_insn "vbmaxw_insn"
|
|
|
778 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
|
|
|
779 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
|
|
|
780 (match_operand:SI 2 "nonmemory_operand" "r")] UNSPEC_ARC_SIMD_VBMAXW))]
|
|
|
781 "TARGET_SIMD_SET"
|
|
|
782 "vbmaxw %0, %1, %2"
|
|
|
783 [(set_attr "type" "simd_varith_1cycle")
|
|
|
784 (set_attr "length" "4")
|
|
|
785 (set_attr "cond" "nocond")])
|
|
|
786
|
|
|
787 (define_insn "vbminw_insn"
|
|
|
788 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
|
|
|
789 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
|
|
|
790 (match_operand:SI 2 "nonmemory_operand" "r")] UNSPEC_ARC_SIMD_VBMINW))]
|
|
|
791 "TARGET_SIMD_SET"
|
|
|
792 "vbminw %0, %1, %2"
|
|
|
793 [(set_attr "type" "simd_varith_1cycle")
|
|
|
794 (set_attr "length" "4")
|
|
|
795 (set_attr "cond" "nocond")])
|
|
|
796
|
|
|
797 (define_insn "vbmulaw_insn"
|
|
|
798 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
|
|
|
799 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
|
|
|
800 (match_operand:SI 2 "nonmemory_operand" "r")] UNSPEC_ARC_SIMD_VBMULAW))]
|
|
|
801 "TARGET_SIMD_SET"
|
|
|
802 "vbmulaw %0, %1, %2"
|
|
|
803 [(set_attr "type" "simd_varith_with_acc")
|
|
|
804 (set_attr "length" "4")
|
|
|
805 (set_attr "cond" "nocond")])
|
|
|
806
|
|
|
807 (define_insn "vbmulfw_insn"
|
|
|
808 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
|
|
|
809 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
|
|
|
810 (match_operand:SI 2 "nonmemory_operand" "r")] UNSPEC_ARC_SIMD_VBMULFW))]
|
|
|
811 "TARGET_SIMD_SET"
|
|
|
812 "vbmulfw %0, %1, %2"
|
|
|
813 [(set_attr "type" "simd_varith_2cycle")
|
|
|
814 (set_attr "length" "4")
|
|
|
815 (set_attr "cond" "nocond")])
|
|
|
816
|
|
|
817 (define_insn "vbmulw_insn"
|
|
|
818 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
|
|
|
819 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
|
|
|
820 (match_operand:SI 2 "nonmemory_operand" "r")] UNSPEC_ARC_SIMD_VBMULW))]
|
|
|
821 "TARGET_SIMD_SET"
|
|
|
822 "vbmulw %0, %1, %2"
|
|
|
823 [(set_attr "type" "simd_varith_2cycle")
|
|
|
824 (set_attr "length" "4")
|
|
|
825 (set_attr "cond" "nocond")])
|
|
|
826
|
|
|
827 (define_insn "vbrsubw_insn"
|
|
|
828 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
|
|
|
829 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
|
|
|
830 (match_operand:SI 2 "nonmemory_operand" "r")] UNSPEC_ARC_SIMD_VBRSUBW))]
|
|
|
831 "TARGET_SIMD_SET"
|
|
|
832 "vbrsubw %0, %1, %2"
|
|
|
833 [(set_attr "type" "simd_varith_1cycle")
|
|
|
834 (set_attr "length" "4")
|
|
|
835 (set_attr "cond" "nocond")])
|
|
|
836
|
|
|
837 (define_insn "vbsubw_insn"
|
|
|
838 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
|
|
|
839 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
|
|
|
840 (match_operand:SI 2 "nonmemory_operand" "r")] UNSPEC_ARC_SIMD_VBSUBW))]
|
|
|
841 "TARGET_SIMD_SET"
|
|
|
842 "vbsubw %0, %1, %2"
|
|
|
843 [(set_attr "type" "simd_varith_1cycle")
|
|
|
844 (set_attr "length" "4")
|
|
|
845 (set_attr "cond" "nocond")])
|
|
|
846 ; Va, Vb, Ic instructions
|
|
|
847
|
|
|
848 ; Va, Vb, u6 instructions
|
|
|
849 (define_insn "vasrrwi_insn"
|
|
|
850 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
|
|
|
851 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
|
|
|
852 (match_operand:SI 2 "immediate_operand" "L")] UNSPEC_ARC_SIMD_VASRRWi))]
|
|
|
853 "TARGET_SIMD_SET"
|
|
|
854 "vasrrwi %0, %1, %2"
|
|
|
855 [(set_attr "type" "simd_varith_2cycle")
|
|
|
856 (set_attr "length" "4")
|
|
|
857 (set_attr "cond" "nocond")])
|
|
|
858
|
|
|
859 (define_insn "vasrsrwi_insn"
|
|
|
860 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
|
|
|
861 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
|
|
|
862 (match_operand:SI 2 "immediate_operand" "L")] UNSPEC_ARC_SIMD_VASRSRWi))]
|
|
|
863 "TARGET_SIMD_SET"
|
|
|
864 "vasrsrwi %0, %1, %2"
|
|
|
865 [(set_attr "type" "simd_varith_2cycle")
|
|
|
866 (set_attr "length" "4")
|
|
|
867 (set_attr "cond" "nocond")])
|
|
|
868
|
|
|
869 (define_insn "vasrwi_insn"
|
|
|
870 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
|
|
|
871 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
|
|
|
872 (match_operand:SI 2 "immediate_operand" "L")] UNSPEC_ARC_SIMD_VASRWi))]
|
|
|
873 "TARGET_SIMD_SET"
|
|
|
874 "vasrwi %0, %1, %2"
|
|
|
875 [(set_attr "type" "simd_varith_1cycle")
|
|
|
876 (set_attr "length" "4")
|
|
|
877 (set_attr "cond" "nocond")])
|
|
|
878
|
|
|
879 (define_insn "vasrpwbi_insn"
|
|
|
880 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
|
|
|
881 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
|
|
|
882 (match_operand:SI 2 "immediate_operand" "L")] UNSPEC_ARC_SIMD_VASRPWBi))]
|
|
|
883 "TARGET_SIMD_SET"
|
|
|
884 "vasrpwbi %0, %1, %2"
|
|
|
885 [(set_attr "type" "simd_vpack")
|
|
|
886 (set_attr "length" "4")
|
|
|
887 (set_attr "cond" "nocond")])
|
|
|
888
|
|
|
889 (define_insn "vasrrpwbi_insn"
|
|
|
890 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
|
|
|
891 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
|
|
|
892 (match_operand:SI 2 "immediate_operand" "L")] UNSPEC_ARC_SIMD_VASRRPWBi))]
|
|
|
893 "TARGET_SIMD_SET"
|
|
|
894 "vasrrpwbi %0, %1, %2"
|
|
|
895 [(set_attr "type" "simd_vpack")
|
|
|
896 (set_attr "length" "4")
|
|
|
897 (set_attr "cond" "nocond")])
|
|
|
898
|
|
|
899 (define_insn "vsr8awi_insn"
|
|
|
900 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
|
|
|
901 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
|
|
|
902 (match_operand:SI 2 "immediate_operand" "L")] UNSPEC_ARC_SIMD_VSR8AWi))]
|
|
|
903 "TARGET_SIMD_SET"
|
|
|
904 "vsr8awi %0, %1, %2"
|
|
|
905 [(set_attr "type" "simd_valign_with_acc")
|
|
|
906 (set_attr "length" "4")
|
|
|
907 (set_attr "cond" "nocond")])
|
|
|
908
|
|
|
909 (define_insn "vsr8i_insn"
|
|
|
910 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
|
|
|
911 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
|
|
|
912 (match_operand:SI 2 "immediate_operand" "L")] UNSPEC_ARC_SIMD_VSR8i))]
|
|
|
913 "TARGET_SIMD_SET"
|
|
|
914 "vsr8i %0, %1, %2"
|
|
|
915 [(set_attr "type" "simd_valign")
|
|
|
916 (set_attr "length" "4")
|
|
|
917 (set_attr "cond" "nocond")])
|
|
|
918
|
|
|
919 ;; Va, Vb, u8 (simm) insns
|
|
|
920
|
|
|
921 (define_insn "vmvaw_insn"
|
|
|
922 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
|
|
|
923 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
|
|
|
924 (match_operand:SI 2 "immediate_operand" "P")] UNSPEC_ARC_SIMD_VMVAW))]
|
|
|
925 "TARGET_SIMD_SET"
|
|
|
926 "vmvaw %0, %1, %2"
|
|
|
927 [(set_attr "type" "simd_vmove_with_acc")
|
|
|
928 (set_attr "length" "4")
|
|
|
929 (set_attr "cond" "nocond")])
|
|
|
930
|
|
|
931 (define_insn "vmvw_insn"
|
|
|
932 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
|
|
|
933 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
|
|
|
934 (match_operand:SI 2 "immediate_operand" "P")] UNSPEC_ARC_SIMD_VMVW))]
|
|
|
935 "TARGET_SIMD_SET"
|
|
|
936 "vmvw %0, %1, %2"
|
|
|
937 [(set_attr "type" "simd_vmove")
|
|
|
938 (set_attr "length" "4")
|
|
|
939 (set_attr "cond" "nocond")])
|
|
|
940
|
|
|
941 (define_insn "vmvzw_insn"
|
|
|
942 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
|
|
|
943 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
|
|
|
944 (match_operand:SI 2 "immediate_operand" "P")] UNSPEC_ARC_SIMD_VMVZW))]
|
|
|
945 "TARGET_SIMD_SET"
|
|
|
946 "vmvzw %0, %1, %2"
|
|
|
947 [(set_attr "type" "simd_vmove_else_zero")
|
|
|
948 (set_attr "length" "4")
|
|
|
949 (set_attr "cond" "nocond")])
|
|
|
950
|
|
|
951 (define_insn "vd6tapf_insn"
|
|
|
952 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
|
|
|
953 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
|
|
|
954 (match_operand:SI 2 "immediate_operand" "P")] UNSPEC_ARC_SIMD_VD6TAPF))]
|
|
|
955 "TARGET_SIMD_SET"
|
|
|
956 "vd6tapf %0, %1, %2"
|
|
|
957 [(set_attr "type" "simd_vspecial_4cycle")
|
|
|
958 (set_attr "length" "4")
|
|
|
959 (set_attr "cond" "nocond")])
|
|
|
960
|
|
|
961 ;; Va, rlimm, u8 (simm) insns
|
|
|
962 (define_insn "vmovaw_insn"
|
|
|
963 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
|
|
|
964 (unspec:V8HI [(match_operand:SI 1 "nonmemory_operand" "r")
|
|
|
965 (match_operand:SI 2 "immediate_operand" "P")] UNSPEC_ARC_SIMD_VMOVAW))]
|
|
|
966 "TARGET_SIMD_SET"
|
|
|
967 "vmovaw %0, %1, %2"
|
|
|
968 [(set_attr "type" "simd_vmove_with_acc")
|
|
|
969 (set_attr "length" "4")
|
|
|
970 (set_attr "cond" "nocond")])
|
|
|
971
|
|
|
972 (define_insn "vmovw_insn"
|
|
|
973 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
|
|
|
974 (unspec:V8HI [(match_operand:SI 1 "nonmemory_operand" "r")
|
|
|
975 (match_operand:SI 2 "immediate_operand" "P")] UNSPEC_ARC_SIMD_VMOVW))]
|
|
|
976 "TARGET_SIMD_SET"
|
|
|
977 "vmovw %0, %1, %2"
|
|
|
978 [(set_attr "type" "simd_vmove")
|
|
|
979 (set_attr "length" "4")
|
|
|
980 (set_attr "cond" "nocond")])
|
|
|
981
|
|
|
982 (define_insn "vmovzw_insn"
|
|
|
983 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
|
|
|
984 (unspec:V8HI [(match_operand:SI 1 "nonmemory_operand" "r")
|
|
|
985 (match_operand:SI 2 "immediate_operand" "P")] UNSPEC_ARC_SIMD_VMOVZW))]
|
|
|
986 "TARGET_SIMD_SET"
|
|
|
987 "vmovzw %0, %1, %2"
|
|
|
988 [(set_attr "type" "simd_vmove_else_zero")
|
|
|
989 (set_attr "length" "4")
|
|
|
990 (set_attr "cond" "nocond")])
|
|
|
991
|
|
|
992 ;; Va, rlimm, Ic insns
|
|
|
993 (define_insn "vsr8_insn"
|
|
|
994 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
|
|
|
995 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
|
|
|
996 (match_operand:SI 2 "immediate_operand" "K")
|
|
|
997 (match_operand:V8HI 3 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VSR8))]
|
|
|
998 "TARGET_SIMD_SET"
|
|
|
999 "vsr8 %0, %1, i%2"
|
|
|
1000 [(set_attr "type" "simd_valign")
|
|
|
1001 (set_attr "length" "4")
|
|
|
1002 (set_attr "cond" "nocond")])
|
|
|
1003
|
|
|
1004 (define_insn "vasrw_insn"
|
|
|
1005 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
|
|
|
1006 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
|
|
|
1007 (match_operand:SI 2 "immediate_operand" "K")
|
|
|
1008 (match_operand:V8HI 3 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VASRW))]
|
|
|
1009 "TARGET_SIMD_SET"
|
|
|
1010 "vasrw %0, %1, i%2"
|
|
|
1011 [(set_attr "type" "simd_varith_1cycle")
|
|
|
1012 (set_attr "length" "4")
|
|
|
1013 (set_attr "cond" "nocond")])
|
|
|
1014
|
|
|
1015 (define_insn "vsr8aw_insn"
|
|
|
1016 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
|
|
|
1017 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
|
|
|
1018 (match_operand:SI 2 "immediate_operand" "K")
|
|
|
1019 (match_operand:V8HI 3 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VSR8AW))]
|
|
|
1020 "TARGET_SIMD_SET"
|
|
|
1021 "vsr8aw %0, %1, i%2"
|
|
|
1022 [(set_attr "type" "simd_valign_with_acc")
|
|
|
1023 (set_attr "length" "4")
|
|
|
1024 (set_attr "cond" "nocond")])
|
|
|
1025
|
|
|
1026 ;; Va, Vb insns
|
|
|
1027 (define_insn "vabsaw_insn"
|
|
|
1028 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
|
|
|
1029 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VABSAW))]
|
|
|
1030 "TARGET_SIMD_SET"
|
|
|
1031 "vabsaw %0, %1"
|
|
|
1032 [(set_attr "type" "simd_varith_with_acc")
|
|
|
1033 (set_attr "length" "4")
|
|
|
1034 (set_attr "cond" "nocond")])
|
|
|
1035
|
|
|
1036 (define_insn "vabsw_insn"
|
|
|
1037 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
|
|
|
1038 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VABSW))]
|
|
|
1039 "TARGET_SIMD_SET"
|
|
|
1040 "vabsw %0, %1"
|
|
|
1041 [(set_attr "type" "simd_varith_1cycle")
|
|
|
1042 (set_attr "length" "4")
|
|
|
1043 (set_attr "cond" "nocond")])
|
|
|
1044
|
|
|
1045 (define_insn "vaddsuw_insn"
|
|
|
1046 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
|
|
|
1047 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VADDSUW))]
|
|
|
1048 "TARGET_SIMD_SET"
|
|
|
1049 "vaddsuw %0, %1"
|
|
|
1050 [(set_attr "type" "simd_varith_1cycle")
|
|
|
1051 (set_attr "length" "4")
|
|
|
1052 (set_attr "cond" "nocond")])
|
|
|
1053
|
|
|
1054 (define_insn "vsignw_insn"
|
|
|
1055 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
|
|
|
1056 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VSIGNW))]
|
|
|
1057 "TARGET_SIMD_SET"
|
|
|
1058 "vsignw %0, %1"
|
|
|
1059 [(set_attr "type" "simd_varith_1cycle")
|
|
|
1060 (set_attr "length" "4")
|
|
|
1061 (set_attr "cond" "nocond")])
|
|
|
1062
|
|
|
1063 (define_insn "vexch1_insn"
|
|
|
1064 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
|
|
|
1065 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VEXCH1))]
|
|
|
1066 "TARGET_SIMD_SET"
|
|
|
1067 "vexch1 %0, %1"
|
|
|
1068 [(set_attr "type" "simd_vpermute")
|
|
|
1069 (set_attr "length" "4")
|
|
|
1070 (set_attr "cond" "nocond")])
|
|
|
1071
|
|
|
1072 (define_insn "vexch2_insn"
|
|
|
1073 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
|
|
|
1074 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VEXCH2))]
|
|
|
1075 "TARGET_SIMD_SET"
|
|
|
1076 "vexch2 %0, %1"
|
|
|
1077 [(set_attr "type" "simd_vpermute")
|
|
|
1078 (set_attr "length" "4")
|
|
|
1079 (set_attr "cond" "nocond")])
|
|
|
1080
|
|
|
1081 (define_insn "vexch4_insn"
|
|
|
1082 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
|
|
|
1083 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VEXCH4))]
|
|
|
1084 "TARGET_SIMD_SET"
|
|
|
1085 "vexch4 %0, %1"
|
|
|
1086 [(set_attr "type" "simd_vpermute")
|
|
|
1087 (set_attr "length" "4")
|
|
|
1088 (set_attr "cond" "nocond")])
|
|
|
1089
|
|
|
1090 (define_insn "vupbaw_insn"
|
|
|
1091 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
|
|
|
1092 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VUPBAW))]
|
|
|
1093 "TARGET_SIMD_SET"
|
|
|
1094 "vupbaw %0, %1"
|
|
|
1095 [(set_attr "type" "simd_vpack_with_acc")
|
|
|
1096 (set_attr "length" "4")
|
|
|
1097 (set_attr "cond" "nocond")])
|
|
|
1098
|
|
|
1099 (define_insn "vupbw_insn"
|
|
|
1100 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
|
|
|
1101 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VUPBW))]
|
|
|
1102 "TARGET_SIMD_SET"
|
|
|
1103 "vupbw %0, %1"
|
|
|
1104 [(set_attr "type" "simd_vpack")
|
|
|
1105 (set_attr "length" "4")
|
|
|
1106 (set_attr "cond" "nocond")])
|
|
|
1107
|
|
|
1108 (define_insn "vupsbaw_insn"
|
|
|
1109 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
|
|
|
1110 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VUPSBAW))]
|
|
|
1111 "TARGET_SIMD_SET"
|
|
|
1112 "vupsbaw %0, %1"
|
|
|
1113 [(set_attr "type" "simd_vpack_with_acc")
|
|
|
1114 (set_attr "length" "4")
|
|
|
1115 (set_attr "cond" "nocond")])
|
|
|
1116
|
|
|
1117 (define_insn "vupsbw_insn"
|
|
|
1118 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
|
|
|
1119 (unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VUPSBW))]
|
|
|
1120 "TARGET_SIMD_SET"
|
|
|
1121 "vupsbw %0, %1"
|
|
|
1122 [(set_attr "type" "simd_vpack")
|
|
|
1123 (set_attr "length" "4")
|
|
|
1124 (set_attr "cond" "nocond")])
|
|
|
1125
|
|
|
1126 ; DMA setup instructions
|
|
|
1127 (define_insn "vdirun_insn"
|
|
|
1128 [(set (match_operand:SI 0 "arc_simd_dma_register_operand" "=d")
|
|
|
1129 (unspec_volatile:SI [(match_operand:SI 1 "nonmemory_operand" "r")
|
|
|
1130 (match_operand:SI 2 "nonmemory_operand" "r")] UNSPEC_ARC_SIMD_VDIRUN))]
|
|
|
1131 "TARGET_SIMD_SET"
|
|
|
1132 "vdirun %1, %2"
|
|
|
1133 [(set_attr "type" "simd_dma")
|
|
|
1134 (set_attr "length" "4")
|
|
|
1135 (set_attr "cond" "nocond")])
|
|
|
1136
|
|
|
1137 (define_insn "vdorun_insn"
|
|
|
1138 [(set (match_operand:SI 0 "arc_simd_dma_register_operand" "=d")
|
|
|
1139 (unspec_volatile:SI [(match_operand:SI 1 "nonmemory_operand" "r")
|
|
|
1140 (match_operand:SI 2 "nonmemory_operand" "r")] UNSPEC_ARC_SIMD_VDORUN))]
|
|
|
1141 "TARGET_SIMD_SET"
|
|
|
1142 "vdorun %1, %2"
|
|
|
1143 [(set_attr "type" "simd_dma")
|
|
|
1144 (set_attr "length" "4")
|
|
|
1145 (set_attr "cond" "nocond")])
|
|
|
1146
|
|
|
1147 (define_insn "vdiwr_insn"
|
|
|
1148 [(set (match_operand:SI 0 "arc_simd_dma_register_operand" "=d,d")
|
|
|
1149 (unspec_volatile:SI [(match_operand:SI 1 "nonmemory_operand" "r,Cal")] UNSPEC_ARC_SIMD_VDIWR))]
|
|
|
1150 "TARGET_SIMD_SET"
|
|
|
1151 "vdiwr %0, %1"
|
|
|
1152 [(set_attr "type" "simd_dma")
|
|
|
1153 (set_attr "length" "4,8")
|
|
|
1154 (set_attr "cond" "nocond,nocond")])
|
|
|
1155
|
|
|
1156 (define_insn "vdowr_insn"
|
|
|
1157 [(set (match_operand:SI 0 "arc_simd_dma_register_operand" "=d,d")
|
|
|
1158 (unspec_volatile:SI [(match_operand:SI 1 "nonmemory_operand" "r,Cal")] UNSPEC_ARC_SIMD_VDOWR))]
|
|
|
1159 "TARGET_SIMD_SET"
|
|
|
1160 "vdowr %0, %1"
|
|
|
1161 [(set_attr "type" "simd_dma")
|
|
|
1162 (set_attr "length" "4,8")
|
|
|
1163 (set_attr "cond" "nocond,nocond")])
|
|
|
1164
|
|
|
1165 ;; vector record and run instructions
|
|
|
1166 (define_insn "vrec_insn"
|
|
|
1167 [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand" "r")] UNSPEC_ARC_SIMD_VREC)]
|
|
|
1168 "TARGET_SIMD_SET"
|
|
|
1169 "vrec %0"
|
|
|
1170 [(set_attr "type" "simd_vcontrol")
|
|
|
1171 (set_attr "length" "4")
|
|
|
1172 (set_attr "cond" "nocond")])
|
|
|
1173
|
|
|
1174 (define_insn "vrun_insn"
|
|
|
1175 [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand" "r")] UNSPEC_ARC_SIMD_VRUN)]
|
|
|
1176 "TARGET_SIMD_SET"
|
|
|
1177 "vrun %0"
|
|
|
1178 [(set_attr "type" "simd_vcontrol")
|
|
|
1179 (set_attr "length" "4")
|
|
|
1180 (set_attr "cond" "nocond")])
|
|
|
1181
|
|
|
1182 (define_insn "vrecrun_insn"
|
|
|
1183 [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand" "r")] UNSPEC_ARC_SIMD_VRECRUN)]
|
|
|
1184 "TARGET_SIMD_SET"
|
|
|
1185 "vrecrun %0"
|
|
|
1186 [(set_attr "type" "simd_vcontrol")
|
|
|
1187 (set_attr "length" "4")
|
|
|
1188 (set_attr "cond" "nocond")])
|
|
|
1189
|
|
|
1190 (define_insn "vendrec_insn"
|
|
|
1191 [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand" "r")] UNSPEC_ARC_SIMD_VENDREC)]
|
|
|
1192 "TARGET_SIMD_SET"
|
|
131
|
1193 "vendrec %0"
|
|
111
|
1194 [(set_attr "type" "simd_vcontrol")
|
|
|
1195 (set_attr "length" "4")
|
|
|
1196 (set_attr "cond" "nocond")])
|
|
|
1197
|
|
|
1198 (define_insn "vld32wh_insn"
|
|
|
1199 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
|
|
|
1200 (vec_concat:V8HI
|
|
|
1201 (zero_extend:V4HI
|
|
|
1202 (mem:V4QI
|
|
|
1203 (plus:SI
|
|
|
1204 (match_operand:SI 1 "immediate_operand" "P")
|
|
|
1205 (zero_extend:SI
|
|
|
1206 (vec_select:HI
|
|
|
1207 (match_operand:V8HI 2 "vector_register_operand" "v")
|
|
|
1208 (parallel [(match_operand:SI 3 "immediate_operand" "L")]))))))
|
|
|
1209 (vec_select:V4HI
|
|
|
1210 (match_dup 0)
|
|
|
1211 (parallel [(const_int 0) (const_int 1) (const_int 2) (const_int 3)])
|
|
|
1212 )))]
|
|
|
1213 "TARGET_SIMD_SET"
|
|
|
1214 "vld32wh %0, [i%3,%1]"
|
|
|
1215 [(set_attr "type" "simd_vload")
|
|
|
1216 (set_attr "length" "4")
|
|
|
1217 (set_attr "cond" "nocond")])
|
|
|
1218
|
|
|
1219 (define_insn "vld32wl_insn"
|
|
|
1220 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
|
|
|
1221 (vec_concat:V8HI
|
|
|
1222 (vec_select:V4HI
|
|
|
1223 (match_dup 0)
|
|
|
1224 (parallel [(const_int 4) (const_int 5) (const_int 6) (const_int 7)]))
|
|
|
1225 (zero_extend:V4HI
|
|
|
1226 (mem:V4QI
|
|
|
1227 (plus:SI
|
|
|
1228 (match_operand:SI 1 "immediate_operand" "P")
|
|
|
1229 (zero_extend:SI
|
|
|
1230 (vec_select:HI (match_operand:V8HI 2 "vector_register_operand" "v")
|
|
|
1231 (parallel
|
|
|
1232 [(match_operand:SI 3 "immediate_operand" "L")]))
|
|
|
1233 ))))))]
|
|
|
1234 "TARGET_SIMD_SET"
|
|
|
1235 "vld32wl %0, [i%3,%1]"
|
|
|
1236 [(set_attr "type" "simd_vload")
|
|
|
1237 (set_attr "length" "4")
|
|
|
1238 (set_attr "cond" "nocond")])
|
|
|
1239
|
|
|
1240 (define_insn "vld64w_insn"
|
|
|
1241 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
|
|
|
1242 (zero_extend:V8HI (mem:V4HI (plus:SI (zero_extend:SI (vec_select:HI (match_operand:V8HI 1 "vector_register_operand" "v")
|
|
|
1243 (parallel [(match_operand:SI 2 "immediate_operand" "L")])))
|
|
|
1244 (match_operand:SI 3 "immediate_operand" "P")))))]
|
|
|
1245 "TARGET_SIMD_SET"
|
|
|
1246 "vld64w %0, [i%2, %3]"
|
|
|
1247 [(set_attr "type" "simd_vload")
|
|
|
1248 (set_attr "length" "4")
|
|
|
1249 (set_attr "cond" "nocond")]
|
|
|
1250 )
|
|
|
1251
|
|
|
1252 (define_insn "vld64_insn"
|
|
|
1253 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
|
|
|
1254 (vec_concat:V8HI
|
|
|
1255 (vec_select:V4HI
|
|
|
1256 (match_dup 0)
|
|
|
1257 (parallel [(const_int 4) (const_int 5) (const_int 6) (const_int 7)]))
|
|
|
1258 (mem:V4HI
|
|
|
1259 (plus:SI
|
|
|
1260 (match_operand:SI 1 "immediate_operand" "P")
|
|
|
1261 (zero_extend:SI
|
|
|
1262 (vec_select:HI
|
|
|
1263 (match_operand:V8HI 2 "vector_register_operand" "v")
|
|
|
1264 (parallel [(match_operand:SI 3 "immediate_operand" "L")]))
|
|
|
1265 )))))]
|
|
|
1266 "TARGET_SIMD_SET"
|
|
|
1267 "vld64 %0, [i%3,%1]"
|
|
|
1268 [(set_attr "type" "simd_vload")
|
|
|
1269 (set_attr "length" "4")
|
|
|
1270 (set_attr "cond" "nocond")])
|
|
|
1271
|
|
|
1272 (define_insn "vld32_insn"
|
|
|
1273 [(set (match_operand:V8HI 0 "vector_register_operand" "=v")
|
|
|
1274 (vec_concat:V8HI
|
|
|
1275 (vec_select:V4HI
|
|
|
1276 (match_dup 0)
|
|
|
1277 (parallel [(const_int 4) (const_int 5) (const_int 6) (const_int 7)]))
|
|
|
1278 (vec_concat:V4HI
|
|
|
1279 (vec_select:V2HI
|
|
|
1280 (match_dup 0)
|
|
|
1281 (parallel [(const_int 2) (const_int 3)]))
|
|
|
1282 (mem:V2HI
|
|
|
1283 (plus:SI
|
|
|
1284 (match_operand:SI 1 "immediate_operand" "P")
|
|
|
1285 (zero_extend:SI
|
|
|
1286 (vec_select:HI
|
|
|
1287 (match_operand:V8HI 2 "vector_register_operand" "v")
|
|
|
1288 (parallel [(match_operand:SI 3 "immediate_operand" "L")]))))))))]
|
|
|
1289 "TARGET_SIMD_SET"
|
|
|
1290 "vld32 %0, [i%3,%1]"
|
|
|
1291 [(set_attr "type" "simd_vload")
|
|
|
1292 (set_attr "length" "4")
|
|
|
1293 (set_attr "cond" "nocond")])
|
|
|
1294
|
|
|
1295 (define_insn "vst16_n_insn"
|
|
|
1296 [(set (mem:HI (plus:SI (match_operand:SI 0 "immediate_operand" "P")
|
|
|
1297 (zero_extend: SI (vec_select:HI (match_operand:V8HI 1 "vector_register_operand" "v")
|
|
|
1298 (parallel [(match_operand:SI 2 "immediate_operand" "L")])))))
|
|
|
1299 (vec_select:HI (match_operand:V8HI 3 "vector_register_operand" "v")
|
|
|
1300 (parallel [(match_operand:SI 4 "immediate_operand" "L")])))]
|
|
|
1301 "TARGET_SIMD_SET"
|
|
|
1302 "vst16_%4 %3,[i%2, %0]"
|
|
|
1303 [(set_attr "type" "simd_vstore")
|
|
|
1304 (set_attr "length" "4")
|
|
|
1305 (set_attr "cond" "nocond")])
|
|
|
1306
|
|
|
1307 (define_insn "vst32_n_insn"
|
|
|
1308 [(set (mem:SI (plus:SI (match_operand:SI 0 "immediate_operand" "P")
|
|
|
1309 (zero_extend: SI (vec_select:HI (match_operand:V8HI 1 "vector_register_operand" "v")
|
|
|
1310 (parallel [(match_operand:SI 2 "immediate_operand" "L")])))))
|
|
|
1311 (vec_select:SI (unspec:V4SI [(match_operand:V8HI 3 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VCAST)
|
|
|
1312 (parallel [(match_operand:SI 4 "immediate_operand" "L")])))]
|
|
|
1313 "TARGET_SIMD_SET"
|
|
|
1314 "vst32_%4 %3,[i%2, %0]"
|
|
|
1315 [(set_attr "type" "simd_vstore")
|
|
|
1316 (set_attr "length" "4")
|
|
|
1317 (set_attr "cond" "nocond")])
|
|
|
1318
|
|
|
1319 ;; SIMD unit interrupt
|
|
|
1320 (define_insn "vinti_insn"
|
|
|
1321 [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand" "L")] UNSPEC_ARC_SIMD_VINTI)]
|
|
|
1322 "TARGET_SIMD_SET"
|
|
|
1323 "vinti %0"
|
|
|
1324 [(set_attr "type" "simd_vcontrol")
|
|
|
1325 (set_attr "length" "4")
|
|
|
1326 (set_attr "cond" "nocond")])
|
|
|
1327
|
|
|
1328 ;; New ARCv2 SIMD extensions
|
|
|
1329
|
|
|
1330 ;;64-bit vectors of halwords and words
|
|
|
1331 (define_mode_iterator VWH [V4HI V2SI])
|
|
|
1332
|
|
|
1333 ;;double element vectors
|
|
|
1334 (define_mode_iterator VDV [V2HI V2SI])
|
|
|
1335 (define_mode_attr V_addsub [(V2HI "HI") (V2SI "SI")])
|
|
|
1336 (define_mode_attr V_addsub_suffix [(V2HI "2h") (V2SI "")])
|
|
|
1337
|
|
|
1338 ;;all vectors
|
|
|
1339 (define_mode_iterator VCT [V2HI V4HI V2SI])
|
|
|
1340 (define_mode_attr V_suffix [(V2HI "2h") (V4HI "4h") (V2SI "2")])
|
|
|
1341
|
|
|
1342 ;; Widening operations.
|
|
|
1343 (define_code_iterator SE [sign_extend zero_extend])
|
|
|
1344 (define_code_attr V_US [(sign_extend "s") (zero_extend "u")])
|
|
|
1345 (define_code_attr V_US_suffix [(sign_extend "") (zero_extend "u")])
|
|
|
1346
|
|
|
1347
|
|
|
1348 ;; Move patterns
|
|
|
1349 (define_expand "movv2hi"
|
|
|
1350 [(set (match_operand:V2HI 0 "move_dest_operand" "")
|
|
|
1351 (match_operand:V2HI 1 "general_operand" ""))]
|
|
|
1352 ""
|
|
|
1353 "{
|
|
|
1354 if (prepare_move_operands (operands, V2HImode))
|
|
|
1355 DONE;
|
|
|
1356 }")
|
|
|
1357
|
|
|
1358 (define_insn_and_split "*movv2hi_insn"
|
|
|
1359 [(set (match_operand:V2HI 0 "move_dest_operand" "=r,r,r,m")
|
|
|
1360 (match_operand:V2HI 1 "general_operand" "i,r,m,r"))]
|
|
|
1361 "(register_operand (operands[0], V2HImode)
|
|
|
1362 || register_operand (operands[1], V2HImode))"
|
|
|
1363 "@
|
|
|
1364 #
|
|
|
1365 mov%? %0, %1
|
|
|
1366 ld%U1%V1 %0,%1
|
|
|
1367 st%U0%V0 %1,%0"
|
|
|
1368 "reload_completed && GET_CODE (operands[1]) == CONST_VECTOR"
|
|
|
1369 [(set (match_dup 0) (match_dup 2))]
|
|
|
1370 {
|
|
|
1371 HOST_WIDE_INT intval = INTVAL (XVECEXP (operands[1], 0, 1)) << 16;
|
|
|
1372 intval |= INTVAL (XVECEXP (operands[1], 0, 0)) & 0xFFFF;
|
|
|
1373
|
|
|
1374 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));
|
|
|
1375 operands[2] = GEN_INT (trunc_int_for_mode (intval, SImode));
|
|
|
1376 }
|
|
|
1377 [(set_attr "type" "move,move,load,store")
|
|
|
1378 (set_attr "predicable" "yes,yes,no,no")
|
|
|
1379 (set_attr "iscompact" "false,false,false,false")
|
|
|
1380 ])
|
|
|
1381
|
|
|
1382 (define_expand "movmisalignv2hi"
|
|
|
1383 [(set (match_operand:V2HI 0 "general_operand" "")
|
|
|
1384 (match_operand:V2HI 1 "general_operand" ""))]
|
|
|
1385 ""
|
|
|
1386 "{
|
|
|
1387 if (prepare_move_operands (operands, V2HImode))
|
|
|
1388 DONE;
|
|
|
1389 }")
|
|
|
1390
|
|
|
1391 (define_expand "mov<mode>"
|
|
|
1392 [(set (match_operand:VWH 0 "move_dest_operand" "")
|
|
|
1393 (match_operand:VWH 1 "general_operand" ""))]
|
|
|
1394 ""
|
|
|
1395 "{
|
|
|
1396 if (prepare_move_operands (operands, <MODE>mode))
|
|
|
1397 DONE;
|
|
|
1398 }")
|
|
|
1399
|
|
|
1400 (define_insn_and_split "*mov<mode>_insn"
|
|
|
1401 [(set (match_operand:VWH 0 "move_dest_operand" "=r,r,r,m")
|
|
|
1402 (match_operand:VWH 1 "general_operand" "i,r,m,r"))]
|
|
|
1403 "TARGET_PLUS_QMACW
|
|
|
1404 && (register_operand (operands[0], <MODE>mode)
|
|
|
1405 || register_operand (operands[1], <MODE>mode))"
|
|
|
1406 "*
|
|
|
1407 {
|
|
|
1408 switch (which_alternative)
|
|
|
1409 {
|
|
|
1410 default:
|
|
|
1411 return \"#\";
|
|
|
1412
|
|
|
1413 case 1:
|
|
|
1414 return \"vadd2 %0, %1, 0\";
|
|
|
1415
|
|
|
1416 case 2:
|
|
|
1417 if (TARGET_LL64)
|
|
|
1418 return \"ldd%U1%V1 %0,%1\";
|
|
|
1419 return \"#\";
|
|
|
1420
|
|
|
1421 case 3:
|
|
|
1422 if (TARGET_LL64)
|
|
|
1423 return \"std%U0%V0 %1,%0\";
|
|
|
1424 return \"#\";
|
|
|
1425 }
|
|
|
1426 }"
|
|
|
1427 "reload_completed"
|
|
|
1428 [(const_int 0)]
|
|
|
1429 {
|
|
|
1430 arc_split_move (operands);
|
|
|
1431 DONE;
|
|
|
1432 }
|
|
|
1433 [(set_attr "type" "move,move,load,store")
|
|
|
1434 (set_attr "predicable" "yes,no,no,no")
|
|
|
1435 (set_attr "iscompact" "false,false,false,false")
|
|
|
1436 ])
|
|
|
1437
|
|
|
1438 (define_expand "movmisalign<mode>"
|
|
|
1439 [(set (match_operand:VWH 0 "general_operand" "")
|
|
|
1440 (match_operand:VWH 1 "general_operand" ""))]
|
|
|
1441 ""
|
|
|
1442 "{
|
|
|
1443 if (prepare_move_operands (operands, <MODE>mode))
|
|
|
1444 DONE;
|
|
|
1445 }")
|
|
|
1446
|
|
|
1447 (define_insn "bswapv2hi2"
|
|
|
1448 [(set (match_operand:V2HI 0 "register_operand" "=r,r")
|
|
|
1449 (bswap:V2HI (match_operand:V2HI 1 "nonmemory_operand" "r,i")))]
|
|
|
1450 "TARGET_V2 && TARGET_SWAP"
|
|
|
1451 "swape %0, %1"
|
|
|
1452 [(set_attr "length" "4,8")
|
|
|
1453 (set_attr "type" "two_cycle_core")])
|
|
|
1454
|
|
|
1455 ;; Simple arithmetic insns
|
|
|
1456 (define_insn "add<mode>3"
|
|
|
1457 [(set (match_operand:VCT 0 "register_operand" "=r,r")
|
|
|
1458 (plus:VCT (match_operand:VCT 1 "register_operand" "0,r")
|
|
|
1459 (match_operand:VCT 2 "register_operand" "r,r")))]
|
|
|
1460 "TARGET_PLUS_DMPY"
|
|
|
1461 "vadd<V_suffix>%? %0, %1, %2"
|
|
|
1462 [(set_attr "length" "4")
|
|
|
1463 (set_attr "type" "multi")
|
|
|
1464 (set_attr "predicable" "yes,no")
|
|
|
1465 (set_attr "cond" "canuse,nocond")])
|
|
|
1466
|
|
|
1467 (define_insn "sub<mode>3"
|
|
|
1468 [(set (match_operand:VCT 0 "register_operand" "=r,r")
|
|
|
1469 (minus:VCT (match_operand:VCT 1 "register_operand" "0,r")
|
|
|
1470 (match_operand:VCT 2 "register_operand" "r,r")))]
|
|
|
1471 "TARGET_PLUS_DMPY"
|
|
|
1472 "vsub<V_suffix>%? %0, %1, %2"
|
|
|
1473 [(set_attr "length" "4")
|
|
|
1474 (set_attr "type" "multi")
|
|
|
1475 (set_attr "predicable" "yes,no")
|
|
|
1476 (set_attr "cond" "canuse,nocond")])
|
|
|
1477
|
|
|
1478 ;; Combined arithmetic ops
|
|
|
1479 (define_insn "addsub<mode>3"
|
|
|
1480 [(set (match_operand:VDV 0 "register_operand" "=r,r")
|
|
|
1481 (vec_concat:VDV
|
|
|
1482 (plus:<V_addsub> (vec_select:<V_addsub> (match_operand:VDV 1 "register_operand" "0,r")
|
|
|
1483 (parallel [(const_int 0)]))
|
|
|
1484 (vec_select:<V_addsub> (match_operand:VDV 2 "register_operand" "r,r")
|
|
|
1485 (parallel [(const_int 0)])))
|
|
|
1486 (minus:<V_addsub> (vec_select:<V_addsub> (match_dup 1) (parallel [(const_int 1)]))
|
|
|
1487 (vec_select:<V_addsub> (match_dup 2) (parallel [(const_int 1)])))))]
|
|
|
1488 "TARGET_PLUS_DMPY"
|
|
|
1489 "vaddsub<V_addsub_suffix>%? %0, %1, %2"
|
|
|
1490 [(set_attr "length" "4")
|
|
|
1491 (set_attr "type" "multi")
|
|
|
1492 (set_attr "predicable" "yes,no")
|
|
|
1493 (set_attr "cond" "canuse,nocond")])
|
|
|
1494
|
|
|
1495 (define_insn "subadd<mode>3"
|
|
|
1496 [(set (match_operand:VDV 0 "register_operand" "=r,r")
|
|
|
1497 (vec_concat:VDV
|
|
|
1498 (minus:<V_addsub> (vec_select:<V_addsub> (match_operand:VDV 1 "register_operand" "0,r")
|
|
|
1499 (parallel [(const_int 0)]))
|
|
|
1500 (vec_select:<V_addsub> (match_operand:VDV 2 "register_operand" "r,r")
|
|
|
1501 (parallel [(const_int 0)])))
|
|
|
1502 (plus:<V_addsub> (vec_select:<V_addsub> (match_dup 1) (parallel [(const_int 1)]))
|
|
|
1503 (vec_select:<V_addsub> (match_dup 2) (parallel [(const_int 1)])))))]
|
|
|
1504 "TARGET_PLUS_DMPY"
|
|
|
1505 "vsubadd<V_addsub_suffix>%? %0, %1, %2"
|
|
|
1506 [(set_attr "length" "4")
|
|
|
1507 (set_attr "type" "multi")
|
|
|
1508 (set_attr "predicable" "yes,no")
|
|
|
1509 (set_attr "cond" "canuse,nocond")])
|
|
|
1510
|
|
|
1511 (define_insn "addsubv4hi3"
|
|
|
1512 [(set (match_operand:V4HI 0 "even_register_operand" "=r,r")
|
|
|
1513 (vec_concat:V4HI
|
|
|
1514 (vec_concat:V2HI
|
|
|
1515 (plus:HI (vec_select:HI (match_operand:V4HI 1 "even_register_operand" "0,r")
|
|
|
1516 (parallel [(const_int 0)]))
|
|
|
1517 (vec_select:HI (match_operand:V4HI 2 "even_register_operand" "r,r")
|
|
|
1518 (parallel [(const_int 0)])))
|
|
|
1519 (minus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))
|
|
|
1520 (vec_select:HI (match_dup 2) (parallel [(const_int 1)]))))
|
|
|
1521 (vec_concat:V2HI
|
|
|
1522 (plus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
|
|
|
1523 (vec_select:HI (match_dup 2) (parallel [(const_int 2)])))
|
|
|
1524 (minus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 3)]))
|
|
|
1525 (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))
|
|
|
1526 ))]
|
|
|
1527 "TARGET_PLUS_QMACW"
|
|
|
1528 "vaddsub4h%? %0, %1, %2"
|
|
|
1529 [(set_attr "length" "4")
|
|
|
1530 (set_attr "type" "multi")
|
|
|
1531 (set_attr "predicable" "yes,no")
|
|
|
1532 (set_attr "cond" "canuse,nocond")])
|
|
|
1533
|
|
|
1534 (define_insn "subaddv4hi3"
|
|
|
1535 [(set (match_operand:V4HI 0 "even_register_operand" "=r,r")
|
|
|
1536 (vec_concat:V4HI
|
|
|
1537 (vec_concat:V2HI
|
|
|
1538 (minus:HI (vec_select:HI (match_operand:V4HI 1 "even_register_operand" "0,r")
|
|
|
1539 (parallel [(const_int 0)]))
|
|
|
1540 (vec_select:HI (match_operand:V4HI 2 "even_register_operand" "r,r")
|
|
|
1541 (parallel [(const_int 0)])))
|
|
|
1542 (plus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))
|
|
|
1543 (vec_select:HI (match_dup 2) (parallel [(const_int 1)]))))
|
|
|
1544 (vec_concat:V2HI
|
|
|
1545 (minus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
|
|
|
1546 (vec_select:HI (match_dup 2) (parallel [(const_int 2)])))
|
|
|
1547 (plus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 3)]))
|
|
|
1548 (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))
|
|
|
1549 ))]
|
|
|
1550 "TARGET_PLUS_QMACW"
|
|
|
1551 "vsubadd4h%? %0, %1, %2"
|
|
|
1552 [(set_attr "length" "4")
|
|
|
1553 (set_attr "type" "multi")
|
|
|
1554 (set_attr "predicable" "yes,no")
|
|
|
1555 (set_attr "cond" "canuse,nocond")])
|
|
|
1556
|
|
|
1557 ;; Multiplication
|
|
|
1558 (define_insn "dmpyh<V_US_suffix>"
|
|
|
1559 [(set (match_operand:SI 0 "register_operand" "=r,r")
|
|
|
1560 (plus:SI
|
|
|
1561 (mult:SI
|
|
|
1562 (SE:SI
|
|
|
1563 (vec_select:HI (match_operand:V2HI 1 "register_operand" "0,r")
|
|
|
1564 (parallel [(const_int 0)])))
|
|
|
1565 (SE:SI
|
|
|
1566 (vec_select:HI (match_operand:V2HI 2 "register_operand" "r,r")
|
|
|
1567 (parallel [(const_int 0)]))))
|
|
|
1568 (mult:SI
|
|
|
1569 (SE:SI (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
|
|
|
1570 (SE:SI (vec_select:HI (match_dup 2) (parallel [(const_int 1)]))))))
|
|
|
1571 (set (reg:DI ARCV2_ACC)
|
|
|
1572 (zero_extend:DI
|
|
|
1573 (plus:SI
|
|
|
1574 (mult:SI
|
|
|
1575 (SE:SI (vec_select:HI (match_dup 1) (parallel [(const_int 0)])))
|
|
|
1576 (SE:SI (vec_select:HI (match_dup 2) (parallel [(const_int 0)]))))
|
|
|
1577 (mult:SI
|
|
|
1578 (SE:SI (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
|
|
|
1579 (SE:SI (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))))]
|
|
|
1580 "TARGET_PLUS_DMPY"
|
|
|
1581 "dmpyh<V_US_suffix>%? %0, %1, %2"
|
|
|
1582 [(set_attr "length" "4")
|
|
|
1583 (set_attr "type" "multi")
|
|
|
1584 (set_attr "predicable" "yes,no")
|
|
|
1585 (set_attr "cond" "canuse,nocond")])
|
|
|
1586
|
|
|
1587 ;; We can use dmac as well here. To be investigated which version
|
|
|
1588 ;; brings more.
|
|
|
1589 (define_expand "sdot_prodv2hi"
|
|
|
1590 [(match_operand:SI 0 "register_operand" "")
|
|
|
1591 (match_operand:V2HI 1 "register_operand" "")
|
|
|
1592 (match_operand:V2HI 2 "register_operand" "")
|
|
|
1593 (match_operand:SI 3 "register_operand" "")]
|
|
|
1594 "TARGET_PLUS_DMPY"
|
|
|
1595 {
|
|
|
1596 rtx t = gen_reg_rtx (SImode);
|
|
|
1597 emit_insn (gen_dmpyh (t, operands[1], operands[2]));
|
|
|
1598 emit_insn (gen_addsi3 (operands[0], operands[3], t));
|
|
|
1599 DONE;
|
|
|
1600 })
|
|
|
1601
|
|
|
1602 (define_expand "udot_prodv2hi"
|
|
|
1603 [(match_operand:SI 0 "register_operand" "")
|
|
|
1604 (match_operand:V2HI 1 "register_operand" "")
|
|
|
1605 (match_operand:V2HI 2 "register_operand" "")
|
|
|
1606 (match_operand:SI 3 "register_operand" "")]
|
|
|
1607 "TARGET_PLUS_DMPY"
|
|
|
1608 {
|
|
|
1609 rtx t = gen_reg_rtx (SImode);
|
|
|
1610 emit_insn (gen_dmpyhu (t, operands[1], operands[2]));
|
|
|
1611 emit_insn (gen_addsi3 (operands[0], operands[3], t));
|
|
|
1612 DONE;
|
|
|
1613 })
|
|
|
1614
|
|
|
1615 (define_insn "arc_vec_<V_US>mult_lo_v4hi"
|
|
|
1616 [(set (match_operand:V2SI 0 "even_register_operand" "=r,r")
|
|
|
1617 (mult:V2SI (SE:V2SI (vec_select:V2HI
|
|
|
1618 (match_operand:V4HI 1 "even_register_operand" "0,r")
|
|
|
1619 (parallel [(const_int 0) (const_int 1)])))
|
|
|
1620 (SE:V2SI (vec_select:V2HI
|
|
|
1621 (match_operand:V4HI 2 "even_register_operand" "r,r")
|
|
|
1622 (parallel [(const_int 0) (const_int 1)])))))
|
|
|
1623 (set (reg:V2SI ARCV2_ACC)
|
|
|
1624 (mult:V2SI (SE:V2SI (vec_select:V2HI (match_dup 1)
|
|
|
1625 (parallel [(const_int 0) (const_int 1)])))
|
|
|
1626 (SE:V2SI (vec_select:V2HI (match_dup 2)
|
|
|
1627 (parallel [(const_int 0) (const_int 1)])))))
|
|
|
1628 ]
|
|
|
1629 "TARGET_PLUS_MACD"
|
|
|
1630 "vmpy2h<V_US_suffix>%? %0, %1, %2"
|
|
|
1631 [(set_attr "length" "4")
|
|
|
1632 (set_attr "type" "multi")
|
|
|
1633 (set_attr "predicable" "yes,no")
|
|
|
1634 (set_attr "cond" "canuse,nocond")])
|
|
|
1635
|
|
|
1636 (define_insn "arc_vec_<V_US>multacc_lo_v4hi"
|
|
|
1637 [(set (reg:V2SI ARCV2_ACC)
|
|
|
1638 (mult:V2SI (SE:V2SI (vec_select:V2HI
|
|
|
1639 (match_operand:V4HI 0 "even_register_operand" "r")
|
|
|
1640 (parallel [(const_int 0) (const_int 1)])))
|
|
|
1641 (SE:V2SI (vec_select:V2HI
|
|
|
1642 (match_operand:V4HI 1 "even_register_operand" "r")
|
|
|
1643 (parallel [(const_int 0) (const_int 1)])))))
|
|
|
1644 ]
|
|
|
1645 "TARGET_PLUS_MACD"
|
|
|
1646 "vmpy2h<V_US_suffix>%? 0, %0, %1"
|
|
|
1647 [(set_attr "length" "4")
|
|
|
1648 (set_attr "type" "multi")
|
|
|
1649 (set_attr "predicable" "no")
|
|
|
1650 (set_attr "cond" "nocond")])
|
|
|
1651
|
|
|
1652 (define_expand "vec_widen_<V_US>mult_lo_v4hi"
|
|
|
1653 [(set (match_operand:V2SI 0 "even_register_operand" "")
|
|
|
1654 (mult:V2SI (SE:V2SI (vec_select:V2HI
|
|
|
1655 (match_operand:V4HI 1 "even_register_operand" "")
|
|
|
1656 (parallel [(const_int 0) (const_int 1)])))
|
|
|
1657 (SE:V2SI (vec_select:V2HI
|
|
|
1658 (match_operand:V4HI 2 "even_register_operand" "")
|
|
|
1659 (parallel [(const_int 0) (const_int 1)])))))]
|
|
|
1660 "TARGET_PLUS_QMACW"
|
|
|
1661 {
|
|
|
1662 emit_insn (gen_arc_vec_<V_US>mult_lo_v4hi (operands[0],
|
|
|
1663 operands[1],
|
|
|
1664 operands[2]));
|
|
|
1665 DONE;
|
|
|
1666 }
|
|
|
1667 )
|
|
|
1668
|
|
|
1669 (define_insn "arc_vec_<V_US>mult_hi_v4hi"
|
|
|
1670 [(set (match_operand:V2SI 0 "even_register_operand" "=r,r")
|
|
|
1671 (mult:V2SI (SE:V2SI (vec_select:V2HI
|
|
|
1672 (match_operand:V4HI 1 "even_register_operand" "0,r")
|
|
|
1673 (parallel [(const_int 2) (const_int 3)])))
|
|
|
1674 (SE:V2SI (vec_select:V2HI
|
|
|
1675 (match_operand:V4HI 2 "even_register_operand" "r,r")
|
|
|
1676 (parallel [(const_int 2) (const_int 3)])))))
|
|
|
1677 (set (reg:V2SI ARCV2_ACC)
|
|
|
1678 (mult:V2SI (SE:V2SI (vec_select:V2HI (match_dup 1)
|
|
|
1679 (parallel [(const_int 2) (const_int 3)])))
|
|
|
1680 (SE:V2SI (vec_select:V2HI (match_dup 2)
|
|
|
1681 (parallel [(const_int 2) (const_int 3)])))))
|
|
|
1682 ]
|
|
|
1683 "TARGET_PLUS_QMACW"
|
|
|
1684 "vmpy2h<V_US_suffix>%? %0, %R1, %R2"
|
|
|
1685 [(set_attr "length" "4")
|
|
|
1686 (set_attr "type" "multi")
|
|
|
1687 (set_attr "predicable" "yes,no")
|
|
|
1688 (set_attr "cond" "canuse,nocond")])
|
|
|
1689
|
|
|
1690 (define_expand "vec_widen_<V_US>mult_hi_v4hi"
|
|
|
1691 [(set (match_operand:V2SI 0 "even_register_operand" "")
|
|
|
1692 (mult:V2SI (SE:V2SI (vec_select:V2HI
|
|
|
1693 (match_operand:V4HI 1 "even_register_operand" "")
|
|
|
1694 (parallel [(const_int 2) (const_int 3)])))
|
|
|
1695 (SE:V2SI (vec_select:V2HI
|
|
|
1696 (match_operand:V4HI 2 "even_register_operand" "")
|
|
|
1697 (parallel [(const_int 2) (const_int 3)])))))]
|
|
|
1698 "TARGET_PLUS_MACD"
|
|
|
1699 {
|
|
|
1700 emit_insn (gen_arc_vec_<V_US>mult_hi_v4hi (operands[0],
|
|
|
1701 operands[1],
|
|
|
1702 operands[2]));
|
|
|
1703 DONE;
|
|
|
1704 }
|
|
|
1705 )
|
|
|
1706
|
|
|
1707 (define_insn "arc_vec_<V_US>mac_hi_v4hi"
|
|
|
1708 [(set (match_operand:V2SI 0 "even_register_operand" "=r,r")
|
|
|
1709 (plus:V2SI
|
|
|
1710 (reg:V2SI ARCV2_ACC)
|
|
|
1711 (mult:V2SI (SE:V2SI (vec_select:V2HI
|
|
|
1712 (match_operand:V4HI 1 "even_register_operand" "0,r")
|
|
|
1713 (parallel [(const_int 2) (const_int 3)])))
|
|
|
1714 (SE:V2SI (vec_select:V2HI
|
|
|
1715 (match_operand:V4HI 2 "even_register_operand" "r,r")
|
|
|
1716 (parallel [(const_int 2) (const_int 3)]))))))
|
|
|
1717 (set (reg:V2SI ARCV2_ACC)
|
|
|
1718 (plus:V2SI
|
|
|
1719 (reg:V2SI ARCV2_ACC)
|
|
|
1720 (mult:V2SI (SE:V2SI (vec_select:V2HI (match_dup 1)
|
|
|
1721 (parallel [(const_int 2) (const_int 3)])))
|
|
|
1722 (SE:V2SI (vec_select:V2HI (match_dup 2)
|
|
|
1723 (parallel [(const_int 2) (const_int 3)]))))))
|
|
|
1724 ]
|
|
|
1725 "TARGET_PLUS_MACD"
|
|
|
1726 "vmac2h<V_US_suffix>%? %0, %R1, %R2"
|
|
|
1727 [(set_attr "length" "4")
|
|
|
1728 (set_attr "type" "multi")
|
|
|
1729 (set_attr "predicable" "yes,no")
|
|
|
1730 (set_attr "cond" "canuse,nocond")])
|
|
|
1731
|
|
|
1732 ;; Builtins
|
|
|
1733 (define_insn "dmach"
|
|
|
1734 [(set (match_operand:SI 0 "register_operand" "=r,r")
|
|
|
1735 (unspec:SI [(match_operand:V2HI 1 "register_operand" "0,r")
|
|
|
1736 (match_operand:V2HI 2 "register_operand" "r,r")
|
|
|
1737 (reg:DI ARCV2_ACC)]
|
|
|
1738 UNSPEC_ARC_DMACH))
|
|
|
1739 (clobber (reg:DI ARCV2_ACC))]
|
|
|
1740 "TARGET_PLUS_DMPY"
|
|
|
1741 "dmach%? %0, %1, %2"
|
|
|
1742 [(set_attr "length" "4")
|
|
|
1743 (set_attr "type" "multi")
|
|
|
1744 (set_attr "predicable" "yes,no")
|
|
|
1745 (set_attr "cond" "canuse,nocond")])
|
|
|
1746
|
|
|
1747 (define_insn "dmachu"
|
|
|
1748 [(set (match_operand:SI 0 "register_operand" "=r,r")
|
|
|
1749 (unspec:SI [(match_operand:V2HI 1 "register_operand" "0,r")
|
|
|
1750 (match_operand:V2HI 2 "register_operand" "r,r")
|
|
|
1751 (reg:DI ARCV2_ACC)]
|
|
|
1752 UNSPEC_ARC_DMACHU))
|
|
|
1753 (clobber (reg:DI ARCV2_ACC))]
|
|
|
1754 "TARGET_PLUS_DMPY"
|
|
|
1755 "dmachu%? %0, %1, %2"
|
|
|
1756 [(set_attr "length" "4")
|
|
|
1757 (set_attr "type" "multi")
|
|
|
1758 (set_attr "predicable" "yes,no")
|
|
|
1759 (set_attr "cond" "canuse,nocond")])
|
|
|
1760
|
|
|
1761 (define_insn "dmacwh"
|
|
|
1762 [(set (match_operand:DI 0 "even_register_operand" "=r,r")
|
|
|
1763 (unspec:DI [(match_operand:V2SI 1 "even_register_operand" "0,r")
|
|
|
1764 (match_operand:V2HI 2 "register_operand" "r,r")
|
|
|
1765 (reg:DI ARCV2_ACC)]
|
|
|
1766 UNSPEC_ARC_DMACWH))
|
|
|
1767 (clobber (reg:DI ARCV2_ACC))]
|
|
|
1768 "TARGET_PLUS_QMACW"
|
|
|
1769 "dmacwh%? %0, %1, %2"
|
|
|
1770 [(set_attr "length" "4")
|
|
|
1771 (set_attr "type" "multi")
|
|
|
1772 (set_attr "predicable" "yes,no")
|
|
|
1773 (set_attr "cond" "canuse,nocond")])
|
|
|
1774
|
|
|
1775 (define_insn "dmacwhu"
|
|
|
1776 [(set (match_operand:DI 0 "register_operand" "=r,r")
|
|
|
1777 (unspec:DI [(match_operand:V2SI 1 "even_register_operand" "0,r")
|
|
|
1778 (match_operand:V2HI 2 "register_operand" "r,r")
|
|
|
1779 (reg:DI ARCV2_ACC)]
|
|
|
1780 UNSPEC_ARC_DMACWHU))
|
|
|
1781 (clobber (reg:DI ARCV2_ACC))]
|
|
|
1782 "TARGET_PLUS_QMACW"
|
|
|
1783 "dmacwhu%? %0, %1, %2"
|
|
|
1784 [(set_attr "length" "4")
|
|
|
1785 (set_attr "type" "multi")
|
|
|
1786 (set_attr "predicable" "yes,no")
|
|
|
1787 (set_attr "cond" "canuse,nocond")])
|
|
|
1788
|
|
|
1789 (define_insn "vmac2h"
|
|
|
1790 [(set (match_operand:V2SI 0 "even_register_operand" "=r,r")
|
|
|
1791 (unspec:V2SI [(match_operand:V2HI 1 "register_operand" "0,r")
|
|
|
1792 (match_operand:V2HI 2 "register_operand" "r,r")
|
|
|
1793 (reg:DI ARCV2_ACC)]
|
|
|
1794 UNSPEC_ARC_VMAC2H))
|
|
|
1795 (clobber (reg:DI ARCV2_ACC))]
|
|
|
1796 "TARGET_PLUS_MACD"
|
|
|
1797 "vmac2h%? %0, %1, %2"
|
|
|
1798 [(set_attr "length" "4")
|
|
|
1799 (set_attr "type" "multi")
|
|
|
1800 (set_attr "predicable" "yes,no")
|
|
|
1801 (set_attr "cond" "canuse,nocond")])
|
|
|
1802
|
|
|
1803 (define_insn "vmac2hu"
|
|
|
1804 [(set (match_operand:V2SI 0 "even_register_operand" "=r,r")
|
|
|
1805 (unspec:V2SI [(match_operand:V2HI 1 "register_operand" "0,r")
|
|
|
1806 (match_operand:V2HI 2 "register_operand" "r,r")
|
|
|
1807 (reg:DI ARCV2_ACC)]
|
|
|
1808 UNSPEC_ARC_VMAC2HU))
|
|
|
1809 (clobber (reg:DI ARCV2_ACC))]
|
|
|
1810 "TARGET_PLUS_MACD"
|
|
|
1811 "vmac2hu%? %0, %1, %2"
|
|
|
1812 [(set_attr "length" "4")
|
|
|
1813 (set_attr "type" "multi")
|
|
|
1814 (set_attr "predicable" "yes,no")
|
|
|
1815 (set_attr "cond" "canuse,nocond")])
|
|
|
1816
|
|
|
1817 (define_insn "vmpy2h"
|
|
|
1818 [(set (match_operand:V2SI 0 "even_register_operand" "=r,r")
|
|
|
1819 (unspec:V2SI [(match_operand:V2HI 1 "register_operand" "0,r")
|
|
|
1820 (match_operand:V2HI 2 "register_operand" "r,r")]
|
|
|
1821 UNSPEC_ARC_VMPY2H))
|
|
|
1822 (clobber (reg:DI ARCV2_ACC))]
|
|
|
1823 "TARGET_PLUS_MACD"
|
|
|
1824 "vmpy2h%? %0, %1, %2"
|
|
|
1825 [(set_attr "length" "4")
|
|
|
1826 (set_attr "type" "multi")
|
|
|
1827 (set_attr "predicable" "yes,no")
|
|
|
1828 (set_attr "cond" "canuse,nocond")])
|
|
|
1829
|
|
|
1830 (define_insn "vmpy2hu"
|
|
|
1831 [(set (match_operand:V2SI 0 "even_register_operand" "=r,r")
|
|
|
1832 (unspec:V2SI [(match_operand:V2HI 1 "register_operand" "0,r")
|
|
|
1833 (match_operand:V2HI 2 "register_operand" "r,r")]
|
|
|
1834 UNSPEC_ARC_VMPY2HU))
|
|
|
1835 (clobber (reg:DI ARCV2_ACC))]
|
|
|
1836 "TARGET_PLUS_MACD"
|
|
|
1837 "vmpy2hu%? %0, %1, %2"
|
|
|
1838 [(set_attr "length" "4")
|
|
|
1839 (set_attr "type" "multi")
|
|
|
1840 (set_attr "predicable" "yes,no")
|
|
|
1841 (set_attr "cond" "canuse,nocond")])
|
|
|
1842
|
|
|
1843 (define_insn "qmach"
|
|
|
1844 [(set (match_operand:DI 0 "even_register_operand" "=r,r")
|
|
|
1845 (unspec:DI [(match_operand:V4HI 1 "even_register_operand" "0,r")
|
|
|
1846 (match_operand:V4HI 2 "even_register_operand" "r,r")
|
|
|
1847 (reg:DI ARCV2_ACC)]
|
|
|
1848 UNSPEC_ARC_QMACH))
|
|
|
1849 (clobber (reg:DI ARCV2_ACC))]
|
|
|
1850 "TARGET_PLUS_QMACW"
|
|
|
1851 "qmach%? %0, %1, %2"
|
|
|
1852 [(set_attr "length" "4")
|
|
|
1853 (set_attr "type" "multi")
|
|
|
1854 (set_attr "predicable" "yes,no")
|
|
|
1855 (set_attr "cond" "canuse,nocond")])
|
|
|
1856
|
|
|
1857 (define_insn "qmachu"
|
|
|
1858 [(set (match_operand:DI 0 "even_register_operand" "=r,r")
|
|
|
1859 (unspec:DI [(match_operand:V4HI 1 "even_register_operand" "0,r")
|
|
|
1860 (match_operand:V4HI 2 "even_register_operand" "r,r")
|
|
|
1861 (reg:DI ARCV2_ACC)]
|
|
|
1862 UNSPEC_ARC_QMACHU))
|
|
|
1863 (clobber (reg:DI ARCV2_ACC))]
|
|
|
1864 "TARGET_PLUS_QMACW"
|
|
|
1865 "qmachu%? %0, %1, %2"
|
|
|
1866 [(set_attr "length" "4")
|
|
|
1867 (set_attr "type" "multi")
|
|
|
1868 (set_attr "predicable" "yes,no")
|
|
|
1869 (set_attr "cond" "canuse,nocond")])
|
|
|
1870
|
|
|
1871 (define_insn "qmpyh"
|
|
|
1872 [(set (match_operand:DI 0 "even_register_operand" "=r,r")
|
|
|
1873 (unspec:DI [(match_operand:V4HI 1 "even_register_operand" "0,r")
|
|
|
1874 (match_operand:V4HI 2 "even_register_operand" "r,r")]
|
|
|
1875 UNSPEC_ARC_QMPYH))
|
|
|
1876 (clobber (reg:DI ARCV2_ACC))]
|
|
|
1877 "TARGET_PLUS_QMACW"
|
|
|
1878 "qmpyh%? %0, %1, %2"
|
|
|
1879 [(set_attr "length" "4")
|
|
|
1880 (set_attr "type" "multi")
|
|
|
1881 (set_attr "predicable" "yes,no")
|
|
|
1882 (set_attr "cond" "canuse,nocond")])
|
|
|
1883
|
|
|
1884 (define_insn "qmpyhu"
|
|
|
1885 [(set (match_operand:DI 0 "even_register_operand" "=r,r")
|
|
|
1886 (unspec:DI [(match_operand:V4HI 1 "even_register_operand" "0,r")
|
|
|
1887 (match_operand:V4HI 2 "even_register_operand" "r,r")]
|
|
|
1888 UNSPEC_ARC_QMPYHU))
|
|
|
1889 (clobber (reg:DI ARCV2_ACC))]
|
|
|
1890 "TARGET_PLUS_QMACW"
|
|
|
1891 "qmpyhu%? %0, %1, %2"
|
|
|
1892 [(set_attr "length" "4")
|
|
|
1893 (set_attr "type" "multi")
|
|
|
1894 (set_attr "predicable" "yes,no")
|
|
|
1895 (set_attr "cond" "canuse,nocond")])
|
