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annotate gcc/config/arm/constraints.md @ 145:1830386684a0

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gcc-9.2.0
author anatofuz
date Thu, 13 Feb 2020 11:34:05 +0900
parents 84e7813d76e9
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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1 ;; Constraint definitions for ARM and Thumb
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2 ;; Copyright (C) 2006-2020 Free Software Foundation, Inc.
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3 ;; Contributed by ARM Ltd.
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4
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5 ;; This file is part of GCC.
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6
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7 ;; GCC is free software; you can redistribute it and/or modify it
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8 ;; under the terms of the GNU General Public License as published
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9 ;; by the Free Software Foundation; either version 3, or (at your
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10 ;; option) any later version.
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11
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12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
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13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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15 ;; License for more details.
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17 ;; You should have received a copy of the GNU General Public License
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18 ;; along with GCC; see the file COPYING3. If not see
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19 ;; <http://www.gnu.org/licenses/>.
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20
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21 ;; The following register constraints have been used:
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22 ;; - in ARM/Thumb-2 state: t, w, x, y, z
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23 ;; - in Thumb state: h, b
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24 ;; - in both states: l, c, k, q, Cs, Ts, US
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25 ;; In ARM state, 'l' is an alias for 'r'
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26 ;; 'f' and 'v' were previously used for FPA and MAVERICK registers.
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28 ;; The following normal constraints have been used:
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29 ;; in ARM/Thumb-2 state: G, I, j, J, K, L, M
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30 ;; in Thumb-1 state: I, J, K, L, M, N, O
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31 ;; 'H' was previously used for FPA.
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32
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33 ;; The following multi-letter normal constraints have been used:
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34 ;; in ARM/Thumb-2 state: Da, Db, Dc, Dd, Dn, DN, Dm, Dl, DL, Do, Dv, Dy, Di,
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35 ;; Dt, Dp, Dz, Tu
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36 ;; in Thumb-1 state: Pa, Pb, Pc, Pd, Pe
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37 ;; in Thumb-2 state: Ha, Pj, PJ, Ps, Pt, Pu, Pv, Pw, Px, Py, Pz
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38 ;; in all states: Pf, Pg
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39
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40 ;; The following memory constraints have been used:
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41 ;; in ARM/Thumb-2 state: Uh, Ut, Uv, Uy, Un, Um, Us
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42 ;; in ARM state: Uq
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43 ;; in Thumb state: Uu, Uw
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44 ;; in all states: Q
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45
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46
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47 (define_register_constraint "t" "TARGET_32BIT ? VFP_LO_REGS : NO_REGS"
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48 "The VFP registers @code{s0}-@code{s31}.")
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49
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50 (define_register_constraint "w"
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51 "TARGET_32BIT ? (TARGET_VFPD32 ? VFP_REGS : VFP_LO_REGS) : NO_REGS"
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52 "The VFP registers @code{d0}-@code{d15}, or @code{d0}-@code{d31} for VFPv3.")
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53
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54 (define_register_constraint "x" "TARGET_32BIT ? VFP_D0_D7_REGS : NO_REGS"
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55 "The VFP registers @code{d0}-@code{d7}.")
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57 (define_register_constraint "y" "TARGET_REALLY_IWMMXT ? IWMMXT_REGS : NO_REGS"
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58 "The Intel iWMMX co-processor registers.")
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59
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60 (define_register_constraint "z"
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61 "TARGET_REALLY_IWMMXT ? IWMMXT_GR_REGS : NO_REGS"
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62 "The Intel iWMMX GR registers.")
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63
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64 (define_register_constraint "l" "TARGET_THUMB ? LO_REGS : GENERAL_REGS"
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65 "In Thumb state the core registers @code{r0}-@code{r7}.")
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66
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67 (define_register_constraint "h" "TARGET_THUMB ? HI_REGS : NO_REGS"
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68 "In Thumb state the core registers @code{r8}-@code{r15}.")
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69
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70 (define_constraint "j"
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71 "A constant suitable for a MOVW instruction. (ARM/Thumb-2)"
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72 (and (match_test "TARGET_HAVE_MOVT")
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73 (ior (and (match_code "high")
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74 (match_test "arm_valid_symbolic_address_p (XEXP (op, 0))"))
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75 (and (match_code "const_int")
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76 (match_test "(ival & 0xffff0000) == 0")))))
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78 (define_constraint "Pj"
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79 "@internal A 12-bit constant suitable for an ADDW or SUBW instruction. (Thumb-2)"
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80 (and (match_code "const_int")
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81 (and (match_test "TARGET_THUMB2")
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82 (match_test "(ival & 0xfffff000) == 0"))))
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83
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84 (define_constraint "PJ"
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85 "@internal A constant that satisfies the Pj constrant if negated."
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86 (and (match_code "const_int")
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87 (and (match_test "TARGET_THUMB2")
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88 (match_test "((-ival) & 0xfffff000) == 0"))))
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89
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90 (define_register_constraint "k" "STACK_REG"
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91 "@internal The stack register.")
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92
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93 (define_register_constraint "b" "TARGET_THUMB ? BASE_REGS : NO_REGS"
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94 "@internal
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95 Thumb only. The union of the low registers and the stack register.")
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96
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97 (define_constraint "c"
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98 "@internal The condition code register."
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99 (match_operand 0 "cc_register"))
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100
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101 (define_register_constraint "Cs" "CALLER_SAVE_REGS"
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102 "@internal The caller save registers. Useful for sibcalls.")
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103
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104 (define_constraint "I"
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105 "In ARM/Thumb-2 state a constant that can be used as an immediate value in a
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106 Data Processing instruction. In Thumb-1 state a constant in the range
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107 0-255."
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108 (and (match_code "const_int")
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109 (match_test "TARGET_32BIT ? const_ok_for_arm (ival)
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110 : ival >= 0 && ival <= 255")))
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111
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112 (define_constraint "J"
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113 "In ARM/Thumb-2 state a constant in the range @minus{}4095-4095. In Thumb-1
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114 state a constant in the range @minus{}255-@minus{}1."
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115 (and (match_code "const_int")
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116 (match_test "TARGET_32BIT ? (ival >= -4095 && ival <= 4095)
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117 : (ival >= -255 && ival <= -1)")))
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118
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119 (define_constraint "K"
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120 "In ARM/Thumb-2 state a constant that satisfies the @code{I} constraint if
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121 inverted. In Thumb-1 state a constant that satisfies the @code{I}
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122 constraint multiplied by any power of 2."
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123 (and (match_code "const_int")
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124 (match_test "TARGET_32BIT ? const_ok_for_arm (~ival)
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125 : thumb_shiftable_const (ival)")))
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126
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127 (define_constraint "L"
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128 "In ARM/Thumb-2 state a constant that satisfies the @code{I} constraint if
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129 negated. In Thumb-1 state a constant in the range @minus{}7-7."
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130 (and (match_code "const_int")
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131 (match_test "TARGET_32BIT ? const_ok_for_arm (-ival)
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132 : (ival >= -7 && ival <= 7)")))
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133
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134 ;; The ARM state version is internal...
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135 ;; @internal In ARM/Thumb-2 state a constant in the range 0-32 or any
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136 ;; power of 2.
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137 (define_constraint "M"
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138 "In Thumb-1 state a constant that is a multiple of 4 in the range 0-1020."
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139 (and (match_code "const_int")
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140 (match_test "TARGET_32BIT ? ((ival >= 0 && ival <= 32)
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141 || (((ival & (ival - 1)) & 0xFFFFFFFF) == 0))
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142 : ival >= 0 && ival <= 1020 && (ival & 3) == 0")))
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143
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144 (define_constraint "N"
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145 "Thumb-1 state a constant in the range 0-31."
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146 (and (match_code "const_int")
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147 (match_test "!TARGET_32BIT && (ival >= 0 && ival <= 31)")))
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148
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149 (define_constraint "O"
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150 "In Thumb-1 state a constant that is a multiple of 4 in the range
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151 @minus{}508-508."
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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152 (and (match_code "const_int")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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153 (match_test "TARGET_THUMB1 && ival >= -508 && ival <= 508
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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154 && ((ival & 3) == 0)")))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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155
55
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ryoma <e075725@ie.u-ryukyu.ac.jp>
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156 (define_constraint "Pa"
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
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157 "@internal In Thumb-1 state a constant in the range -510 to +510"
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
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158 (and (match_code "const_int")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
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159 (match_test "TARGET_THUMB1 && ival >= -510 && ival <= 510
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
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160 && (ival > 255 || ival < -255)")))
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
161
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
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162 (define_constraint "Pb"
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
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163 "@internal In Thumb-1 state a constant in the range -262 to +262"
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
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164 (and (match_code "const_int")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
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165 (match_test "TARGET_THUMB1 && ival >= -262 && ival <= 262
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
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166 && (ival > 255 || ival < -255)")))
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
167
67
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168 (define_constraint "Pc"
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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169 "@internal In Thumb-1 state a constant that is in the range 1021 to 1275"
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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170 (and (match_code "const_int")
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents: 55
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171 (match_test "TARGET_THUMB1
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents: 55
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172 && ival > 1020 && ival <= 1275")))
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173
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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174 (define_constraint "Pd"
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kono
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175 "@internal In Thumb state a constant in the range 0 to 7"
kono
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176 (and (match_code "const_int")
kono
parents: 67
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177 (match_test "TARGET_THUMB && ival >= 0 && ival <= 7")))
kono
parents: 67
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178
kono
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179 (define_constraint "Pe"
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180 "@internal In Thumb-1 state a constant in the range 256 to +510"
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181 (and (match_code "const_int")
111
kono
parents: 67
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182 (match_test "TARGET_THUMB1 && ival >= 256 && ival <= 510")))
kono
parents: 67
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183
kono
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184 (define_constraint "Pf"
kono
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185 "Memory models except relaxed, consume or release ones."
kono
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186 (and (match_code "const_int")
kono
parents: 67
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187 (match_test "!is_mm_relaxed (memmodel_from_int (ival))
kono
parents: 67
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188 && !is_mm_consume (memmodel_from_int (ival))
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parents: 67
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189 && !is_mm_release (memmodel_from_int (ival))")))
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190
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191 (define_constraint "Pg"
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192 "@internal In Thumb-2 state a constant in range 1 to 32"
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parents: 131
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193 (and (match_code "const_int")
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parents: 131
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194 (match_test "TARGET_THUMB2 && ival >= 1 && ival <= 32")))
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parents: 131
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195
55
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
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196 (define_constraint "Ps"
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
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197 "@internal In Thumb-2 state a constant in the range -255 to +255"
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
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198 (and (match_code "const_int")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
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199 (match_test "TARGET_THUMB2 && ival >= -255 && ival <= 255")))
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
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200
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
201 (define_constraint "Pt"
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
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202 "@internal In Thumb-2 state a constant in the range -7 to +7"
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
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203 (and (match_code "const_int")
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
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204 (match_test "TARGET_THUMB2 && ival >= -7 && ival <= 7")))
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
205
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206 (define_constraint "Pu"
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents: 55
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207 "@internal In Thumb-2 state a constant in the range +1 to +8"
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents: 55
diff changeset
208 (and (match_code "const_int")
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents: 55
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209 (match_test "TARGET_THUMB2 && ival >= 1 && ival <= 8")))
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents: 55
diff changeset
210
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents: 55
diff changeset
211 (define_constraint "Pv"
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents: 55
diff changeset
212 "@internal In Thumb-2 state a constant in the range -255 to 0"
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents: 55
diff changeset
213 (and (match_code "const_int")
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents: 55
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214 (match_test "TARGET_THUMB2 && ival >= -255 && ival <= 0")))
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents: 55
diff changeset
215
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents: 55
diff changeset
216 (define_constraint "Pw"
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents: 55
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217 "@internal In Thumb-2 state a constant in the range -255 to -1"
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents: 55
diff changeset
218 (and (match_code "const_int")
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents: 55
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219 (match_test "TARGET_THUMB2 && ival >= -255 && ival <= -1")))
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents: 55
diff changeset
220
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents: 55
diff changeset
221 (define_constraint "Px"
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents: 55
diff changeset
222 "@internal In Thumb-2 state a constant in the range -7 to -1"
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents: 55
diff changeset
223 (and (match_code "const_int")
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents: 55
diff changeset
224 (match_test "TARGET_THUMB2 && ival >= -7 && ival <= -1")))
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents: 55
diff changeset
225
111
kono
parents: 67
diff changeset
226 (define_constraint "Py"
kono
parents: 67
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227 "@internal In Thumb-2 state a constant in the range 0 to 255"
kono
parents: 67
diff changeset
228 (and (match_code "const_int")
kono
parents: 67
diff changeset
229 (match_test "TARGET_THUMB2 && ival >= 0 && ival <= 255")))
kono
parents: 67
diff changeset
230
kono
parents: 67
diff changeset
231 (define_constraint "Pz"
kono
parents: 67
diff changeset
232 "@internal In Thumb-2 state the constant 0"
kono
parents: 67
diff changeset
233 (and (match_code "const_int")
kono
parents: 67
diff changeset
234 (match_test "TARGET_THUMB2 && (ival == 0)")))
kono
parents: 67
diff changeset
235
0
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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236 (define_constraint "G"
111
kono
parents: 67
diff changeset
237 "In ARM/Thumb-2 state the floating-point constant 0."
0
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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238 (and (match_code "const_double")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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239 (match_test "TARGET_32BIT && arm_const_double_rtx (op)")))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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240
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parents: 131
diff changeset
241 (define_constraint "Ha"
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parents: 131
diff changeset
242 "@internal In ARM / Thumb-2 a float constant iff literal pools are allowed."
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parents: 131
diff changeset
243 (and (match_code "const_double")
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parents: 131
diff changeset
244 (match_test "satisfies_constraint_E (op)")
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parents: 131
diff changeset
245 (match_test "!arm_disable_literal_pool")))
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parents: 131
diff changeset
246
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247 (define_constraint "Dz"
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248 "@internal
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249 In ARM/Thumb-2 state a vector of constant zeros."
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents: 55
diff changeset
250 (and (match_code "const_vector")
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents: 55
diff changeset
251 (match_test "TARGET_NEON && op == CONST0_RTX (mode)")))
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents: 55
diff changeset
252
0
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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253 (define_constraint "Da"
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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254 "@internal
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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255 In ARM/Thumb-2 state a const_int, const_double or const_vector that can
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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256 be generated with two Data Processing insns."
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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257 (and (match_code "const_double,const_int,const_vector")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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258 (match_test "TARGET_32BIT && arm_const_double_inline_cost (op) == 2")))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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259
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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260 (define_constraint "Db"
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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261 "@internal
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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262 In ARM/Thumb-2 state a const_int, const_double or const_vector that can
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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263 be generated with three Data Processing insns."
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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264 (and (match_code "const_double,const_int,const_vector")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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265 (match_test "TARGET_32BIT && arm_const_double_inline_cost (op) == 3")))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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266
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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267 (define_constraint "Dc"
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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268 "@internal
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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269 In ARM/Thumb-2 state a const_int, const_double or const_vector that can
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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270 be generated with four Data Processing insns. This pattern is disabled
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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271 if optimizing for space or when we have load-delay slots to fill."
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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272 (and (match_code "const_double,const_int,const_vector")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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273 (match_test "TARGET_32BIT && arm_const_double_inline_cost (op) == 4
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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274 && !(optimize_size || arm_ld_sched)")))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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275
111
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parents: 67
diff changeset
276 (define_constraint "Dd"
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parents: 67
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277 "@internal
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parents: 67
diff changeset
278 In ARM/Thumb-2 state a const_int that can be used by insn adddi."
kono
parents: 67
diff changeset
279 (and (match_code "const_int")
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parents: 67
diff changeset
280 (match_test "TARGET_32BIT && const_ok_for_dimode_op (ival, PLUS)")))
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parents: 67
diff changeset
281
67
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diff changeset
282 (define_constraint "Di"
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diff changeset
283 "@internal
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284 In ARM/Thumb-2 state a const_int or const_double where both the high
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
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diff changeset
285 and low SImode words can be generated as immediates in 32-bit instructions."
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parents: 55
diff changeset
286 (and (match_code "const_double,const_int")
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents: 55
diff changeset
287 (match_test "TARGET_32BIT && arm_const_double_by_immediates (op)")))
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nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents: 55
diff changeset
288
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parents: 131
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289 (define_constraint "Dm"
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290 "@internal
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parents: 131
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291 In ARM/Thumb-2 state a const_vector which can be loaded with a Neon vmov
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parents: 131
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292 immediate instruction."
1830386684a0 gcc-9.2.0
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parents: 131
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293 (and (match_code "const_vector")
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parents: 131
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294 (match_test "TARGET_32BIT
1830386684a0 gcc-9.2.0
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parents: 131
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295 && imm_for_neon_mov_operand (op, GET_MODE (op))")))
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parents: 131
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296
0
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297 (define_constraint "Dn"
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298 "@internal
145
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299 In ARM/Thumb-2 state a DImode const_int which can be loaded with a Neon vmov
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parents: 131
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300 immediate instruction."
1830386684a0 gcc-9.2.0
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parents: 131
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301 (and (match_code "const_int")
1830386684a0 gcc-9.2.0
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parents: 131
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302 (match_test "TARGET_32BIT && imm_for_neon_mov_operand (op, DImode)")))
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parents: 131
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303
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304 (define_constraint "DN"
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305 "@internal
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306 In ARM/Thumb-2 state a TImode const_int which can be loaded with a Neon vmov
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parents: 131
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307 immediate instruction."
1830386684a0 gcc-9.2.0
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parents: 131
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308 (and (match_code "const_int")
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parents: 131
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309 (match_test "TARGET_32BIT && imm_for_neon_mov_operand (op, TImode)")))
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310
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311 (define_constraint "Dl"
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312 "@internal
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313 In ARM/Thumb-2 state a const_vector which can be used with a Neon vorr or
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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314 vbic instruction."
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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315 (and (match_code "const_vector")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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316 (match_test "TARGET_32BIT
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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317 && imm_for_neon_logic_operand (op, GET_MODE (op))")))
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318
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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319 (define_constraint "DL"
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320 "@internal
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321 In ARM/Thumb-2 state a const_vector which can be used with a Neon vorn or
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322 vand instruction."
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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323 (and (match_code "const_vector")
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324 (match_test "TARGET_32BIT
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325 && imm_for_neon_inv_logic_operand (op, GET_MODE (op))")))
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326
111
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327 (define_constraint "Do"
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328 "@internal
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329 In ARM/Thumb2 state valid offset for an ldrd/strd instruction."
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330 (and (match_code "const_int")
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331 (match_test "TARGET_LDRD && offset_ok_for_ldrd_strd (ival)")))
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332
0
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333 (define_constraint "Dv"
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334 "@internal
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335 In ARM/Thumb-2 state a const_double which can be used with a VFP fconsts
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336 instruction."
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337 (and (match_code "const_double")
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338 (match_test "TARGET_32BIT && vfp3_const_double_rtx (op)")))
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339
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340 (define_constraint "Dy"
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341 "@internal
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342 In ARM/Thumb-2 state a const_double which can be used with a VFP fconstd
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343 instruction."
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344 (and (match_code "const_double")
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345 (match_test "TARGET_32BIT && TARGET_VFP_DOUBLE && vfp3_const_double_rtx (op)")))
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346
111
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347 (define_constraint "Dt"
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348 "@internal
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349 In ARM/ Thumb2 a const_double which can be used with a vcvt.f32.s32 with fract bits operation"
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350 (and (match_code "const_double")
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351 (match_test "TARGET_32BIT && vfp3_const_double_for_fract_bits (op)")))
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352
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353 (define_constraint "Dp"
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354 "@internal
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355 In ARM/ Thumb2 a const_double which can be used with a vcvt.s32.f32 with bits operation"
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356 (and (match_code "const_double")
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357 (match_test "TARGET_32BIT
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358 && vfp3_const_double_for_bits (op) > 0")))
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359
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parents: 131
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360 (define_constraint "Tu"
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361 "@internal In ARM / Thumb-2 an integer constant iff literal pools are
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parents: 131
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362 allowed."
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parents: 131
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363 (and (match_test "CONSTANT_P (op)")
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parents: 131
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364 (match_test "!arm_disable_literal_pool")))
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parents: 131
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365
111
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366 (define_register_constraint "Ts" "(arm_restrict_it) ? LO_REGS : GENERAL_REGS"
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367 "For arm_restrict_it the core registers @code{r0}-@code{r7}. GENERAL_REGS otherwise.")
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368
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369 (define_memory_constraint "Ua"
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370 "@internal
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371 An address valid for loading/storing register exclusive"
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372 (match_operand 0 "mem_noofs_operand"))
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373
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374 (define_memory_constraint "Uh"
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375 "@internal
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376 An address suitable for byte and half-word loads which does not point inside a constant pool"
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377 (and (match_code "mem")
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378 (match_test "arm_legitimate_address_p (GET_MODE (op), XEXP (op, 0), false) && !arm_is_constant_pool_ref (op)")))
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379
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380 (define_memory_constraint "Ut"
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381 "@internal
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382 In ARM/Thumb-2 state an address valid for loading/storing opaque structure
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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383 types wider than TImode."
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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384 (and (match_code "mem")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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385 (match_test "TARGET_32BIT && neon_struct_mem_operand (op)")))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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386
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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387 (define_memory_constraint "Uv"
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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388 "@internal
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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389 In ARM/Thumb-2 state a valid VFP load/store address."
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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390 (and (match_code "mem")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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391 (match_test "TARGET_32BIT && arm_coproc_mem_operand (op, FALSE)")))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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392
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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393 (define_memory_constraint "Uy"
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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394 "@internal
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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395 In ARM/Thumb-2 state a valid iWMMX load/store address."
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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396 (and (match_code "mem")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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397 (match_test "TARGET_32BIT && arm_coproc_mem_operand (op, TRUE)")))
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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398
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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399 (define_memory_constraint "Un"
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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400 "@internal
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parents: 0
diff changeset
401 In ARM/Thumb-2 state a valid address for Neon doubleword vector
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
402 load/store instructions."
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parents: 0
diff changeset
403 (and (match_code "mem")
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404 (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 0, true)")))
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
405
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
406 (define_memory_constraint "Um"
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
407 "@internal
0
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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408 In ARM/Thumb-2 state a valid address for Neon element and structure
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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409 load/store instructions."
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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410 (and (match_code "mem")
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411 (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 2, true)")))
0
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412
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
413 (define_memory_constraint "Us"
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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414 "@internal
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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415 In ARM/Thumb-2 state a valid address for non-offset loads/stores of
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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416 quad-word values in four ARM registers."
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417 (and (match_code "mem")
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418 (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 1, true)")))
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419
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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420 (define_memory_constraint "Uq"
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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421 "@internal
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422 In ARM state an address valid in ldrsb instructions."
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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423 (and (match_code "mem")
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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424 (match_test "TARGET_ARM
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425 && arm_legitimate_address_outer_p (GET_MODE (op), XEXP (op, 0),
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426 SIGN_EXTEND, 0)
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427 && !arm_is_constant_pool_ref (op)")))
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428
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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429 (define_memory_constraint "Q"
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430 "@internal
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431 An address that is a single base register."
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432 (and (match_code "mem")
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433 (match_test "REG_P (XEXP (op, 0))")))
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434
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435 (define_memory_constraint "Uu"
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436 "@internal
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437 In Thumb state an address that is valid in 16bit encoding."
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438 (and (match_code "mem")
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439 (match_test "TARGET_THUMB
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440 && thumb1_legitimate_address_p (GET_MODE (op), XEXP (op, 0),
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441 0)")))
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442
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443 ; The 16-bit post-increment LDR/STR accepted by thumb1_legitimate_address_p
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444 ; are actually LDM/STM instructions, so cannot be used to access unaligned
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445 ; data.
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446 (define_memory_constraint "Uw"
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447 "@internal
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448 In Thumb state an address that is valid in 16bit encoding, and that can be
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449 used for unaligned accesses."
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450 (and (match_code "mem")
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451 (match_test "TARGET_THUMB
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452 && thumb1_legitimate_address_p (GET_MODE (op), XEXP (op, 0),
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453 0)
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454 && GET_CODE (XEXP (op, 0)) != POST_INC")))
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455
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456 (define_constraint "US"
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457 "@internal
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458 US is a symbol reference."
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459 (match_code "symbol_ref")
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460 )
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461
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462 (define_memory_constraint "Uz"
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463 "@internal
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464 A memory access that is accessible as an LDC/STC operand"
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465 (and (match_code "mem")
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466 (match_test "arm_coproc_ldc_stc_legitimate_address (op)")))
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diff changeset
467
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468 ;; We used to have constraint letters for S and R in ARM state, but
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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469 ;; all uses of these now appear to have been removed.
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470
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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471 ;; Additionally, we used to have a Q constraint in Thumb state, but
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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472 ;; this wasn't really a valid memory constraint. Again, all uses of
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
473 ;; this now seem to have been removed.
111
kono
parents: 67
diff changeset
474