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1 ;; ARM Cortex-M7 pipeline description
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2 ;; Copyright (C) 2014-2020 Free Software Foundation, Inc.
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3 ;;
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4 ;; This file is part of GCC.
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5 ;;
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6 ;; GCC is free software; you can redistribute it and/or modify it
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7 ;; under the terms of the GNU General Public License as published by
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8 ;; the Free Software Foundation; either version 3, or (at your option)
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9 ;; any later version.
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10 ;;
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11 ;; GCC is distributed in the hope that it will be useful, but
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12 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
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13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 ;; General Public License for more details.
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15 ;;
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16 ;; You should have received a copy of the GNU General Public License
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17 ;; along with GCC; see the file COPYING3. If not see
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18 ;; <http://www.gnu.org/licenses/>.
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19
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20 (define_automaton "cortex_m7")
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21
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22 ;; We model the dual-issue constraints of this core with
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23 ;; following units.
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24
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25 (define_cpu_unit "cm7_i0, cm7_i1" "cortex_m7")
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26 (define_cpu_unit "cm7_a0, cm7_a1" "cortex_m7")
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27 (define_cpu_unit "cm7_branch,cm7_wb,cm7_ext,cm7_shf" "cortex_m7")
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28 (define_cpu_unit "cm7_lsu" "cortex_m7")
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29 (define_cpu_unit "cm7_mac" "cortex_m7")
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30 (define_cpu_unit "cm7_fpu" "cortex_m7")
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31
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32 (define_reservation "cm7_all_units"
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33 "cm7_i0+cm7_i1+cm7_a0+cm7_a1+cm7_branch\
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34 +cm7_wb+cm7_ext+cm7_shf+cm7_lsu+cm7_mac\
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35 +cm7_fpu")
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36
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37 ;; Simple alu instruction without inline shift operation.
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38 (define_insn_reservation "cortex_m7_alu_simple" 2
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39 (and (eq_attr "tune" "cortexm7")
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40 (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
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41 alu_sreg,alus_sreg,logic_reg,logics_reg,\
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42 adc_imm,adcs_imm,adc_reg,adcs_reg,\
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43 adr,bfm,rev,\
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44 shift_imm,shift_reg,\
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45 mov_imm,mov_reg,mvn_imm,mvn_reg,\
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46 mov_shift_reg,mov_shift,\
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47 mvn_shift,mvn_shift_reg,\
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48 logic_shift_imm,logics_shift_imm,\
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49 alu_shift_reg,alus_shift_reg,\
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50 logic_shift_reg,logics_shift_reg,\
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51 mrs,clz,f_mcr,f_mrc,multiple"))
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52 "cm7_i0|cm7_i1,cm7_a0|cm7_a1")
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53
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54 ;; Simple alu with inline shift operation.
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55 (define_insn_reservation "cortex_m7_alu_shift" 2
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56 (and (eq_attr "tune" "cortexm7")
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57 (eq_attr "type" "alu_shift_imm,alus_shift_imm"))
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58 "cm7_i0|cm7_i1,(cm7_a0|cm7_a1)+cm7_shf+cm7_branch")
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59
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60 ;; Only one ALU can be used for DSP instructions.
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61 (define_insn_reservation "cortex_m7_dsp" 2
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62 (and (eq_attr "tune" "cortexm7")
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63 (eq_attr "type" "alu_dsp_reg,smlaxy,smlalxy,smulxy"))
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64 "cm7_i0|cm7_i1,cm7_a0")
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65
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66 ;; The multiply instructions.
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67 (define_insn_reservation "cortex_m7_multiply" 2
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68 (and (eq_attr "tune" "cortexm7")
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69 (eq_attr "type" "mul,muls,umull,smull"))
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70 "cm7_i0|cm7_i1,(cm7_a0|cm7_a1)+cm7_wb")
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71
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72 (define_insn_reservation "cortex_m7_idiv" 4
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73 (and (eq_attr "tune" "cortexm7")
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74 (eq_attr "type" "sdiv,udiv"))
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75 "cm7_all_units*4")
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76
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77 (define_insn_reservation "cortex_m7_alu_extend" 2
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78 (and (eq_attr "tune" "cortexm7")
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79 (eq_attr "type" "extend"))
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80 "cm7_i0|cm7_i1,(cm7_a0|cm7_a1)+cm7_ext+cm7_branch")
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81
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82 (define_insn_reservation "cortex_m7_mac" 2
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83 (and (eq_attr "tune" "cortexm7")
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84 (eq_attr "type" "mla,mlas"))
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85 "cm7_i0|cm7_i1,cm7_mac+cm7_wb")
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86
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87 ;; The branch instructions.
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88 (define_insn_reservation "cortex_m7_branch" 0
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89 (and (eq_attr "tune" "cortexm7")
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90 (eq_attr "type" "branch,call"))
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91 "cm7_i0|cm7_i1,cm7_branch")
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92
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93 ;; The load instructions.
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94 (define_insn_reservation "cortex_m7_load1" 2
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95 (and (eq_attr "tune" "cortexm7")
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96 (eq_attr "type" "load_byte, load_4"))
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97 "cm7_i0|cm7_i1,cm7_lsu")
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98
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99 (define_insn_reservation "cortex_m7_load2" 2
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100 (and (eq_attr "tune" "cortexm7")
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101 (eq_attr "type" "load_8"))
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102 "cm7_all_units")
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103
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104 (define_insn_reservation "cortex_m7_loadm" 2
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105 (and (eq_attr "tune" "cortexm7")
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106 (eq_attr "type" "load_12,load_16"))
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107 "cm7_all_units*2")
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108
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109 ;; The store instructions.
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110 (define_insn_reservation "cortex_m7_store1" 0
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111 (and (eq_attr "tune" "cortexm7")
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112 (eq_attr "type" "store_4"))
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113 "cm7_i0|cm7_i1,cm7_lsu+cm7_wb")
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114
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115 (define_insn_reservation "cortex_m7_store2" 0
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116 (and (eq_attr "tune" "cortexm7")
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117 (eq_attr "type" "store_8"))
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118 "cm7_all_units")
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119
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120 (define_insn_reservation "cortex_m7_storem" 0
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121 (and (eq_attr "tune" "cortexm7")
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122 (eq_attr "type" "store_12,store_16"))
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123 "cm7_all_units*2")
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124
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125 ;; The FPU instructions.
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126 (define_insn_reservation "cortex_m7_fpalu" 3
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127 (and (eq_attr "tune" "cortexm7")
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128 (eq_attr "type" "ffariths,ffarithd,fadds,faddd,fmov,fconsts,\
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129 fconstd,fcmpd,f_cvt,f_cvtf2i,f_cvti2f, fcmps,\
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130 fmuls,f_flag"))
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131 "cm7_i0|cm7_i1,cm7_fpu")
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132
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133 (define_insn_reservation "cortex_m7_fmacs" 6
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134 (and (eq_attr "tune" "cortexm7")
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135 (eq_attr "type" "fmacs,ffmas"))
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136 "cm7_i0|cm7_i1,cm7_fpu")
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137
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138 (define_insn_reservation "cortex_m7_fdivs" 16
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139 (and (eq_attr "tune" "cortexm7")
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140 (eq_attr "type" "fdivs, fsqrts"))
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141 "cm7_i0|cm7_i1, cm7_fpu*5")
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142
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143 (define_insn_reservation "cortex_m7_f_loads" 2
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144 (and (eq_attr "tune" "cortexm7")
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145 (eq_attr "type" "f_loads"))
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146 "cm7_i0|cm7_i1, cm7_lsu")
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147
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148 (define_insn_reservation "cortex_m7_f_stores" 0
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149 (and (eq_attr "tune" "cortexm7")
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150 (eq_attr "type" "f_stores"))
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151 "cm7_i0|cm7_i1, cm7_lsu+cm7_wb")
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152
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153 (define_insn_reservation "cortex_m7_fmuld" 6
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154 (and (eq_attr "tune" "cortexm7")
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155 (eq_attr "type" "fmuld"))
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156 "cm7_i0|cm7_i1,cm7_fpu*3")
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157
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158 (define_insn_reservation "cortex_m7_fmacd" 10
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159 (and (eq_attr "tune" "cortexm7")
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160 (eq_attr "type" "fmacd,ffmad"))
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161 "cm7_i0|cm7_i1,cm7_fpu*4")
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162
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163 (define_insn_reservation "cortex_m7_fdivd" 31
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164 (and (eq_attr "tune" "cortexm7")
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165 (eq_attr "type" "fdivd,fsqrtd"))
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166 "cm7_i0|cm7_i1,cm7_fpu*4")
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167
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168 (define_insn_reservation "cortex_m7_f_loadd" 3
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169 (and (eq_attr "tune" "cortexm7")
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170 (eq_attr "type" "f_loadd"))
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171 "cm7_all_units")
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172
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173 (define_insn_reservation "cortex_m7_f_stored" 0
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174 (and (eq_attr "tune" "cortexm7")
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175 (eq_attr "type" "f_stored"))
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176 "cm7_all_units")
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177
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178 (define_insn_reservation "cortex_m7_f_mcr" 1
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179 (and (eq_attr "tune" "cortexm7")
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180 (eq_attr "type" "f_mcrr,f_mrrc"))
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181 "cm7_all_units")
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