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145
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1 ;; Machine description for eBPF.
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2 ;; Copyright (C) 2019-2020 Free Software Foundation, Inc.
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3
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4 ;; This file is part of GCC.
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5
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6 ;; GCC is free software; you can redistribute it and/or modify
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7 ;; it under the terms of the GNU General Public License as published by
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8 ;; the Free Software Foundation; either version 3, or (at your option)
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9 ;; any later version.
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10
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11 ;; GCC is distributed in the hope that it will be useful,
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12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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14 ;; GNU General Public License for more details.
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15
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16 ;; You should have received a copy of the GNU General Public License
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17 ;; along with GCC; see the file COPYING3. If not see
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18 ;; <http://www.gnu.org/licenses/>.
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19
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20 (include "predicates.md")
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21 (include "constraints.md")
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22
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23 ;;;; Unspecs
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24
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25 (define_c_enum "unspec" [
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26 UNSPEC_LDINDABS
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27 UNSPEC_XADD
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28 ])
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29
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30 ;;;; Constants
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31
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32 (define_constants
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33 [(R0_REGNUM 0)
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34 (R1_REGNUM 1)
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35 (R2_REGNUM 2)
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36 (R3_REGNUM 3)
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37 (R4_REGNUM 4)
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38 (R5_REGNUM 5)
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39 (R6_REGNUM 6)
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40 (R7_REGNUM 7)
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41 (R8_REGNUM 8)
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42 (R9_REGNUM 9)
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43 (R10_REGNUM 10)
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44 (R11_REGNUM 11)
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45 ])
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46
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47 ;;;; Attributes
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48
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49 ;; Instruction classes.
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50 ;; alu 64-bit arithmetic.
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51 ;; alu32 32-bit arithmetic.
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52 ;; end endianness conversion instructions.
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53 ;; ld load instructions.
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54 ;; lddx load 64-bit immediate instruction.
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55 ;; ldx generic load instructions.
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56 ;; st generic store instructions for immediates.
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57 ;; stx generic store instructions.
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58 ;; jmp jump instructions.
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59 ;; xadd atomic exchange-and-add instructions.
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60 ;; multi multiword sequence (or user asm statements).
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61
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62 (define_attr "type"
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63 "unknown,alu,alu32,end,ld,lddw,ldx,st,stx,jmp,xadd,multi"
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64 (const_string "unknown"))
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65
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66 ;; Length of instruction in bytes.
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67 (define_attr "length" ""
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68 (cond [
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69 (eq_attr "type" "lddw") (const_int 16)
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70 ] (const_int 8)))
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71
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72 ;; Describe a user's asm statement.
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73 (define_asm_attributes
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74 [(set_attr "type" "multi")])
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75
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76 ;;;; Mode attributes and iterators
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77
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78 (define_mode_attr mop [(QI "b") (HI "h") (SI "w") (DI "dw")
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79 (SF "w") (DF "dw")])
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80 (define_mode_attr mtype [(SI "alu32") (DI "alu")])
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81 (define_mode_attr msuffix [(SI "32") (DI "")])
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82
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83 ;;;; NOPs
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84
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85 (define_insn "nop"
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86 [(const_int 0)]
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87 ""
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88 "mov\t%%r0,%%r0"
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89 [(set_attr "type" "alu")])
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90
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91 ;;;; Arithmetic/Logical
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92
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93 ;; The arithmetic and logic operations below are defined for SI and DI
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94 ;; modes. The mode iterator AM is used in order to expand to two
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95 ;; insns, with the proper modes.
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96 ;;
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97 ;; 32-bit arithmetic (for SI modes) is implemented using the alu32
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98 ;; instructions.
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99
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100 (define_mode_iterator AM [SI DI])
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101
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102 ;;; Addition
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103 (define_insn "add<AM:mode>3"
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104 [(set (match_operand:AM 0 "register_operand" "=r,r")
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105 (plus:AM (match_operand:AM 1 "register_operand" " 0,0")
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106 (match_operand:AM 2 "reg_or_imm_operand" " r,I")))]
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107 "1"
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108 "add<msuffix>\t%0,%2"
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109 [(set_attr "type" "<mtype>")])
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110
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111 ;;; Subtraction
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112
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113 ;; Note that subtractions of constants become additions, so there is
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114 ;; no need to handle immediate operands in the subMODE3 insns.
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115
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116 (define_insn "sub<AM:mode>3"
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117 [(set (match_operand:AM 0 "register_operand" "=r")
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118 (minus:AM (match_operand:AM 1 "register_operand" " 0")
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119 (match_operand:AM 2 "register_operand" " r")))]
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120 ""
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121 "sub<msuffix>\t%0,%2"
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122 [(set_attr "type" "<mtype>")])
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123
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124 ;;; Negation
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125 (define_insn "neg<AM:mode>2"
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126 [(set (match_operand:AM 0 "register_operand" "=r")
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127 (neg:AM (match_operand:AM 1 "register_operand" " 0")))]
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128 ""
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129 "neg<msuffix>\t%0"
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130 [(set_attr "type" "<mtype>")])
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131
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132 ;;; Multiplication
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133 (define_insn "mul<AM:mode>3"
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134 [(set (match_operand:AM 0 "register_operand" "=r,r")
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135 (mult:AM (match_operand:AM 1 "register_operand" " 0,0")
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136 (match_operand:AM 2 "reg_or_imm_operand" " r,I")))]
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137 ""
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138 "mul<msuffix>\t%0,%2"
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139 [(set_attr "type" "<mtype>")])
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140
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141 (define_insn "*mulsidi3_zeroextend"
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142 [(set (match_operand:DI 0 "register_operand" "=r,r")
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143 (zero_extend:DI
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144 (mult:SI (match_operand:SI 1 "register_operand" "0,0")
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145 (match_operand:SI 2 "reg_or_imm_operand" "r,I"))))]
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146 ""
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147 "mul32\t%0,%2"
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148 [(set_attr "type" "alu32")])
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149
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150 ;;; Division
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151
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152 ;; Note that eBPF doesn't provide instructions for signed integer
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153 ;; division.
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154
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155 (define_insn "udiv<AM:mode>3"
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156 [(set (match_operand:AM 0 "register_operand" "=r,r")
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157 (udiv:AM (match_operand:AM 1 "register_operand" " 0,0")
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158 (match_operand:AM 2 "reg_or_imm_operand" "r,I")))]
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159 ""
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160 "div<msuffix>\t%0,%2"
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161 [(set_attr "type" "<mtype>")])
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162
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163 ;;; Modulus
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164
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165 ;; Note that eBPF doesn't provide instructions for signed integer
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166 ;; remainder.
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167
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168 (define_insn "umod<AM:mode>3"
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169 [(set (match_operand:AM 0 "register_operand" "=r,r")
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170 (umod:AM (match_operand:AM 1 "register_operand" " 0,0")
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171 (match_operand:AM 2 "reg_or_imm_operand" "r,I")))]
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172 ""
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173 "mod<msuffix>\t%0,%2"
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174 [(set_attr "type" "<mtype>")])
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175
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176 ;;; Logical AND
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177 (define_insn "and<AM:mode>3"
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178 [(set (match_operand:AM 0 "register_operand" "=r,r")
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179 (and:AM (match_operand:AM 1 "register_operand" " 0,0")
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180 (match_operand:AM 2 "reg_or_imm_operand" "r,I")))]
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181 ""
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182 "and<msuffix>\t%0,%2"
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183 [(set_attr "type" "<mtype>")])
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184
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185 ;;; Logical inclusive-OR
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186 (define_insn "ior<AM:mode>3"
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187 [(set (match_operand:AM 0 "register_operand" "=r,r")
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188 (ior:AM (match_operand:AM 1 "register_operand" " 0,0")
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189 (match_operand:AM 2 "reg_or_imm_operand" "r,I")))]
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190 ""
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191 "or<msuffix>\t%0,%2"
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192 [(set_attr "type" "<mtype>")])
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193
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194 ;;; Logical exclusive-OR
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195 (define_insn "xor<AM:mode>3"
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196 [(set (match_operand:AM 0 "register_operand" "=r,r")
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197 (xor:AM (match_operand:AM 1 "register_operand" " 0,0")
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198 (match_operand:AM 2 "reg_or_imm_operand" "r,I")))]
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199 ""
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200 "xor<msuffix>\t%0,%2"
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201 [(set_attr "type" "<mtype>")])
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202
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203 ;;;; Conversions
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204
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205 ;;; Zero-extensions
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206
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207 ;; For register operands smaller than 32-bit zero-extending is
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208 ;; achieved ANDing the value in the source register to a suitable
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209 ;; mask.
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210 ;;
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211 ;; For register operands bigger or equal than 32-bit, we generate a
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212 ;; mov32 instruction to zero the high 32-bits of the destination
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213 ;; register.
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214 ;;
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215 ;; For memory operands, of any width, zero-extending is achieved using
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216 ;; the ldx{bhwdw} instructions to load the values in registers.
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217
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218 (define_insn "zero_extendhidi2"
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219 [(set (match_operand:DI 0 "register_operand" "=r,r")
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220 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
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221 ""
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222 "@
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223 and\t%0,0xffff
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224 ldxh\t%0,%1"
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225 [(set_attr "type" "alu,ldx")])
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226
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227 (define_insn "zero_extendqidi2"
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228 [(set (match_operand:DI 0 "register_operand" "=r,r")
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229 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
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230 ""
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231 "@
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232 and\t%0,0xff
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233 ldxb\t%0,%1"
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234 [(set_attr "type" "alu,ldx")])
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235
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236 (define_insn "zero_extendsidi2"
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237 [(set (match_operand:DI 0 "register_operand" "=r,r")
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238 (zero_extend:DI
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239 (match_operand:SI 1 "nonimmediate_operand" "r,m")))]
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240 ""
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241 "@
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242 mov32\t%0,%1
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243 ldxw\t%0,%1"
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244 [(set_attr "type" "alu,ldx")])
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245
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246 ;;; Sign-extension
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247
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248 ;; Sign-extending a 32-bit value into a 64-bit value is achieved using
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249 ;; shifting, with instructions generated by the expand below.
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250
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251 (define_expand "extendsidi2"
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252 [(set (match_operand:DI 0 "register_operand")
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253 (sign_extend:DI (match_operand:SI 1 "register_operand")))]
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254 ""
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255 {
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256 operands[1] = gen_lowpart (DImode, operands[1]);
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257 emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (32)));
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258 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32)));
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259 DONE;
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260 })
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261
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262 ;;;; Data movement
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263
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264 (define_mode_iterator MM [QI HI SI DI SF DF])
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265
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266 (define_expand "mov<MM:mode>"
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267 [(set (match_operand:MM 0 "general_operand")
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268 (match_operand:MM 1 "general_operand"))]
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269 ""
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270 "
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271 {
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272 if (!register_operand(operands[0], <MM:MODE>mode)
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273 && !register_operand(operands[1], <MM:MODE>mode))
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274 operands[1] = force_reg (<MM:MODE>mode, operands[1]);
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275 }")
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276
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277 (define_insn "*mov<MM:mode>"
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278 [(set (match_operand:MM 0 "nonimmediate_operand" "=r, r,r,m,m")
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279 (match_operand:MM 1 "mov_src_operand" " m,rI,B,r,I"))]
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280 ""
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281 "@
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282 ldx<mop>\t%0,%1
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283 mov\t%0,%1
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284 lddw\t%0,%1
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285 stx<mop>\t%0,%1
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286 st<mop>\t%0,%1"
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287 [(set_attr "type" "ldx,alu,alu,stx,st")])
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288
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289 ;;;; Shifts
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290
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291 (define_mode_iterator SIM [SI DI])
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292
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293 (define_insn "ashr<SIM:mode>3"
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294 [(set (match_operand:SIM 0 "register_operand" "=r,r")
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295 (ashiftrt:SIM (match_operand:SIM 1 "register_operand" " 0,0")
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296 (match_operand:SIM 2 "reg_or_imm_operand" " r,I")))]
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297 ""
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298 "arsh<msuffix>\t%0,%2"
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299 [(set_attr "type" "<mtype>")])
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300
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301 (define_insn "ashl<SIM:mode>3"
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302 [(set (match_operand:SIM 0 "register_operand" "=r,r")
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303 (ashift:SIM (match_operand:SIM 1 "register_operand" " 0,0")
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304 (match_operand:SIM 2 "reg_or_imm_operand" " r,I")))]
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305 ""
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306 "lsh<msuffix>\t%0,%2"
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307 [(set_attr "type" "<mtype>")])
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308
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309 (define_insn "lshr<SIM:mode>3"
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310 [(set (match_operand:SIM 0 "register_operand" "=r,r")
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311 (lshiftrt:SIM (match_operand:SIM 1 "register_operand" " 0,0")
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312 (match_operand:SIM 2 "reg_or_imm_operand" " r,I")))]
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313 ""
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314 "rsh<msuffix>\t%0,%2"
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315 [(set_attr "type" "<mtype>")])
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316
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317 ;;;; Conditional branches
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318
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319 ;; The eBPF jump instructions use 64-bit arithmetic when evaluating
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320 ;; the jump conditions. Therefore we use DI modes below.
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321
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322 (define_expand "cbranchdi4"
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323 [(set (pc)
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324 (if_then_else (match_operator 0 "comparison_operator"
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325 [(match_operand:DI 1 "register_operand")
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326 (match_operand:DI 2 "reg_or_imm_operand")])
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327 (label_ref (match_operand 3 "" ""))
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328 (pc)))]
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329 ""
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330 {
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331 if (!ordered_comparison_operator (operands[0], VOIDmode))
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332 FAIL;
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333 })
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334
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335 (define_insn "*branch_on_di"
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336 [(set (pc)
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337 (if_then_else (match_operator 3 "ordered_comparison_operator"
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338 [(match_operand:DI 0 "register_operand" "r")
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339 (match_operand:DI 1 "reg_or_imm_operand" "rI")])
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340 (label_ref (match_operand 2 "" ""))
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341 (pc)))]
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342 ""
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343 {
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344 int code = GET_CODE (operands[3]);
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345
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346 switch (code)
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347 {
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348 case EQ: return "jeq\t%0,%1,%2"; break;
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349 case NE: return "jne\t%0,%1,%2"; break;
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350 case LT: return "jslt\t%0,%1,%2"; break;
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351 case LE: return "jsle\t%0,%1,%2"; break;
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352 case GT: return "jsgt\t%0,%1,%2"; break;
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353 case GE: return "jsge\t%0,%1,%2"; break;
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354 case LTU: return "jlt\t%0,%1,%2"; break;
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355 case LEU: return "jle\t%0,%1,%2"; break;
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356 case GTU: return "jgt\t%0,%1,%2"; break;
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357 case GEU: return "jge\t%0,%1,%2"; break;
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358 default:
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359 gcc_unreachable ();
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360 return "";
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361 }
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362 }
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363 [(set_attr "type" "jmp")])
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364
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365 ;;;; Unconditional branches
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366
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367 (define_insn "jump"
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368 [(set (pc)
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369 (label_ref (match_operand 0 "" "")))]
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370 ""
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371 "ja\t%0"
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372 [(set_attr "type" "jmp")])
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373
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374 ;;;; Function prologue/epilogue
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375
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376 (define_insn "exit"
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377 [(simple_return)]
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378 ""
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379 "exit"
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380 [(set_attr "type" "jmp")])
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381
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382 (define_expand "prologue"
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383 [(const_int 0)]
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384 ""
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385 {
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386 bpf_expand_prologue ();
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387 DONE;
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388 })
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389
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390 (define_expand "epilogue"
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391 [(const_int 0)]
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392 ""
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393 {
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394 bpf_expand_epilogue ();
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395 DONE;
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396 })
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397
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398 ;;;; Function calls
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399
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400 (define_expand "call"
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401 [(parallel [(call (match_operand 0 "")
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402 (match_operand 1 ""))
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403 (use (match_operand 2 "")) ;; next_arg_reg
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404 (use (match_operand 3 ""))])] ;; struct_value_size_rtx
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405 ""
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406 {
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407 rtx target = XEXP (operands[0], 0);
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408 emit_call_insn (gen_call_internal (target, operands[1]));
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409 DONE;
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410 })
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411
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412 (define_insn "call_internal"
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413 [(call (mem:DI (match_operand:DI 0 "call_operand" "Sr"))
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414 (match_operand:SI 1 "general_operand" ""))]
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415 ;; operands[2] is next_arg_register
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416 ;; operands[3] is struct_value_size_rtx.
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417 ""
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418 { return bpf_output_call (operands[0]); }
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419 [(set_attr "type" "jmp")])
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420
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421 (define_expand "call_value"
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422 [(parallel [(set (match_operand 0 "")
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423 (call (match_operand 1 "")
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424 (match_operand 2 "")))
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425 (use (match_operand 3 ""))])] ;; next_arg_reg
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426 ""
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427 {
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428 rtx target = XEXP (operands[1], 0);
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429 emit_call_insn (gen_call_value_internal (operands[0], target,
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430 operands[2]));
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431 DONE;
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432 })
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433
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434 (define_insn "call_value_internal"
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435 [(set (match_operand 0 "register_operand" "")
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436 (call (mem:DI (match_operand:DI 1 "call_operand" "Sr"))
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437 (match_operand:SI 2 "general_operand" "")))]
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438 ;; operands[3] is next_arg_register
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439 ;; operands[4] is struct_value_size_rtx.
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440 ""
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441 { return bpf_output_call (operands[1]); }
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442 [(set_attr "type" "jmp")])
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443
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444 (define_insn "sibcall"
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445 [(call (label_ref (match_operand 0 "" ""))
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446 (match_operand:SI 1 "general_operand" ""))]
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447 ;; operands[2] is next_arg_register
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448 ;; operands[3] is struct_value_size_rtx.
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449 ""
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450 "ja\t%0"
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451 [(set_attr "type" "jmp")])
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452
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453 ;;;; Non-generic load instructions
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454
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455 (define_mode_iterator LDM [QI HI SI DI])
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456 (define_mode_attr ldop [(QI "b") (HI "h") (SI "w") (DI "dw")])
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457
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458 (define_insn "ldind<ldop>"
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459 [(set (reg:LDM R0_REGNUM)
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460 (unspec:LDM [(match_operand:DI 0 "register_operand" "r")
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461 (match_operand:SI 1 "imm32_operand" "I")]
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462 UNSPEC_LDINDABS))
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463 (clobber (reg:DI R1_REGNUM))
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464 (clobber (reg:DI R2_REGNUM))
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465 (clobber (reg:DI R3_REGNUM))
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466 (clobber (reg:DI R4_REGNUM))]
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467 ""
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468 "ldind<ldop>\t%0,%1"
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469 [(set_attr "type" "ld")])
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470
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471 (define_insn "ldabs<ldop>"
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472 [(set (reg:LDM R0_REGNUM)
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473 (unspec:LDM [(match_operand:SI 0 "imm32_operand" "I")
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474 (match_operand:SI 1 "imm32_operand" "I")]
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475 UNSPEC_LDINDABS))
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476 (clobber (reg:DI R1_REGNUM))
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477 (clobber (reg:DI R2_REGNUM))
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478 (clobber (reg:DI R3_REGNUM))
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479 (clobber (reg:DI R4_REGNUM))]
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480 ""
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481 "ldabs<ldop>\t%0"
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482 [(set_attr "type" "ld")])
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483
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484 ;;;; Atomic increments
|
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485
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486 (define_mode_iterator AMO [SI DI])
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487
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488 (define_insn "atomic_add<AMO:mode>"
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489 [(set (match_operand:AMO 0 "memory_operand" "+m")
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490 (unspec_volatile:AMO
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491 [(plus:AMO (match_dup 0)
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492 (match_operand:AMO 1 "register_operand" "r"))
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493 (match_operand:SI 2 "const_int_operand")] ;; Memory model.
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494 UNSPEC_XADD))]
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495 ""
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496 "xadd<mop>\t%0,%1"
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497 [(set_attr "type" "xadd")])
|
