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1 ;; DFA scheduling description for EPIPHANY
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2 ;; Copyright (C) 2004-2020 Free Software Foundation, Inc.
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3 ;; Contributed by Embecosm on behalf of Adapteva, Inc.
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4
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5 ;; This file is part of GCC.
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6
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7 ;; GCC is free software; you can redistribute it and/or modify
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8 ;; it under the terms of the GNU General Public License as published by
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9 ;; the Free Software Foundation; either version 3, or (at your option)
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10 ;; any later version.
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11
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12 ;; GCC is distributed in the hope that it will be useful,
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13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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15 ;; GNU General Public License for more details.
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16
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17 ;; You should have received a copy of the GNU General Public License
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18 ;; along with GCC; see the file COPYING3. If not see
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19 ;; <http://www.gnu.org/licenses/>.
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20
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21 ;; Two automata are defined to reduce number of states
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22 ;; which a single large automaton will have. (Factoring)
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23
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24 (define_automaton "inst_pipeline,fpu_pipe")
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25
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26 ;; This unit is basically the decode unit of the processor.
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27 ;; Since epiphany is a dual issue machine, it is as if there are two
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28 ;; units so that any insn can be processed by either one
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29 ;; of the decoding unit.
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30
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31 (define_cpu_unit "pipe_01,pipe_02" "inst_pipeline")
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32
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33 ;; The fixed point arithmetic unit.
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34
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35 (define_cpu_unit "int" "inst_pipeline")
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36
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37 ;; The floating point unit.
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38
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39 (define_cpu_unit "F0" "fpu_pipe")
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40
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41 ;; ----------------------------------------------------
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42 ;; This reservation is to simplify the dual issue description.
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43
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44 (define_reservation "issue" "pipe_01|pipe_02")
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45
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46 ;; This is to express instructions that cannot be paired.
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47
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48 (define_reservation "d_lock" "pipe_01+pipe_02")
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49
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50 ;; We don't model all pipeline stages; we model the issue stage
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51 ;; inasmuch as we allow only two instructions to issue simultaneously,
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52 ;; and flow instructions prevent any simultaneous issue of another instruction.
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53 ;; (This uses pipe_01 and pipe_02).
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54 ;; Double issue of 'other' insns is prevented by using the int unit in the
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55 ;; E1 stage.
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56 ;; Double issue of float instructions is prevented by using F0 in the E1 stage.
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57
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58 (define_insn_reservation "simple_arith" 2
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59 (and (eq_attr "pipe_model" "epiphany")
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60 (eq_attr "type" "move,cmove,compare,shift,misc,mul")
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61 (eq_attr "length" "4"))
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62 "issue,int")
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63
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64 ; anything but fp / fp_int / v2fp has a bypass
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65 (define_bypass 1 "simple_arith" "simple_arith,simple_arith_2,simple_arith_4,load,store,branch,call,flow")
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66
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67 (define_insn_reservation "simple_arith_2" 2
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68 (and (eq_attr "pipe_model" "epiphany")
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69 (eq_attr "type" "move,cmove,compare,shift,misc,mul")
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70 (eq_attr "length" "8"))
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71 "issue,issue+int,int")
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72
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73 (define_insn_reservation "simple_arith_4" 4
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74 (and (eq_attr "pipe_model" "epiphany")
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75 (eq_attr "type" "move,compare,shift,misc,mul")
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76 (eq_attr "length" "12,16,20,24"))
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77 "issue,issue+int,issue+int,issue+int,int")
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78
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79 ;; Loads have a latency of two.
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80 ;; Note that we fix up the latency of post_modify in epiphany.c:epiphany_adjust_cost
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81
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82 (define_insn_reservation "load" 3
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83 (and (eq_attr "pipe_model" "epiphany")
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84 (eq_attr "type" "load"))
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85 "issue,int")
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86
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87 ; anything but fp / fp_int / v2fp has a bypass
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88 (define_bypass 2 "load" "simple_arith,simple_arith_2,simple_arith_4,load,store,branch,call,flow")
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89
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90 (define_insn_reservation "store" 1
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91 (and (eq_attr "pipe_model" "epiphany")
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92 (eq_attr "type" "store"))
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93 "issue,int")
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94
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95 ;; Branch
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96 ;; Latency when taken: 3
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97 ;; Issue Rate: 1
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98 ;; The latency is 1 when the branch is not taken.
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99 ;; We can't really do much with the latency, even if we could express it,
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100 ;; but the pairing restrictions are useful to take into account.
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101
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102 (define_insn_reservation "branch" 1
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103 (and (eq_attr "pipe_model" "epiphany")
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104 (eq_attr "type" "branch,uncond_branch"))
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105 "d_lock")
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106
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107 ;; calls introduce a longisch delay that is likely to flush the pipelines
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108 ;; of the caller's instructions. Both the call instruction itself and
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109 ;; the rts at the end of the call / sfunc incurs a three cycle penalty,
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110 ;; thus also isolating the scheduling of caller and callee.
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111
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112 (define_insn_reservation "call" 8
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113 (and (eq_attr "pipe_model" "epiphany")
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114 (eq_attr "type" "call,sfunc,fp_sfunc"))
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115 "d_lock*8")
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116
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117 (define_insn_reservation "flow" 1
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118 (and (eq_attr "pipe_model" "epiphany")
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119 (eq_attr "type" "flow"))
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120 "d_lock")
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121
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122 (define_insn_reservation "fp_arith" 5
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123 (and (eq_attr "pipe_model" "epiphany")
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124 (eq_attr "type" "fp,fp_int"))
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125 "issue,F0")
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126
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127 (define_bypass 4 "fp_arith" "store")
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128
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129 ; There are two main consumers for v2fp:
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130 ; - other v2fp operation - in that case, the latencies can dovetail to
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131 ; save one cycle of latency.
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132 ; - 64 bit store operations - we need both registers, but OTOH the latency is
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133 ; one lower to start with.
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134 ; of the bypass saving one cyles then.
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135 (define_insn_reservation "v2fp_arith" 5
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136 (and (eq_attr "pipe_model" "epiphany")
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137 (eq_attr "type" "v2fp"))
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138 "issue,issue+F0,F0")
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139
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140 ; A boolean attribute for use by peephole2 patterns that try to figure out
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141 ; if we overcommitted the FPU.
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142 ; This is notionally a numeric attribute to avoid dependency problems.
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143 (define_attr "sched_use_fpu" ""
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144 (cond [(eq_attr "type" "fp,fp_int,v2fp") (const_int 1)]
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145 (const_int 0)))
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