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1 ;; Goldmont(GLM) Scheduling
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2 ;; Copyright (C) 2018-2020 Free Software Foundation, Inc.
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3 ;;
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4 ;; This file is part of GCC.
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5 ;;
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6 ;; GCC is free software; you can redistribute it and/or modify
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7 ;; it under the terms of the GNU General Public License as published by
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8 ;; the Free Software Foundation; either version 3, or (at your option)
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9 ;; any later version.
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10 ;;
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11 ;; GCC is distributed in the hope that it will be useful,
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12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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14 ;; GNU General Public License for more details.
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15 ;;
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16 ;; You should have received a copy of the GNU General Public License
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17 ;; along with GCC; see the file COPYING3. If not see
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18 ;; <http://www.gnu.org/licenses/>.
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19 ;;
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20 ;; Goldmont has 3 out-of-order IEC, 2 out-of--order FEC and out-of-order MEC.
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21
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22
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23 (define_automaton "glm")
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24
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25 ;; EU: Execution Unit
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26 ;; Goldmont has 3 clusters - IEC, FPC, MEC
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27
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28 ;; IEC has three execution ports - IEC-0, IEC-1 and IEC-2.
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29 ;; FPC has two execution ports - FPC-0 and FPC-1.
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30 ;; MEC has two execution ports - MEC-0 (load) and MEC-1 (store0.
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31 (define_cpu_unit "glm-iec-0,glm-iec-1,glm-iec-2" "glm")
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32 (define_cpu_unit "glm-fec-0,glm-fec-1,glm-load,glm-store" "glm")
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33
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34 ;; Some EUs have duplicated copied and can be accessed via either ports 0, 1 or 2.
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35 (define_reservation "glm-iec-any" "(glm-iec-0 | glm-iec-1 | glm-iec-2)")
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36 (define_reservation "glm-iec-any-load" "(glm-iec-0|glm-iec-1|glm-iec-2)+glm-load")
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37 (define_reservation "glm-iec-any-store" "(glm-iec-0|glm-iec-1|glm-iec-2)+glm-store")
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38 (define_reservation "glm-iec-any-both" "(glm-iec-0 | glm-iec-1 | glm-iec-2) + glm-load + glm-store")
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39 (define_reservation "glm-fec-all" "(glm-fec-0 + glm-fec-1)")
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40 (define_reservation "glm-all" "(glm-iec-0+glm-iec-1+glm-iec-2)+(glm-fec-0+glm-fec-1)+(glm-load+glm-store)")
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41 (define_reservation "glm-int-0" "glm-iec-0")
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42 (define_reservation "glm-int-0-load" "glm-iec-0 + glm-load")
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43 (define_reservation "glm-int-0-both" "glm-iec-0 + glm-load + glm-store")
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44 (define_reservation "glm-int-1" "glm-iec-1")
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45 (define_reservation "glm-int-1-mem" "glm-iec-1 + glm-load")
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46 (define_reservation "glm-int-2" "glm-iec-2")
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47 (define_reservation "glm-int-2-mem" "glm-iec-2 + glm-load")
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48 (define_reservation "glm-fp-0" "glm-fec-0")
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49 (define_reservation "glm-fec-any" "(glm-fec-0 | glm-fec-1)")
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50
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51 ;;; fmul insn can have 4 or 5 cycles latency for scalar and vector types.
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52 (define_reservation "glm-fmul-4c" "glm-fec-0, nothing*3")
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53 (define_reservation "glm-fmul-4c-mem" "glm-fec-0+glm-load, nothing*3")
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54 (define_reservation "glm-fmul-5c" "glm-fec-0, nothing*4")
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55
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56 ;;; fadd has 3 cycles latency.
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57 (define_reservation "glm-fadd-3c" "glm-fec-1, nothing*2")
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58 (define_reservation "glm-fadd-3c-mem" "glm-fec-1+glm-load, nothing*2")
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59
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60 ;;; imul insn has 3 cycles latency for SI operands
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61 (define_reservation "glm-imul-32" "glm-iec-1, nothing*2")
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62 (define_reservation "glm-imul-mem-32"
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63 "(glm-iec-1+glm-load), nothing*2")
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64 ;;; imul has 5 cycles latency for DI operands with 1/2 tput
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65 (define_reservation "glm-imul-64"
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66 "glm-iec-1, glm-iec-1, nothing*3")
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67 (define_reservation "glm-imul-mem-64"
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68 "glm-iec-1+glm-load, glm-iec-1, nothing*3")
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69
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70
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71 (define_insn_reservation "glm_other" 9
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72 (and (eq_attr "cpu" "glm")
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73 (and (eq_attr "type" "other")
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74 (eq_attr "atom_unit" "!jeu")))
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75 "glm-all*9")
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76
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77 ;; return has type "other" with atom_unit "jeu"
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78 (define_insn_reservation "glm_other_2" 1
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79 (and (eq_attr "cpu" "glm")
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80 (and (eq_attr "type" "other")
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81 (eq_attr "atom_unit" "jeu")))
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82 "glm-all")
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83
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84 (define_insn_reservation "glm_multi" 9
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85 (and (eq_attr "cpu" "glm")
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86 (eq_attr "type" "multi"))
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87 "glm-all*9")
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88
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89 ;; Normal alu insns without carry
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90 (define_insn_reservation "glm_alu" 1
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91 (and (eq_attr "cpu" "glm")
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92 (and (eq_attr "type" "alu")
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93 (and (eq_attr "memory" "none")
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94 (eq_attr "use_carry" "0"))))
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95 "glm-iec-any")
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96
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97 ;; Normal alu insns without carry, but use MEC.
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98 (define_insn_reservation "glm_alu_load" 1
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99 (and (eq_attr "cpu" "glm")
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100 (and (eq_attr "type" "alu")
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101 (and (eq_attr "memory" "load")
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102 (eq_attr "use_carry" "0"))))
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103 "glm-iec-any-load")
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104
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105 (define_insn_reservation "glm_alu_mem" 1
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106 (and (eq_attr "cpu" "glm")
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107 (and (eq_attr "type" "alu")
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108 (and (eq_attr "memory" "both")
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109 (eq_attr "use_carry" "0"))))
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110 "glm-iec-any-both")
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111
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112
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113 ;; Alu insn consuming CF, such as add/sbb
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114 (define_insn_reservation "glm_alu_carry" 2
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115 (and (eq_attr "cpu" "glm")
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116 (and (eq_attr "type" "alu")
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117 (and (eq_attr "memory" "none")
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118 (eq_attr "use_carry" "1"))))
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119 "glm-int-2, nothing")
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120
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121 ;; Alu insn consuming CF, such as add/sbb
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122 (define_insn_reservation "glm_alu_carry_mem" 2
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123 (and (eq_attr "cpu" "glm")
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124 (and (eq_attr "type" "alu")
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125 (and (eq_attr "memory" "!none")
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126 (eq_attr "use_carry" "1"))))
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127 "glm-int-2-mem, nothing")
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128
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129 (define_insn_reservation "glm_alu1" 1
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130 (and (eq_attr "cpu" "glm")
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131 (and (eq_attr "type" "alu1")
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132 (eq_attr "memory" "none") (eq_attr "prefix_0f" "0")))
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133 "glm-int-1")
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134
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135 ;; bsf and bsf insn
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136 (define_insn_reservation "glm_alu1_1" 10
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137 (and (eq_attr "cpu" "glm")
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138 (and (eq_attr "type" "alu1")
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139 (eq_attr "memory" "none") (eq_attr "prefix_0f" "1")))
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140 "glm-int-1*8,nothing*2")
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141
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142 (define_insn_reservation "glm_alu1_mem" 1
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143 (and (eq_attr "cpu" "glm")
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144 (and (eq_attr "type" "alu1")
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145 (eq_attr "memory" "!none")))
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146 "glm-int-1-mem")
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147
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148 (define_insn_reservation "glm_negnot" 1
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149 (and (eq_attr "cpu" "glm")
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150 (and (eq_attr "type" "negnot")
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151 (eq_attr "memory" "none")))
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152 "glm-iec-any")
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153
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154 (define_insn_reservation "glm_negnot_mem" 1
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155 (and (eq_attr "cpu" "glm")
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156 (and (eq_attr "type" "negnot")
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157 (eq_attr "memory" "!none")))
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158 "glm-iec-any-both")
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159
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160 (define_insn_reservation "glm_imov" 1
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161 (and (eq_attr "cpu" "glm")
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162 (and (eq_attr "type" "imov")
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163 (eq_attr "memory" "none")))
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164 "glm-iec-any")
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165
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166 (define_insn_reservation "glm_imov_load" 2
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167 (and (eq_attr "cpu" "glm")
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168 (and (eq_attr "type" "imov")
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169 (eq_attr "memory" "load")))
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170 "glm-iec-any-load,nothing")
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171
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172 (define_insn_reservation "glm_imov_store" 1
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173 (and (eq_attr "cpu" "glm")
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174 (and (eq_attr "type" "imov")
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175 (eq_attr "memory" "store")))
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176 "glm-iec-any-store")
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177
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178 ;; 16<-16, 32<-32
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179 (define_insn_reservation "glm_imovx" 1
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180 (and (eq_attr "cpu" "glm")
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181 (and (eq_attr "type" "imovx")
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182 (and (eq_attr "memory" "none")
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183 (ior (and (match_operand:HI 0 "register_operand")
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184 (match_operand:HI 1 "general_operand"))
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185 (and (match_operand:SI 0 "register_operand")
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186 (match_operand:SI 1 "general_operand"))))))
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187 "glm-iec-any")
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188
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189 ;; 16<-16, 32<-32, mem
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190 (define_insn_reservation "glm_imovx_mem" 1
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191 (and (eq_attr "cpu" "glm")
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192 (and (eq_attr "type" "imovx")
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193 (and (eq_attr "memory" "!none")
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194 (ior (and (match_operand:HI 0 "register_operand")
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195 (match_operand:HI 1 "general_operand"))
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196 (and (match_operand:SI 0 "register_operand")
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197 (match_operand:SI 1 "general_operand"))))))
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198 "glm-iec-any-load")
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199
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200
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201 ;; 32<-16, 32<-8, 64<-16, 64<-8, 64<-32, 8<-8
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202 (define_insn_reservation "glm_imovx_2" 1
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203 (and (eq_attr "cpu" "glm")
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204 (and (eq_attr "type" "imovx")
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205 (and (eq_attr "memory" "none")
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206 (ior (match_operand:QI 0 "register_operand")
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207 (ior (and (match_operand:SI 0 "register_operand")
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208 (not (match_operand:SI 1 "general_operand")))
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209 (match_operand:DI 0 "register_operand"))))))
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210 "glm-iec-any")
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211
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212 ;; 32<-16, 32<-8, 64<-16, 64<-8, 64<-32, 8<-8, mem
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213 (define_insn_reservation "glm_imovx_2_load" 2
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214 (and (eq_attr "cpu" "glm")
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215 (and (eq_attr "type" "imovx")
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216 (and (eq_attr "memory" "load")
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217 (ior (match_operand:QI 0 "register_operand")
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218 (ior (and (match_operand:SI 0 "register_operand")
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219 (not (match_operand:SI 1 "general_operand")))
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220 (match_operand:DI 0 "register_operand"))))))
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221 "glm-iec-any-load,nothing")
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222
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223 (define_insn_reservation "glm_imovx_2_mem" 1
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224 (and (eq_attr "cpu" "glm")
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225 (and (eq_attr "type" "imovx")
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226 (and (eq_attr "memory" "!none")
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227 (ior (match_operand:QI 0 "register_operand")
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228 (ior (and (match_operand:SI 0 "register_operand")
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229 (not (match_operand:SI 1 "general_operand")))
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230 (match_operand:DI 0 "register_operand"))))))
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231 "glm-iec-any-both")
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232
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233
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234 ;; 16<-8
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235 (define_insn_reservation "glm_imovx_3" 3
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236 (and (eq_attr "cpu" "glm")
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237 (and (eq_attr "type" "imovx")
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238 (and (match_operand:HI 0 "register_operand")
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239 (match_operand:QI 1 "general_operand"))))
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240 "glm-int-0, nothing*2")
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241
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242 (define_insn_reservation "glm_lea" 1
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243 (and (eq_attr "cpu" "glm")
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244 (and (eq_attr "type" "lea")
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245 (eq_attr "mode" "!HI")))
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246 "glm-iec-any")
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247
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248 ;; lea 16bit address is complex insn
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249 (define_insn_reservation "glm_lea_2" 2
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250 (and (eq_attr "cpu" "glm")
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251 (and (eq_attr "type" "lea")
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252 (eq_attr "mode" "HI")))
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253 "glm-all*2")
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254
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255 (define_insn_reservation "glm_incdec" 1
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256 (and (eq_attr "cpu" "glm")
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257 (and (eq_attr "type" "incdec")
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258 (eq_attr "memory" "none")))
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259 "glm-int-0")
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260
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261 (define_insn_reservation "glm_incdec_mem" 3
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262 (and (eq_attr "cpu" "glm")
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263 (and (eq_attr "type" "incdec")
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264 (eq_attr "memory" "!none")))
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265 "glm-int-0-both, nothing*2")
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266
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267 ;; simple shift instruction use SHIFT eu, none memory
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268 (define_insn_reservation "glm_ishift" 1
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269 (and (eq_attr "cpu" "glm")
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270 (and (eq_attr "type" "ishift")
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271 (and (eq_attr "memory" "none") (eq_attr "prefix_0f" "0"))))
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272 "glm-int-0")
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273
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274 ;; simple shift instruction use SHIFT eu, memory
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275 (define_insn_reservation "glm_ishift_mem" 2
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276 (and (eq_attr "cpu" "glm")
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277 (and (eq_attr "type" "ishift")
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278 (and (eq_attr "memory" "!none") (eq_attr "prefix_0f" "0"))))
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279 "glm-int-0-both,nothing")
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280
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281 ;; DF shift (prefixed with 0f) is complex insn with latency of 4 cycles
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282 (define_insn_reservation "glm_ishift_3" 4
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283 (and (eq_attr "cpu" "glm")
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284 (and (eq_attr "type" "ishift")
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285 (eq_attr "prefix_0f" "1")))
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286 "glm-all*4")
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287
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288 (define_insn_reservation "glm_ishift1" 1
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289 (and (eq_attr "cpu" "glm")
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290 (and (eq_attr "type" "ishift1")
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291 (eq_attr "memory" "none")))
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292 "glm-int-0")
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293
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294 (define_insn_reservation "glm_ishift1_mem" 2
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295 (and (eq_attr "cpu" "glm")
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296 (and (eq_attr "type" "ishift1")
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297 (eq_attr "memory" "!none")))
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298 "glm-int-0-both,nothing")
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299
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300 (define_insn_reservation "glm_rotate" 1
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301 (and (eq_attr "cpu" "glm")
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302 (and (eq_attr "type" "rotate")
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303 (eq_attr "memory" "none")))
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304 "glm-int-0")
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305
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306 (define_insn_reservation "glm_rotate_mem" 2
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307 (and (eq_attr "cpu" "glm")
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308 (and (eq_attr "type" "rotate")
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309 (eq_attr "memory" "!none")))
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310 "glm-int-0-both,nothing")
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311
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312 (define_insn_reservation "glm_imul" 3
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313 (and (eq_attr "cpu" "glm")
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314 (and (eq_attr "type" "imul")
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315 (and (eq_attr "memory" "none") (eq_attr "mode" "SI"))))
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316 "glm-imul-32")
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317
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318 (define_insn_reservation "glm_imul_load" 3
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319 (and (eq_attr "cpu" "glm")
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320 (and (eq_attr "type" "imul")
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321 (and (eq_attr "memory" "!none") (eq_attr "mode" "SI"))))
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322 "glm-imul-mem-32")
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323
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324
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325 ;; latency set to 5 as common 64x64 imul with 1/2 tput
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326 (define_insn_reservation "glm_imul64" 5
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327 (and (eq_attr "cpu" "glm")
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328 (and (eq_attr "type" "imul")
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329 (and (eq_attr "memory" "none") (eq_attr "mode" "!SI"))))
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330 "glm-imul-64")
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331
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332 (define_insn_reservation "glm_imul64-load" 5
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333 (and (eq_attr "cpu" "glm")
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334 (and (eq_attr "type" "imul")
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335 (and (eq_attr "memory" "!none") (eq_attr "mode" "!SI"))))
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336 "glm-imul-mem-64")
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337
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338 (define_insn_reservation "glm_idiv" 25
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339 (and (eq_attr "cpu" "glm")
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340 (eq_attr "type" "idiv"))
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341 "glm-all*16, nothing*9")
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342
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343 (define_insn_reservation "glm_icmp" 1
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344 (and (eq_attr "cpu" "glm")
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345 (and (eq_attr "type" "icmp")
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346 (eq_attr "memory" "none")))
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347 "glm-int-0")
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348
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349 (define_insn_reservation "glm_icmp_mem" 2
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350 (and (eq_attr "cpu" "glm")
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351 (and (eq_attr "type" "icmp")
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352 (eq_attr "memory" "!none")))
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353 "glm-int-0-load,nothing")
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354
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355 (define_insn_reservation "glm_test" 1
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356 (and (eq_attr "cpu" "glm")
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357 (and (eq_attr "type" "test")
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358 (eq_attr "memory" "none")))
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359 "glm-int-0")
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360
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361 (define_insn_reservation "glm_test_mem" 2
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362 (and (eq_attr "cpu" "glm")
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363 (and (eq_attr "type" "test")
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364 (eq_attr "memory" "!none")))
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365 "glm-int-0-load,nothing")
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366
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367 (define_insn_reservation "glm_ibr" 1
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368 (and (eq_attr "cpu" "glm")
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369 (and (eq_attr "type" "ibr")
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370 (eq_attr "memory" "!load")))
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371 "glm-int-1")
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372
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373 ;; complex if jump target is from address
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374 (define_insn_reservation "glm_ibr_2" 2
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375 (and (eq_attr "cpu" "glm")
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376 (and (eq_attr "type" "ibr")
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377 (eq_attr "memory" "load")))
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378 "glm-all*2")
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379
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380 (define_insn_reservation "glm_setcc" 1
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381 (and (eq_attr "cpu" "glm")
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382 (and (eq_attr "type" "setcc")
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383 (eq_attr "memory" "!store")))
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384 "glm-iec-any")
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385
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386 ;; 2 cycles complex if target is in memory
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387 (define_insn_reservation "glm_setcc_2" 2
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388 (and (eq_attr "cpu" "glm")
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389 (and (eq_attr "type" "setcc")
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390 (eq_attr "memory" "store")))
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391 "glm-all*2")
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392
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393 (define_insn_reservation "glm_icmov" 2
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394 (and (eq_attr "cpu" "glm")
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395 (and (eq_attr "type" "icmov")
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396 (eq_attr "memory" "none")))
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397 "glm-iec-any, nothing")
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398
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399 (define_insn_reservation "glm_icmov_mem" 2
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400 (and (eq_attr "cpu" "glm")
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401 (and (eq_attr "type" "icmov")
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402 (eq_attr "memory" "!none")))
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403 "glm-int-0-load, nothing")
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404
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405 ;; UCODE if segreg, ignored
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406 (define_insn_reservation "glm_push" 2
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407 (and (eq_attr "cpu" "glm")
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408 (eq_attr "type" "push"))
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409 "(glm-int-1+glm-int-2)*2")
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410
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411 ;; pop r64 is 1 cycle. UCODE if segreg, ignored
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412 (define_insn_reservation "glm_pop" 1
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413 (and (eq_attr "cpu" "glm")
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414 (and (eq_attr "type" "pop")
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415 (eq_attr "mode" "DI")))
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416 "glm-int-1+glm-int-2")
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417
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418 ;; pop non-r64 is 2 cycles. UCODE if segreg, ignored
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419 (define_insn_reservation "glm_pop_2" 2
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420 (and (eq_attr "cpu" "glm")
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421 (and (eq_attr "type" "pop")
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422 (eq_attr "mode" "!DI")))
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423 "(glm-int-1+glm-int-2)*2")
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424
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425 ;; UCODE if segreg, ignored
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426 (define_insn_reservation "glm_call" 1
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427 (and (eq_attr "cpu" "glm")
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428 (eq_attr "type" "call,callv"))
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429 "(glm-int-0+glm-int-1)")
|
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430
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|
431 (define_insn_reservation "glm_leave" 3
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|
432 (and (eq_attr "cpu" "glm")
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433 (eq_attr "type" "leave"))
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434 "glm-all*3")
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435
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|
436 (define_insn_reservation "glm_str" 3
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437 (and (eq_attr "cpu" "glm")
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|
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438 (eq_attr "type" "str"))
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439 "glm-all*3")
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|
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440
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|
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441 (define_insn_reservation "glm_sselog" 1
|
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442 (and (eq_attr "cpu" "glm")
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443 (and (eq_attr "type" "sselog")
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444 (eq_attr "memory" "none")))
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|
445 "glm-fec-all")
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446
|
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|
447 (define_insn_reservation "glm_sselog_mem" 1
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|
448 (and (eq_attr "cpu" "glm")
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449 (and (eq_attr "type" "sselog")
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|
450 (eq_attr "memory" "!none")))
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|
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451 "glm-fec-all+glm-load")
|
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452
|
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|
453 (define_insn_reservation "glm_sselog1" 1
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|
454 (and (eq_attr "cpu" "glm")
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455 (and (eq_attr "type" "sselog1")
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|
|
456 (eq_attr "memory" "none")))
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|
|
457 "glm-fp-0")
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|
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458
|
|
|
459 (define_insn_reservation "glm_sselog1_mem" 1
|
|
|
460 (and (eq_attr "cpu" "glm")
|
|
|
461 (and (eq_attr "type" "sselog1")
|
|
|
462 (eq_attr "memory" "!none")))
|
|
|
463 "glm-fp-0+glm-load")
|
|
|
464
|
|
|
465 ;; not pmad, not psad
|
|
|
466 (define_insn_reservation "glm_sseiadd" 3
|
|
|
467 (and (eq_attr "cpu" "glm")
|
|
|
468 (and (eq_attr "type" "sseiadd")
|
|
|
469 (and (not (match_operand:V2DI 0 "register_operand"))
|
|
|
470 (and (eq_attr "atom_unit" "!simul")
|
|
|
471 (eq_attr "atom_unit" "!complex")))))
|
|
|
472 "glm-fadd-3c")
|
|
|
473
|
|
|
474 ;; pmad, psad and 64
|
|
|
475 (define_insn_reservation "glm_sseiadd_2" 4
|
|
|
476 (and (eq_attr "cpu" "glm")
|
|
|
477 (and (eq_attr "type" "sseiadd")
|
|
|
478 (and (not (match_operand:V2DI 0 "register_operand"))
|
|
|
479 (and (eq_attr "atom_unit" "simul")
|
|
|
480 (eq_attr "mode" "DI,TI")))))
|
|
|
481 "glm-fmul-4c")
|
|
|
482
|
|
|
483 ;; if paddq(64 bit op), phadd/phsub
|
|
|
484 (define_insn_reservation "glm_sseiadd_3" 5
|
|
|
485 (and (eq_attr "cpu" "glm")
|
|
|
486 (and (eq_attr "type" "sseiadd")
|
|
|
487 (ior (match_operand:V2DI 0 "register_operand")
|
|
|
488 (eq_attr "atom_unit" "complex"))))
|
|
|
489 "glm-fmul-5c")
|
|
|
490
|
|
|
491 ;; if immediate op.
|
|
|
492 (define_insn_reservation "glm_sseishft" 2
|
|
|
493 (and (eq_attr "cpu" "glm")
|
|
|
494 (and (eq_attr "type" "sseishft")
|
|
|
495 (match_operand 2 "immediate_operand")))
|
|
|
496 "glm-fp-0, nothing")
|
|
|
497
|
|
|
498 (define_insn_reservation "glm_sseimul" 4
|
|
|
499 (and (eq_attr "cpu" "glm")
|
|
|
500 (and (eq_attr "type" "sseimul")
|
|
|
501 (eq_attr "memory" "none")))
|
|
|
502 "glm-fmul-4c")
|
|
|
503
|
|
|
504 (define_insn_reservation "glm_sseimul_load" 4
|
|
|
505 (and (eq_attr "cpu" "glm")
|
|
|
506 (and (eq_attr "type" "sseimul")
|
|
|
507 (eq_attr "memory" "!none")))
|
|
|
508 "glm-fmul-4c-mem")
|
|
|
509
|
|
|
510
|
|
|
511 ;; rcpss or rsqrtss
|
|
|
512 (define_insn_reservation "glm_sse" 4
|
|
|
513 (and (eq_attr "cpu" "glm")
|
|
|
514 (and (eq_attr "type" "sse")
|
|
|
515 (and (eq_attr "atom_sse_attr" "rcp") (eq_attr "mode" "SF"))))
|
|
|
516 "glm-fmul-4c")
|
|
|
517
|
|
|
518 ;; movshdup, movsldup. Suggest to type sseishft
|
|
|
519 (define_insn_reservation "glm_sse_2" 1
|
|
|
520 (and (eq_attr "cpu" "glm")
|
|
|
521 (and (eq_attr "type" "sse")
|
|
|
522 (eq_attr "atom_sse_attr" "movdup")))
|
|
|
523 "glm-fec-any")
|
|
|
524
|
|
|
525 ;; lfence
|
|
|
526 (define_insn_reservation "glm_sse_3" 1
|
|
|
527 (and (eq_attr "cpu" "glm")
|
|
|
528 (and (eq_attr "type" "sse")
|
|
|
529 (eq_attr "atom_sse_attr" "lfence")))
|
|
|
530 "glm-fec-any")
|
|
|
531
|
|
|
532 ;; sfence,clflush,mfence, prefetch
|
|
|
533 (define_insn_reservation "glm_sse_4" 1
|
|
|
534 (and (eq_attr "cpu" "glm")
|
|
|
535 (and (eq_attr "type" "sse")
|
|
|
536 (ior (eq_attr "atom_sse_attr" "fence")
|
|
|
537 (eq_attr "atom_sse_attr" "prefetch"))))
|
|
|
538 "glm-fp-0")
|
|
|
539
|
|
|
540 ;; rcpps, rsqrtss, sqrt, ldmxcsr
|
|
|
541 (define_insn_reservation "glm_sse_5" 9
|
|
|
542 (and (eq_attr "cpu" "glm")
|
|
|
543 (and (eq_attr "type" "sse")
|
|
|
544 (ior (ior (eq_attr "atom_sse_attr" "sqrt")
|
|
|
545 (eq_attr "atom_sse_attr" "mxcsr"))
|
|
|
546 (and (eq_attr "atom_sse_attr" "rcp")
|
|
|
547 (eq_attr "mode" "V4SF")))))
|
|
|
548 "glm-fec-all*6, nothing*3")
|
|
|
549
|
|
|
550 ;; xmm->xmm
|
|
|
551 (define_insn_reservation "glm_ssemov" 1
|
|
|
552 (and (eq_attr "cpu" "glm")
|
|
|
553 (and (eq_attr "type" "ssemov")
|
|
|
554 (and (match_operand 0 "register_operand" "xy")
|
|
|
555 (match_operand 1 "register_operand" "xy"))))
|
|
|
556 "glm-fec-any")
|
|
|
557
|
|
|
558 ;; reg->xmm
|
|
|
559 (define_insn_reservation "glm_ssemov_2" 1
|
|
|
560 (and (eq_attr "cpu" "glm")
|
|
|
561 (and (eq_attr "type" "ssemov")
|
|
|
562 (and (match_operand 0 "register_operand" "xy")
|
|
|
563 (match_operand 1 "register_operand" "r"))))
|
|
|
564 "glm-fp-0")
|
|
|
565
|
|
|
566 ;; xmm->reg
|
|
|
567 (define_insn_reservation "glm_ssemov_3" 3
|
|
|
568 (and (eq_attr "cpu" "glm")
|
|
|
569 (and (eq_attr "type" "ssemov")
|
|
|
570 (and (match_operand 0 "register_operand" "r")
|
|
|
571 (match_operand 1 "register_operand" "xy"))))
|
|
|
572 "glm-fp-0, nothing*2")
|
|
|
573
|
|
|
574 ;; mov mem
|
|
|
575 (define_insn_reservation "glm_ssemov_load" 2
|
|
|
576 (and (eq_attr "cpu" "glm")
|
|
|
577 (and (eq_attr "type" "ssemov")
|
|
|
578 (eq_attr "memory" "load")))
|
|
|
579 "glm-fec-any+glm-load,nothing")
|
|
|
580
|
|
|
581 (define_insn_reservation "glm_ssemov_store" 1
|
|
|
582 (and (eq_attr "cpu" "glm")
|
|
|
583 (and (eq_attr "type" "ssemov")
|
|
|
584 (eq_attr "memory" "store")))
|
|
|
585 "glm-fec-any+glm-store")
|
|
|
586
|
|
|
587 ;; no memory simple
|
|
|
588 (define_insn_reservation "glm_sseadd" 3
|
|
|
589 (and (eq_attr "cpu" "glm")
|
|
|
590 (and (eq_attr "type" "sseadd")
|
|
|
591 (eq_attr "memory" "none")))
|
|
|
592 "glm-fadd-3c")
|
|
|
593
|
|
|
594 ;; memory simple
|
|
|
595 (define_insn_reservation "glm_sseadd_mem" 3
|
|
|
596 (and (eq_attr "cpu" "glm")
|
|
|
597 (and (eq_attr "type" "sseadd")
|
|
|
598 (eq_attr "memory" "!none")))
|
|
|
599 "glm-fadd-3c-mem")
|
|
|
600
|
|
|
601 ;; Except dppd/dpps
|
|
|
602 (define_insn_reservation "glm_ssemul" 4
|
|
|
603 (and (eq_attr "cpu" "glm")
|
|
|
604 (and (eq_attr "type" "ssemul")
|
|
|
605 (eq_attr "memory" "none")))
|
|
|
606 "glm-fmul-4c")
|
|
|
607
|
|
|
608 (define_insn_reservation "glm_ssemul_mem" 4
|
|
|
609 (and (eq_attr "cpu" "glm")
|
|
|
610 (and (eq_attr "type" "ssemul")
|
|
|
611 (eq_attr "memory" "!none")))
|
|
|
612 "glm-fmul-4c-mem")
|
|
|
613
|
|
|
614 (define_insn_reservation "glm_ssecmp" 1
|
|
|
615 (and (eq_attr "cpu" "glm")
|
|
|
616 (eq_attr "type" "ssecmp"))
|
|
|
617 "glm-fec-any")
|
|
|
618
|
|
|
619 (define_insn_reservation "glm_ssecomi" 1
|
|
|
620 (and (eq_attr "cpu" "glm")
|
|
|
621 (eq_attr "type" "ssecomi"))
|
|
|
622 "glm-fp-0")
|
|
|
623
|
|
|
624 ;; no memory and cvtpi2ps, cvtps2pi, cvttps2pi
|
|
|
625 (define_insn_reservation "glm_ssecvt" 4
|
|
|
626 (and (eq_attr "cpu" "glm")
|
|
|
627 (and (eq_attr "type" "ssecvt")
|
|
|
628 (ior (and (match_operand:V2SI 0 "register_operand")
|
|
|
629 (match_operand:V4SF 1 "register_operand"))
|
|
|
630 (and (match_operand:V4SF 0 "register_operand")
|
|
|
631 (match_operand:V2SI 1 "register_operand")))))
|
|
|
632 "glm-fp-0, nothing*3")
|
|
|
633
|
|
|
634 ;; memory and cvtpi2ps, cvtps2pi, cvttps2pi
|
|
|
635 (define_insn_reservation "glm_ssecvt_mem" 4
|
|
|
636 (and (eq_attr "cpu" "glm")
|
|
|
637 (and (eq_attr "type" "ssecvt")
|
|
|
638 (ior (and (match_operand:V2SI 0 "register_operand")
|
|
|
639 (match_operand:V4SF 1 "memory_operand"))
|
|
|
640 (and (match_operand:V4SF 0 "register_operand")
|
|
|
641 (match_operand:V2SI 1 "memory_operand")))))
|
|
|
642 "glm-fp-0+glm-load, nothing*3")
|
|
|
643
|
|
|
644 ;; memory and cvtsi2sd
|
|
|
645 (define_insn_reservation "glm_sseicvt" 1
|
|
|
646 (and (eq_attr "cpu" "glm")
|
|
|
647 (and (eq_attr "type" "sseicvt")
|
|
|
648 (and (match_operand:V2DF 0 "register_operand")
|
|
|
649 (match_operand:SI 1 "nonimmediate_operand"))))
|
|
|
650 "glm-fp-0")
|
|
|
651
|
|
|
652 ;; otherwise. 8 cycles average for cvtsd2si
|
|
|
653 (define_insn_reservation "glm_sseicvt_2" 4
|
|
|
654 (and (eq_attr "cpu" "glm")
|
|
|
655 (and (eq_attr "type" "sseicvt")
|
|
|
656 (not (and (match_operand:V2DF 0 "register_operand")
|
|
|
657 (match_operand:SI 1 "memory_operand")))))
|
|
|
658 "glm-fp-0, nothing*3")
|
|
|
659
|
|
|
660 (define_insn_reservation "glm_ssediv" 13
|
|
|
661 (and (eq_attr "cpu" "glm")
|
|
|
662 (eq_attr "type" "ssediv"))
|
|
|
663 "glm-fec-all*12, nothing")
|
|
|
664
|
|
|
665 ;; simple for fmov
|
|
|
666 (define_insn_reservation "glm_fmov" 1
|
|
|
667 (and (eq_attr "cpu" "glm")
|
|
|
668 (and (eq_attr "type" "fmov")
|
|
|
669 (eq_attr "memory" "none")))
|
|
|
670 "glm-fec-any")
|
|
|
671
|
|
|
672 ;; simple for fmov
|
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673 (define_insn_reservation "glm_fmov_load" 3
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674 (and (eq_attr "cpu" "glm")
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675 (and (eq_attr "type" "fmov")
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676 (eq_attr "memory" "load")))
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677 "glm-fec-any+glm-load, nothing*2")
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678
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679 (define_insn_reservation "glm_fmov_store" 1
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680 (and (eq_attr "cpu" "glm")
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681 (and (eq_attr "type" "fmov")
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682 (eq_attr "memory" "store")))
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683 "glm-fec-any+glm-store")
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684
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685 ;; Define bypass here
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686
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687 ;; There will be 0 cycle stall from cmp/test to jcc
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688
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689 ;; There will be 1 cycle stall from flag producer to cmov and adc/sbb
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690 (define_bypass 2 "glm_icmp, glm_test, glm_alu, glm_alu_carry,
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691 glm_alu1, glm_negnot, glm_incdec, glm_ishift,
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692 glm_ishift1, glm_rotate"
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693 "glm_icmov, glm_alu_carry")
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694
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695 ;; lea to shift source stall is 1 cycle
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696 (define_bypass 2 "glm_lea"
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697 "glm_ishift, glm_ishift1, glm_rotate"
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698 "!ix86_dep_by_shift_count")
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699
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700 ;; non-lea to shift count stall is 1 cycle
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701 (define_bypass 2 "glm_alu_carry,
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702 glm_alu,glm_alu1,glm_negnot,glm_imov,glm_imovx,
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703 glm_incdec,glm_ishift,glm_ishift1,glm_rotate,
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704 glm_setcc, glm_icmov, glm_pop, glm_imov_store,
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705 glm_alu_mem, glm_alu_carry_mem, glm_alu1_mem,
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706 glm_alu_load, glm_imovx_mem, glm_imovx_2_mem,
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707 glm_imov_load, glm_icmov_mem, glm_fmov_load, glm_fmov_store"
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708 "glm_ishift, glm_ishift1, glm_rotate,
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709 glm_ishift_mem, glm_ishift1_mem,
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710 glm_rotate_mem"
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711 "ix86_dep_by_shift_count")
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