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1 ;; Copyright (C) 2012-2020 Free Software Foundation, Inc.
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111
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2 ;;
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3 ;; This file is part of GCC.
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4 ;;
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5 ;; GCC is free software; you can redistribute it and/or modify
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6 ;; it under the terms of the GNU General Public License as published by
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7 ;; the Free Software Foundation; either version 3, or (at your option)
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8 ;; any later version.
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9 ;;
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10 ;; GCC is distributed in the hope that it will be useful,
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11 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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12 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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13 ;; GNU General Public License for more details.
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14 ;;
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15 ;; You should have received a copy of the GNU General Public License
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16 ;; along with GCC; see the file COPYING3. If not see
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17 ;; <http://www.gnu.org/licenses/>.
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18 ;;
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19
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145
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20
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111
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21 (define_attr "znver1_decode" "direct,vector,double"
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22 (const_string "direct"))
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23
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145
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24 ;; AMD znver1 and znver2 Scheduling
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25 ;; Modeling automatons for zen decoders, integer execution pipes,
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26 ;; AGU pipes and floating point execution units.
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27 (define_automaton "znver1, znver1_ieu, znver1_fp, znver1_agu")
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28
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29 ;; Decoders unit has 4 decoders and all of them can decode fast path
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30 ;; and vector type instructions.
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31 (define_cpu_unit "znver1-decode0" "znver1")
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32 (define_cpu_unit "znver1-decode1" "znver1")
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33 (define_cpu_unit "znver1-decode2" "znver1")
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34 (define_cpu_unit "znver1-decode3" "znver1")
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35
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36 ;; Currently blocking all decoders for vector path instructions as
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37 ;; they are dispatched separetely as microcode sequence.
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38 ;; Fix me: Need to revisit this.
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39 (define_reservation "znver1-vector" "znver1-decode0+znver1-decode1+znver1-decode2+znver1-decode3")
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40
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41 ;; Direct instructions can be issued to any of the four decoders.
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42 (define_reservation "znver1-direct" "znver1-decode0|znver1-decode1|znver1-decode2|znver1-decode3")
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43
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44 ;; Fix me: Need to revisit this later to simulate fast path double behavior.
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45 (define_reservation "znver1-double" "znver1-direct")
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46
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47
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48 ;; Integer unit 4 ALU pipes.
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49 (define_cpu_unit "znver1-ieu0" "znver1_ieu")
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50 (define_cpu_unit "znver1-ieu1" "znver1_ieu")
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51 (define_cpu_unit "znver1-ieu2" "znver1_ieu")
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52 (define_cpu_unit "znver1-ieu3" "znver1_ieu")
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53 (define_reservation "znver1-ieu" "znver1-ieu0|znver1-ieu1|znver1-ieu2|znver1-ieu3")
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54
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55 ;; 2 AGU pipes in znver1 and 3 AGU pipes in znver2
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56 ;; According to CPU diagram last AGU unit is used only for stores.
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111
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57 (define_cpu_unit "znver1-agu0" "znver1_agu")
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58 (define_cpu_unit "znver1-agu1" "znver1_agu")
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145
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59 (define_cpu_unit "znver2-agu2" "znver1_agu")
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111
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60 (define_reservation "znver1-agu-reserve" "znver1-agu0|znver1-agu1")
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145
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61 (define_reservation "znver2-store-agu-reserve" "znver1-agu0|znver1-agu1|znver2-agu2")
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62
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145
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63 ;; Load is 4 cycles. We do not model reservation of load unit.
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64 ;;(define_reservation "znver1-load" "znver1-agu-reserve, nothing, nothing, nothing")
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111
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65 (define_reservation "znver1-load" "znver1-agu-reserve")
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145
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66 ;; Store operations differs between znver1 and znver2 because extra AGU
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67 ;; was added.
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111
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68 (define_reservation "znver1-store" "znver1-agu-reserve")
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145
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69 (define_reservation "znver2-store" "znver2-store-agu-reserve")
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111
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70
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71 ;; vectorpath (microcoded) instructions are single issue instructions.
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72 ;; So, they occupy all the integer units.
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73 (define_reservation "znver1-ivector" "znver1-ieu0+znver1-ieu1
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74 +znver1-ieu2+znver1-ieu3
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75 +znver1-agu0+znver1-agu1")
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76
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145
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77 (define_reservation "znver2-ivector" "znver1-ieu0+znver1-ieu1
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78 +znver1-ieu2+znver1-ieu3
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79 +znver1-agu0+znver1-agu1+znver2-agu2")
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111
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80 ;; Floating point unit 4 FP pipes.
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81 (define_cpu_unit "znver1-fp0" "znver1_fp")
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82 (define_cpu_unit "znver1-fp1" "znver1_fp")
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83 (define_cpu_unit "znver1-fp2" "znver1_fp")
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84 (define_cpu_unit "znver1-fp3" "znver1_fp")
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85
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86 (define_reservation "znver1-fpu" "znver1-fp0|znver1-fp1|znver1-fp2|znver1-fp3")
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87
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88 (define_reservation "znver1-fvector" "znver1-fp0+znver1-fp1
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89 +znver1-fp2+znver1-fp3
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90 +znver1-agu0+znver1-agu1")
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145
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91 (define_reservation "znver2-fvector" "znver1-fp0+znver1-fp1
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92 +znver1-fp2+znver1-fp3
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93 +znver1-agu0+znver1-agu1+znver2-agu2")
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111
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94
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95 ;; Call instruction
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96 (define_insn_reservation "znver1_call" 1
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97 (and (eq_attr "cpu" "znver1")
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98 (eq_attr "type" "call,callv"))
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99 "znver1-double,znver1-store,znver1-ieu0|znver1-ieu3")
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100
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145
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101 (define_insn_reservation "znver2_call" 1
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102 (and (eq_attr "cpu" "znver2")
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103 (eq_attr "type" "call,callv"))
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104 "znver1-double,znver2-store,znver1-ieu0|znver1-ieu3")
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105
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111
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106 ;; General instructions
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107 (define_insn_reservation "znver1_push" 1
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108 (and (eq_attr "cpu" "znver1")
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109 (and (eq_attr "type" "push")
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145
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110 (eq_attr "memory" "store")))
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111
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111 "znver1-direct,znver1-store")
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145
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112 (define_insn_reservation "znver2_push" 1
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113 (and (eq_attr "cpu" "znver2")
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111
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114 (and (eq_attr "type" "push")
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115 (eq_attr "memory" "store")))
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116 "znver1-direct,znver1-store")
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117
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145
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118 (define_insn_reservation "znver1_push_load" 4
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111
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119 (and (eq_attr "cpu" "znver1")
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120 (and (eq_attr "type" "push")
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121 (eq_attr "memory" "both")))
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122 "znver1-direct,znver1-load,znver1-store")
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145
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123 (define_insn_reservation "znver2_push_load" 4
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124 (and (eq_attr "cpu" "znver2")
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125 (and (eq_attr "type" "push")
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126 (eq_attr "memory" "both")))
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127 "znver1-direct,znver1-load,znver2-store")
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111
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128
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129 (define_insn_reservation "znver1_pop" 4
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145
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130 (and (eq_attr "cpu" "znver1,znver2")
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111
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131 (and (eq_attr "type" "pop")
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132 (eq_attr "memory" "load")))
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133 "znver1-direct,znver1-load")
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134
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135 (define_insn_reservation "znver1_pop_mem" 4
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136 (and (eq_attr "cpu" "znver1")
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137 (and (eq_attr "type" "pop")
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138 (eq_attr "memory" "both")))
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139 "znver1-direct,znver1-load,znver1-store")
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145
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140 (define_insn_reservation "znver2_pop_mem" 4
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141 (and (eq_attr "cpu" "znver2")
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142 (and (eq_attr "type" "pop")
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143 (eq_attr "memory" "both")))
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144 "znver1-direct,znver1-load,znver2-store")
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111
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145
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146 ;; Leave
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147 (define_insn_reservation "znver1_leave" 1
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148 (and (eq_attr "cpu" "znver1")
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149 (eq_attr "type" "leave"))
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150 "znver1-double,znver1-ieu, znver1-store")
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145
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151 (define_insn_reservation "znver2_leave" 1
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152 (and (eq_attr "cpu" "znver2")
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153 (eq_attr "type" "leave"))
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154 "znver1-double,znver1-ieu, znver2-store")
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111
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155
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156 ;; Integer Instructions or General instructions
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157 ;; Multiplications
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158 ;; Reg operands
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159 (define_insn_reservation "znver1_imul" 3
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145
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160 (and (eq_attr "cpu" "znver1,znver2")
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111
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161 (and (eq_attr "type" "imul")
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162 (eq_attr "memory" "none")))
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163 "znver1-direct,znver1-ieu1")
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164
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165 (define_insn_reservation "znver1_imul_mem" 7
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145
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166 (and (eq_attr "cpu" "znver1,znver2")
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111
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167 (and (eq_attr "type" "imul")
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168 (eq_attr "memory" "!none")))
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169 "znver1-direct,znver1-load, znver1-ieu1")
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170
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171 ;; Divisions
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172 ;; Reg operands
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173 (define_insn_reservation "znver1_idiv_DI" 41
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145
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174 (and (eq_attr "cpu" "znver1,znver2")
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111
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175 (and (eq_attr "type" "idiv")
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176 (and (eq_attr "mode" "DI")
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177 (eq_attr "memory" "none"))))
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178 "znver1-double,znver1-ieu2*41")
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179
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180 (define_insn_reservation "znver1_idiv_SI" 25
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145
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181 (and (eq_attr "cpu" "znver1,znver2")
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111
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182 (and (eq_attr "type" "idiv")
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183 (and (eq_attr "mode" "SI")
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184 (eq_attr "memory" "none"))))
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185 "znver1-double,znver1-ieu2*25")
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186
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187 (define_insn_reservation "znver1_idiv_HI" 17
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145
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188 (and (eq_attr "cpu" "znver1,znver2")
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111
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189 (and (eq_attr "type" "idiv")
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190 (and (eq_attr "mode" "HI")
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191 (eq_attr "memory" "none"))))
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192 "znver1-double,znver1-ieu2*17")
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193
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194 (define_insn_reservation "znver1_idiv_QI" 12
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145
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195 (and (eq_attr "cpu" "znver1,znver2")
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111
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196 (and (eq_attr "type" "idiv")
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197 (and (eq_attr "mode" "QI")
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198 (eq_attr "memory" "none"))))
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199 "znver1-direct,znver1-ieu2*12")
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200
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201 ;; Mem operands
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202 (define_insn_reservation "znver1_idiv_mem_DI" 45
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145
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203 (and (eq_attr "cpu" "znver1,znver2")
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111
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204 (and (eq_attr "type" "idiv")
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205 (and (eq_attr "mode" "DI")
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206 (eq_attr "memory" "none"))))
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207 "znver1-double,znver1-load,znver1-ieu2*41")
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208
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209 (define_insn_reservation "znver1_idiv_mem_SI" 29
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145
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210 (and (eq_attr "cpu" "znver1,znver2")
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111
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211 (and (eq_attr "type" "idiv")
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212 (and (eq_attr "mode" "SI")
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213 (eq_attr "memory" "none"))))
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214 "znver1-double,znver1-load,znver1-ieu2*25")
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215
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216 (define_insn_reservation "znver1_idiv_mem_HI" 21
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145
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217 (and (eq_attr "cpu" "znver1,znver2")
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111
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218 (and (eq_attr "type" "idiv")
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219 (and (eq_attr "mode" "HI")
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220 (eq_attr "memory" "none"))))
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221 "znver1-double,znver1-load,znver1-ieu2*17")
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222
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223 (define_insn_reservation "znver1_idiv_mem_QI" 16
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145
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224 (and (eq_attr "cpu" "znver1,znver2")
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111
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225 (and (eq_attr "type" "idiv")
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226 (and (eq_attr "mode" "QI")
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227 (eq_attr "memory" "none"))))
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228 "znver1-direct,znver1-load,znver1-ieu2*12")
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229
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230 ;; STR ISHIFT which are micro coded.
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231 ;; Fix me: Latency need to be rechecked.
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232 (define_insn_reservation "znver1_str_ishift" 6
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233 (and (eq_attr "cpu" "znver1")
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234 (and (eq_attr "type" "str,ishift")
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235 (eq_attr "memory" "both,store")))
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236 "znver1-vector,znver1-ivector")
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145
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237
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238 (define_insn_reservation "znver2_str_ishift" 3
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239 (and (eq_attr "cpu" "znver2")
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240 (and (eq_attr "type" "ishift")
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241 (eq_attr "memory" "both,store")))
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242 "znver1-vector,znver1-ivector")
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243 (define_insn_reservation "znver2_str_istr" 19
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244 (and (eq_attr "cpu" "znver2")
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245 (and (eq_attr "type" "str")
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246 (eq_attr "memory" "both,store")))
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247 "znver1-vector,znver1-ivector")
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111
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248 ;; MOV - integer moves
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249 (define_insn_reservation "znver1_load_imov_double" 2
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250 (and (eq_attr "cpu" "znver1")
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251 (and (eq_attr "znver1_decode" "double")
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252 (and (eq_attr "type" "imovx")
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253 (eq_attr "memory" "none"))))
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254 "znver1-double,znver1-ieu|znver1-ieu")
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255
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256 (define_insn_reservation "znver2_load_imov_double" 1
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257 (and (eq_attr "cpu" "znver2")
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258 (and (eq_attr "znver1_decode" "double")
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259 (and (eq_attr "type" "imovx")
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260 (eq_attr "memory" "none"))))
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261 "znver1-double,znver1-ieu|znver1-ieu")
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111
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262
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263 (define_insn_reservation "znver1_load_imov_direct" 1
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145
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264 (and (eq_attr "cpu" "znver1,znver2")
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111
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265 (and (eq_attr "type" "imov,imovx")
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266 (eq_attr "memory" "none")))
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267 "znver1-direct,znver1-ieu")
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268
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269 (define_insn_reservation "znver1_load_imov_double_store" 2
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270 (and (eq_attr "cpu" "znver1")
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271 (and (eq_attr "znver1_decode" "double")
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272 (and (eq_attr "type" "imovx")
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273 (eq_attr "memory" "store"))))
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145
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274 "znver1-double,znver1-ieu|znver1-ieu,znver1-store")
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275
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276 (define_insn_reservation "znver2_load_imov_double_store" 1
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277 (and (eq_attr "cpu" "znver2")
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278 (and (eq_attr "znver1_decode" "double")
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279 (and (eq_attr "type" "imovx")
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280 (eq_attr "memory" "store"))))
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281 "znver1-double,znver1-ieu|znver1-ieu,znver2-store")
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111
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282
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283 (define_insn_reservation "znver1_load_imov_direct_store" 1
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284 (and (eq_attr "cpu" "znver1")
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285 (and (eq_attr "type" "imov,imovx")
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286 (eq_attr "memory" "store")))
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287 "znver1-direct,znver1-ieu,znver1-store")
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288
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145
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289 (define_insn_reservation "znver2_load_imov_direct_store" 1
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290 (and (eq_attr "cpu" "znver2")
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291 (and (eq_attr "type" "imov,imovx")
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292 (eq_attr "memory" "store")))
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293 "znver1-direct,znver1-ieu,znver2-store")
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294
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111
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295 (define_insn_reservation "znver1_load_imov_double_load" 5
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145
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296 (and (eq_attr "cpu" "znver1,znver2")
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111
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297 (and (eq_attr "znver1_decode" "double")
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298 (and (eq_attr "type" "imovx")
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299 (eq_attr "memory" "load"))))
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145
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300 "znver1-double,znver1-load,znver1-ieu|znver1-ieu")
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301
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302 (define_insn_reservation "znver2_load_imov_double_load" 4
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303 (and (eq_attr "cpu" "znver1,znver2")
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304 (and (eq_attr "znver1_decode" "double")
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305 (and (eq_attr "type" "imovx")
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306 (eq_attr "memory" "load"))))
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307 "znver1-double,znver1-load,znver1-ieu|znver1-ieu")
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111
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308
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309 (define_insn_reservation "znver1_load_imov_direct_load" 4
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145
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310 (and (eq_attr "cpu" "znver1,znver2")
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111
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311 (and (eq_attr "type" "imov,imovx")
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312 (eq_attr "memory" "load")))
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313 "znver1-direct,znver1-load")
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314
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315 ;; INTEGER/GENERAL instructions
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316 ;; register/imm operands only: ALU, ICMP, NEG, NOT, ROTATE, ISHIFT, TEST
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317 (define_insn_reservation "znver1_insn" 1
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145
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318 (and (eq_attr "cpu" "znver1,znver2")
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111
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319 (and (eq_attr "type" "alu,icmp,negnot,rotate,rotate1,ishift,ishift1,test,setcc,incdec,icmov")
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320 (eq_attr "memory" "none,unknown")))
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321 "znver1-direct,znver1-ieu")
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322
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323 (define_insn_reservation "znver1_insn_load" 5
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145
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324 (and (eq_attr "cpu" "znver1,znver2")
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111
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325 (and (eq_attr "type" "alu,icmp,negnot,rotate,rotate1,ishift,ishift1,test,setcc,incdec,icmov")
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326 (eq_attr "memory" "load")))
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327 "znver1-direct,znver1-load,znver1-ieu")
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328
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329 (define_insn_reservation "znver1_insn_store" 1
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330 (and (eq_attr "cpu" "znver1")
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331 (and (eq_attr "type" "alu,icmp,negnot,rotate,rotate1,ishift1,test,setcc,incdec")
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332 (eq_attr "memory" "store")))
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333 "znver1-direct,znver1-ieu,znver1-store")
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334
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145
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335 (define_insn_reservation "znver2_insn_store" 1
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336 (and (eq_attr "cpu" "znver2")
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337 (and (eq_attr "type" "alu,icmp,negnot,rotate,rotate1,ishift1,test,setcc,incdec")
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338 (eq_attr "memory" "store")))
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339 "znver1-direct,znver1-ieu,znver2-store")
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340
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111
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341 (define_insn_reservation "znver1_insn_both" 5
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342 (and (eq_attr "cpu" "znver1")
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343 (and (eq_attr "type" "alu,icmp,negnot,rotate,rotate1,ishift1,test,setcc,incdec")
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344 (eq_attr "memory" "both")))
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345 "znver1-direct,znver1-load,znver1-ieu,znver1-store")
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346
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145
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347 (define_insn_reservation "znver2_insn_both" 5
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348 (and (eq_attr "cpu" "znver2")
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349 (and (eq_attr "type" "alu,icmp,negnot,rotate,rotate1,ishift1,test,setcc,incdec")
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350 (eq_attr "memory" "both")))
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351 "znver1-direct,znver1-load,znver1-ieu,znver2-store")
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352
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111
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353 ;; Fix me: Other vector type insns keeping latency 6 as of now.
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354 (define_insn_reservation "znver1_ieu_vector" 6
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355 (and (eq_attr "cpu" "znver1")
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356 (eq_attr "type" "other,str,multi"))
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357 "znver1-vector,znver1-ivector")
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358
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145
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359 (define_insn_reservation "znver2_ieu_vector" 5
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360 (and (eq_attr "cpu" "znver2")
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361 (eq_attr "type" "other,str,multi"))
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|
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362 "znver1-vector,znver2-ivector")
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363
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111
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364 ;; ALU1 register operands.
|
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365 (define_insn_reservation "znver1_alu1_vector" 3
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366 (and (eq_attr "cpu" "znver1")
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|
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367 (and (eq_attr "znver1_decode" "vector")
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368 (and (eq_attr "type" "alu1")
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369 (eq_attr "memory" "none,unknown"))))
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370 "znver1-vector,znver1-ivector")
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371
|
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145
|
372 (define_insn_reservation "znver2_alu1_vector" 3
|
|
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373 (and (eq_attr "cpu" "znver2")
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|
|
374 (and (eq_attr "znver1_decode" "vector")
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375 (and (eq_attr "type" "alu1")
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376 (eq_attr "memory" "none,unknown"))))
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|
|
377 "znver1-vector,znver2-ivector")
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378
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111
|
379 (define_insn_reservation "znver1_alu1_double" 2
|
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145
|
380 (and (eq_attr "cpu" "znver1,znver2")
|
|
111
|
381 (and (eq_attr "znver1_decode" "double")
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|
382 (and (eq_attr "type" "alu1")
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383 (eq_attr "memory" "none,unknown"))))
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|
|
384 "znver1-double,znver1-ieu")
|
|
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385
|
|
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386 (define_insn_reservation "znver1_alu1_direct" 1
|
|
145
|
387 (and (eq_attr "cpu" "znver1,znver2")
|
|
111
|
388 (and (eq_attr "znver1_decode" "direct")
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|
|
389 (and (eq_attr "type" "alu1")
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390 (eq_attr "memory" "none,unknown"))))
|
|
|
391 "znver1-direct,znver1-ieu")
|
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392
|
|
|
393 ;; Branches : Fix me need to model conditional branches.
|
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|
394 (define_insn_reservation "znver1_branch" 1
|
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145
|
395 (and (eq_attr "cpu" "znver1,znver2")
|
|
111
|
396 (and (eq_attr "type" "ibr")
|
|
|
397 (eq_attr "memory" "none")))
|
|
|
398 "znver1-direct")
|
|
|
399
|
|
|
400 ;; Indirect branches check latencies.
|
|
|
401 (define_insn_reservation "znver1_indirect_branch_mem" 6
|
|
|
402 (and (eq_attr "cpu" "znver1")
|
|
|
403 (and (eq_attr "type" "ibr")
|
|
|
404 (eq_attr "memory" "load")))
|
|
|
405 "znver1-vector,znver1-ivector")
|
|
|
406
|
|
145
|
407 (define_insn_reservation "znver2_indirect_branch_mem" 6
|
|
|
408 (and (eq_attr "cpu" "znver2")
|
|
|
409 (and (eq_attr "type" "ibr")
|
|
|
410 (eq_attr "memory" "load")))
|
|
|
411 "znver1-vector,znver2-ivector")
|
|
|
412
|
|
111
|
413 ;; LEA executes in ALU units with 1 cycle latency.
|
|
|
414 (define_insn_reservation "znver1_lea" 1
|
|
145
|
415 (and (eq_attr "cpu" "znver1,znver2")
|
|
111
|
416 (eq_attr "type" "lea"))
|
|
|
417 "znver1-direct,znver1-ieu")
|
|
|
418
|
|
|
419 ;; Other integer instrucions
|
|
|
420 (define_insn_reservation "znver1_idirect" 1
|
|
145
|
421 (and (eq_attr "cpu" "znver1,znver2")
|
|
111
|
422 (and (eq_attr "unit" "integer,unknown")
|
|
|
423 (eq_attr "memory" "none,unknown")))
|
|
|
424 "znver1-direct,znver1-ieu")
|
|
|
425
|
|
|
426 ;; Floating point
|
|
|
427 (define_insn_reservation "znver1_fp_cmov" 6
|
|
145
|
428 (and (eq_attr "cpu" "znver1,znver2")
|
|
111
|
429 (eq_attr "type" "fcmov"))
|
|
|
430 "znver1-vector,znver1-fvector")
|
|
|
431
|
|
|
432 (define_insn_reservation "znver1_fp_mov_direct_load" 8
|
|
145
|
433 (and (eq_attr "cpu" "znver1,znver2")
|
|
111
|
434 (and (eq_attr "znver1_decode" "direct")
|
|
|
435 (and (eq_attr "type" "fmov")
|
|
|
436 (eq_attr "memory" "load"))))
|
|
|
437 "znver1-direct,znver1-load,znver1-fp3|znver1-fp1")
|
|
|
438
|
|
|
439 (define_insn_reservation "znver1_fp_mov_direct_store" 5
|
|
|
440 (and (eq_attr "cpu" "znver1")
|
|
|
441 (and (eq_attr "znver1_decode" "direct")
|
|
|
442 (and (eq_attr "type" "fmov")
|
|
|
443 (eq_attr "memory" "store"))))
|
|
|
444 "znver1-direct,znver1-fp2|znver1-fp3,znver1-store")
|
|
145
|
445 (define_insn_reservation "znver2_fp_mov_direct_store" 5
|
|
|
446 (and (eq_attr "cpu" "znver2")
|
|
|
447 (and (eq_attr "znver1_decode" "direct")
|
|
|
448 (and (eq_attr "type" "fmov")
|
|
|
449 (eq_attr "memory" "store"))))
|
|
|
450 "znver1-direct,znver1-fp2|znver1-fp3,znver2-store")
|
|
111
|
451
|
|
|
452 (define_insn_reservation "znver1_fp_mov_double" 4
|
|
145
|
453 (and (eq_attr "cpu" "znver1,znver2")
|
|
111
|
454 (and (eq_attr "znver1_decode" "double")
|
|
|
455 (and (eq_attr "type" "fmov")
|
|
|
456 (eq_attr "memory" "none"))))
|
|
|
457 "znver1-double,znver1-fp3")
|
|
|
458
|
|
|
459 (define_insn_reservation "znver1_fp_mov_double_load" 12
|
|
|
460 (and (eq_attr "cpu" "znver1")
|
|
|
461 (and (eq_attr "znver1_decode" "double")
|
|
|
462 (and (eq_attr "type" "fmov")
|
|
|
463 (eq_attr "memory" "load"))))
|
|
|
464 "znver1-double,znver1-load,znver1-fp3")
|
|
|
465
|
|
145
|
466 (define_insn_reservation "znver2_fp_mov_double_load" 12
|
|
|
467 (and (eq_attr "cpu" "znver2")
|
|
|
468 (and (eq_attr "znver1_decode" "double")
|
|
|
469 (and (eq_attr "type" "fmov")
|
|
|
470 (eq_attr "memory" "load"))))
|
|
|
471 "znver1-double,znver1-load,znver1-fp3")
|
|
|
472
|
|
111
|
473 (define_insn_reservation "znver1_fp_mov_direct" 1
|
|
145
|
474 (and (eq_attr "cpu" "znver1,znver2")
|
|
111
|
475 (eq_attr "type" "fmov"))
|
|
|
476 "znver1-direct,znver1-fp3")
|
|
|
477
|
|
145
|
478 ;; TODO: AGU?
|
|
111
|
479 (define_insn_reservation "znver1_fp_spc_direct" 5
|
|
145
|
480 (and (eq_attr "cpu" "znver1,znver2")
|
|
111
|
481 (and (eq_attr "type" "fpspc")
|
|
|
482 (eq_attr "memory" "store")))
|
|
|
483 "znver1-direct,znver1-fp3,znver1-fp2")
|
|
|
484
|
|
|
485 (define_insn_reservation "znver1_fp_insn_vector" 6
|
|
|
486 (and (eq_attr "cpu" "znver1")
|
|
|
487 (and (eq_attr "znver1_decode" "vector")
|
|
|
488 (eq_attr "type" "fpspc,mmxcvt,sselog1,ssemul,ssemov")))
|
|
|
489 "znver1-vector,znver1-fvector")
|
|
145
|
490 (define_insn_reservation "znver2_fp_insn_vector" 6
|
|
|
491 (and (eq_attr "cpu" "znver2")
|
|
|
492 (and (eq_attr "znver1_decode" "vector")
|
|
|
493 (eq_attr "type" "fpspc,mmxcvt,sselog1,ssemul,ssemov")))
|
|
|
494 "znver1-vector,znver2-fvector")
|
|
111
|
495
|
|
|
496 ;; FABS
|
|
|
497 (define_insn_reservation "znver1_fp_fsgn" 1
|
|
145
|
498 (and (eq_attr "cpu" "znver1,znver2")
|
|
111
|
499 (eq_attr "type" "fsgn"))
|
|
|
500 "znver1-direct,znver1-fp3")
|
|
|
501
|
|
|
502 (define_insn_reservation "znver1_fp_fcmp" 2
|
|
145
|
503 (and (eq_attr "cpu" "znver1,znver2")
|
|
111
|
504 (and (eq_attr "memory" "none")
|
|
|
505 (and (eq_attr "znver1_decode" "double")
|
|
|
506 (eq_attr "type" "fcmp"))))
|
|
|
507 "znver1-double,znver1-fp0,znver1-fp2")
|
|
|
508
|
|
|
509 (define_insn_reservation "znver1_fp_fcmp_load" 9
|
|
145
|
510 (and (eq_attr "cpu" "znver1,znver2")
|
|
111
|
511 (and (eq_attr "memory" "none")
|
|
|
512 (and (eq_attr "znver1_decode" "double")
|
|
|
513 (eq_attr "type" "fcmp"))))
|
|
|
514 "znver1-double,znver1-load, znver1-fp0,znver1-fp2")
|
|
|
515
|
|
|
516 ;;FADD FSUB FMUL
|
|
|
517 (define_insn_reservation "znver1_fp_op_mul" 5
|
|
145
|
518 (and (eq_attr "cpu" "znver1,znver2")
|
|
111
|
519 (and (eq_attr "type" "fop,fmul")
|
|
|
520 (eq_attr "memory" "none")))
|
|
|
521 "znver1-direct,znver1-fp0*5")
|
|
|
522
|
|
|
523 (define_insn_reservation "znver1_fp_op_mul_load" 12
|
|
145
|
524 (and (eq_attr "cpu" "znver1,znver2")
|
|
111
|
525 (and (eq_attr "type" "fop,fmul")
|
|
|
526 (eq_attr "memory" "load")))
|
|
|
527 "znver1-direct,znver1-load,znver1-fp0*5")
|
|
|
528
|
|
|
529 (define_insn_reservation "znver1_fp_op_imul_load" 16
|
|
145
|
530 (and (eq_attr "cpu" "znver1,znver2")
|
|
111
|
531 (and (eq_attr "type" "fop,fmul")
|
|
|
532 (and (eq_attr "fp_int_src" "true")
|
|
|
533 (eq_attr "memory" "load"))))
|
|
|
534 "znver1-double,znver1-load,znver1-fp3,znver1-fp0")
|
|
|
535
|
|
|
536 (define_insn_reservation "znver1_fp_op_div" 15
|
|
145
|
537 (and (eq_attr "cpu" "znver1,znver2")
|
|
111
|
538 (and (eq_attr "type" "fdiv")
|
|
|
539 (eq_attr "memory" "none")))
|
|
|
540 "znver1-direct,znver1-fp3*15")
|
|
|
541
|
|
|
542 (define_insn_reservation "znver1_fp_op_div_load" 22
|
|
145
|
543 (and (eq_attr "cpu" "znver1,znver2")
|
|
111
|
544 (and (eq_attr "type" "fdiv")
|
|
|
545 (eq_attr "memory" "load")))
|
|
|
546 "znver1-direct,znver1-load,znver1-fp3*15")
|
|
|
547
|
|
|
548 (define_insn_reservation "znver1_fp_op_idiv_load" 27
|
|
|
549 (and (eq_attr "cpu" "znver1")
|
|
|
550 (and (eq_attr "type" "fdiv")
|
|
|
551 (and (eq_attr "fp_int_src" "true")
|
|
|
552 (eq_attr "memory" "load"))))
|
|
|
553 "znver1-double,znver1-load,znver1-fp3*19")
|
|
|
554
|
|
145
|
555 (define_insn_reservation "znver2_fp_op_idiv_load" 26
|
|
|
556 (and (eq_attr "cpu" "znver2")
|
|
|
557 (and (eq_attr "type" "fdiv")
|
|
|
558 (and (eq_attr "fp_int_src" "true")
|
|
|
559 (eq_attr "memory" "load"))))
|
|
|
560 "znver1-double,znver1-load,znver1-fp3*19")
|
|
|
561
|
|
111
|
562 ;; MMX, SSE, SSEn.n, AVX, AVX2 instructions
|
|
|
563 (define_insn_reservation "znver1_fp_insn" 1
|
|
145
|
564 (and (eq_attr "cpu" "znver1,znver2")
|
|
111
|
565 (eq_attr "type" "mmx"))
|
|
|
566 "znver1-direct,znver1-fpu")
|
|
|
567
|
|
|
568 (define_insn_reservation "znver1_mmx_add" 1
|
|
145
|
569 (and (eq_attr "cpu" "znver1,znver2")
|
|
111
|
570 (and (eq_attr "type" "mmxadd")
|
|
|
571 (eq_attr "memory" "none")))
|
|
|
572 "znver1-direct,znver1-fp0|znver1-fp1|znver1-fp3")
|
|
|
573
|
|
|
574 (define_insn_reservation "znver1_mmx_add_load" 8
|
|
145
|
575 (and (eq_attr "cpu" "znver1,znver2")
|
|
111
|
576 (and (eq_attr "type" "mmxadd")
|
|
|
577 (eq_attr "memory" "load")))
|
|
|
578 "znver1-direct,znver1-load,znver1-fp0|znver1-fp1|znver1-fp3")
|
|
|
579
|
|
|
580 (define_insn_reservation "znver1_mmx_cmp" 1
|
|
145
|
581 (and (eq_attr "cpu" "znver1,znver2")
|
|
111
|
582 (and (eq_attr "type" "mmxcmp")
|
|
|
583 (eq_attr "memory" "none")))
|
|
|
584 "znver1-direct,znver1-fp0|znver1-fp3")
|
|
|
585
|
|
|
586 (define_insn_reservation "znver1_mmx_cmp_load" 8
|
|
145
|
587 (and (eq_attr "cpu" "znver1,znver2")
|
|
111
|
588 (and (eq_attr "type" "mmxcmp")
|
|
|
589 (eq_attr "memory" "load")))
|
|
|
590 "znver1-direct,znver1-load,znver1-fp0|znver1-fp3")
|
|
|
591
|
|
|
592 (define_insn_reservation "znver1_mmx_cvt_pck_shuf" 1
|
|
145
|
593 (and (eq_attr "cpu" "znver1,znver2")
|
|
111
|
594 (and (eq_attr "type" "mmxcvt,sseshuf,sseshuf1")
|
|
|
595 (eq_attr "memory" "none")))
|
|
|
596 "znver1-direct,znver1-fp1|znver1-fp2")
|
|
|
597
|
|
|
598 (define_insn_reservation "znver1_mmx_cvt_pck_shuf_load" 8
|
|
145
|
599 (and (eq_attr "cpu" "znver1,znver2")
|
|
111
|
600 (and (eq_attr "type" "mmxcvt,sseshuf,sseshuf1")
|
|
|
601 (eq_attr "memory" "load")))
|
|
|
602 "znver1-direct,znver1-load,znver1-fp1|znver1-fp2")
|
|
|
603
|
|
|
604 (define_insn_reservation "znver1_mmx_shift_move" 1
|
|
145
|
605 (and (eq_attr "cpu" "znver1,znver2")
|
|
111
|
606 (and (eq_attr "type" "mmxshft,mmxmov")
|
|
|
607 (eq_attr "memory" "none")))
|
|
|
608 "znver1-direct,znver1-fp2")
|
|
|
609
|
|
|
610 (define_insn_reservation "znver1_mmx_shift_move_load" 8
|
|
145
|
611 (and (eq_attr "cpu" "znver1,znver2")
|
|
111
|
612 (and (eq_attr "type" "mmxshft,mmxmov")
|
|
|
613 (eq_attr "memory" "load")))
|
|
|
614 "znver1-direct,znver1-load,znver1-fp2")
|
|
|
615
|
|
|
616 (define_insn_reservation "znver1_mmx_move_store" 1
|
|
|
617 (and (eq_attr "cpu" "znver1")
|
|
|
618 (and (eq_attr "type" "mmxshft,mmxmov")
|
|
|
619 (eq_attr "memory" "store,both")))
|
|
|
620 "znver1-direct,znver1-fp2,znver1-store")
|
|
145
|
621 (define_insn_reservation "znver2_mmx_move_store" 1
|
|
|
622 (and (eq_attr "cpu" "znver1")
|
|
|
623 (and (eq_attr "type" "mmxshft,mmxmov")
|
|
|
624 (eq_attr "memory" "store,both")))
|
|
|
625 "znver1-direct,znver1-fp2,znver2-store")
|
|
111
|
626
|
|
|
627 (define_insn_reservation "znver1_mmx_mul" 3
|
|
145
|
628 (and (eq_attr "cpu" "znver1,znver2")
|
|
111
|
629 (and (eq_attr "type" "mmxmul")
|
|
|
630 (eq_attr "memory" "none")))
|
|
|
631 "znver1-direct,znver1-fp0*3")
|
|
|
632
|
|
|
633 (define_insn_reservation "znver1_mmx_load" 10
|
|
145
|
634 (and (eq_attr "cpu" "znver1,znver2")
|
|
111
|
635 (and (eq_attr "type" "mmxmul")
|
|
|
636 (eq_attr "memory" "load")))
|
|
|
637 "znver1-direct,znver1-load,znver1-fp0*3")
|
|
|
638
|
|
145
|
639 ;; TODO
|
|
111
|
640 (define_insn_reservation "znver1_avx256_log" 1
|
|
|
641 (and (eq_attr "cpu" "znver1")
|
|
|
642 (and (eq_attr "mode" "V8SF,V4DF,OI")
|
|
|
643 (and (eq_attr "type" "sselog")
|
|
|
644 (eq_attr "memory" "none"))))
|
|
|
645 "znver1-double,znver1-fpu")
|
|
|
646
|
|
|
647 (define_insn_reservation "znver1_avx256_log_load" 8
|
|
|
648 (and (eq_attr "cpu" "znver1")
|
|
|
649 (and (eq_attr "mode" "V8SF,V4DF,OI")
|
|
|
650 (and (eq_attr "type" "sselog")
|
|
|
651 (eq_attr "memory" "load"))))
|
|
|
652 "znver1-double,znver1-load,znver1-fpu")
|
|
|
653
|
|
|
654 (define_insn_reservation "znver1_sse_log" 1
|
|
145
|
655 (and (eq_attr "cpu" "znver1,znver2")
|
|
111
|
656 (and (eq_attr "type" "sselog")
|
|
|
657 (eq_attr "memory" "none")))
|
|
|
658 "znver1-direct,znver1-fpu")
|
|
|
659
|
|
|
660 (define_insn_reservation "znver1_sse_log_load" 8
|
|
145
|
661 (and (eq_attr "cpu" "znver1,znver2")
|
|
111
|
662 (and (eq_attr "type" "sselog")
|
|
|
663 (eq_attr "memory" "load")))
|
|
|
664 "znver1-direct,znver1-load,znver1-fpu")
|
|
|
665
|
|
|
666 (define_insn_reservation "znver1_avx256_log1" 1
|
|
|
667 (and (eq_attr "cpu" "znver1")
|
|
|
668 (and (eq_attr "mode" "V8SF,V4DF,OI")
|
|
|
669 (and (eq_attr "type" "sselog1")
|
|
|
670 (eq_attr "memory" "none"))))
|
|
|
671 "znver1-double,znver1-fp1|znver1-fp2")
|
|
|
672
|
|
|
673 (define_insn_reservation "znver1_avx256_log1_load" 8
|
|
|
674 (and (eq_attr "cpu" "znver1")
|
|
|
675 (and (eq_attr "mode" "V8SF,V4DF,OI")
|
|
|
676 (and (eq_attr "type" "sselog1")
|
|
|
677 (eq_attr "memory" "!none"))))
|
|
|
678 "znver1-double,znver1-load,znver1-fp1|znver1-fp2")
|
|
|
679
|
|
|
680 (define_insn_reservation "znver1_sse_log1" 1
|
|
145
|
681 (and (eq_attr "cpu" "znver1,znver2")
|
|
111
|
682 (and (eq_attr "type" "sselog1")
|
|
|
683 (eq_attr "memory" "none")))
|
|
|
684 "znver1-direct,znver1-fp1|znver1-fp2")
|
|
|
685
|
|
|
686 (define_insn_reservation "znver1_sse_log1_load" 8
|
|
145
|
687 (and (eq_attr "cpu" "znver1,znver2")
|
|
111
|
688 (and (eq_attr "type" "sselog1")
|
|
|
689 (eq_attr "memory" "!none")))
|
|
|
690 "znver1-direct,znver1-load,znver1-fp1|znver1-fp2")
|
|
|
691
|
|
|
692 (define_insn_reservation "znver1_sse_comi" 1
|
|
|
693 (and (eq_attr "cpu" "znver1")
|
|
|
694 (and (eq_attr "mode" "SF,DF,V4SF,V2DF")
|
|
|
695 (and (eq_attr "prefix" "!vex")
|
|
|
696 (and (eq_attr "prefix_extra" "0")
|
|
|
697 (and (eq_attr "type" "ssecomi")
|
|
|
698 (eq_attr "memory" "none"))))))
|
|
|
699 "znver1-direct,znver1-fp0|znver1-fp1")
|
|
|
700
|
|
|
701 (define_insn_reservation "znver1_sse_comi_load" 8
|
|
145
|
702 (and (ior (and (eq_attr "cpu" "znver1")
|
|
|
703 (eq_attr "mode" "SF,DF,V4SF,V2DF"))
|
|
|
704 (eq_attr "cpu" "znver2"))
|
|
|
705 (and (eq_attr "prefix_extra" "0")
|
|
|
706 (and (eq_attr "type" "ssecomi")
|
|
|
707 (eq_attr "memory" "load"))))
|
|
111
|
708 "znver1-direct,znver1-load,znver1-fp0|znver1-fp1")
|
|
|
709
|
|
|
710 (define_insn_reservation "znver1_sse_comi_double" 2
|
|
145
|
711 (and (ior (and (eq_attr "cpu" "znver1")
|
|
|
712 (eq_attr "mode" "V4SF,V2DF,TI"))
|
|
|
713 (eq_attr "cpu" "znver2"))
|
|
|
714 (and (eq_attr "prefix" "vex")
|
|
|
715 (and (eq_attr "prefix_extra" "0")
|
|
|
716 (and (eq_attr "type" "ssecomi")
|
|
|
717 (eq_attr "memory" "none")))))
|
|
111
|
718 "znver1-double,znver1-fp0|znver1-fp1")
|
|
|
719
|
|
|
720 (define_insn_reservation "znver1_sse_comi_double_load" 10
|
|
145
|
721 (and (ior (and (eq_attr "cpu" "znver1")
|
|
|
722 (eq_attr "mode" "V4SF,V2DF,TI"))
|
|
|
723 (eq_attr "cpu" "znver2"))
|
|
|
724 (and (eq_attr "prefix" "vex")
|
|
|
725 (and (eq_attr "prefix_extra" "0")
|
|
|
726 (and (eq_attr "type" "ssecomi")
|
|
|
727 (eq_attr "memory" "load")))))
|
|
111
|
728 "znver1-double,znver1-load,znver1-fp0|znver1-fp1")
|
|
|
729
|
|
|
730 (define_insn_reservation "znver1_sse_test" 1
|
|
145
|
731 (and (ior (and (eq_attr "cpu" "znver1")
|
|
|
732 (eq_attr "mode" "SF,DF,V4SF,V2DF,TI"))
|
|
|
733 (eq_attr "cpu" "znver2"))
|
|
|
734 (and (eq_attr "prefix_extra" "1")
|
|
|
735 (and (eq_attr "type" "ssecomi")
|
|
|
736 (eq_attr "memory" "none"))))
|
|
111
|
737 "znver1-direct,znver1-fp1|znver1-fp2")
|
|
|
738
|
|
|
739 (define_insn_reservation "znver1_sse_test_load" 8
|
|
145
|
740 (and (ior (and (eq_attr "cpu" "znver1")
|
|
|
741 (eq_attr "mode" "SF,DF,V4SF,V2DF,TI"))
|
|
|
742 (eq_attr "cpu" "znver2"))
|
|
|
743 (and (eq_attr "prefix_extra" "1")
|
|
|
744 (and (eq_attr "type" "ssecomi")
|
|
|
745 (eq_attr "memory" "load"))))
|
|
111
|
746 "znver1-direct,znver1-load,znver1-fp1|znver1-fp2")
|
|
|
747
|
|
|
748 ;; SSE moves
|
|
|
749 ;; Fix me: Need to revist this again some of the moves may be restricted
|
|
|
750 ;; to some fpu pipes.
|
|
|
751 (define_insn_reservation "znver1_sse_mov" 2
|
|
|
752 (and (eq_attr "cpu" "znver1")
|
|
|
753 (and (eq_attr "mode" "SI")
|
|
|
754 (and (eq_attr "isa" "avx")
|
|
|
755 (and (eq_attr "type" "ssemov")
|
|
|
756 (eq_attr "memory" "none")))))
|
|
|
757 "znver1-direct,znver1-ieu0")
|
|
|
758
|
|
145
|
759 (define_insn_reservation "znver2_sse_mov" 1
|
|
|
760 (and (eq_attr "cpu" "znver2")
|
|
|
761 (and (eq_attr "mode" "SI")
|
|
|
762 (and (eq_attr "isa" "avx")
|
|
|
763 (and (eq_attr "type" "ssemov")
|
|
|
764 (eq_attr "memory" "none")))))
|
|
|
765 "znver1-direct,znver1-ieu0")
|
|
|
766
|
|
111
|
767 (define_insn_reservation "znver1_avx_mov" 2
|
|
|
768 (and (eq_attr "cpu" "znver1")
|
|
|
769 (and (eq_attr "mode" "TI")
|
|
|
770 (and (eq_attr "isa" "avx")
|
|
|
771 (and (eq_attr "type" "ssemov")
|
|
|
772 (and (match_operand:SI 1 "register_operand")
|
|
|
773 (eq_attr "memory" "none"))))))
|
|
|
774 "znver1-direct,znver1-ieu2")
|
|
|
775
|
|
145
|
776 (define_insn_reservation "znver2_avx_mov" 1
|
|
|
777 (and (eq_attr "cpu" "znver2")
|
|
|
778 (and (eq_attr "mode" "TI")
|
|
|
779 (and (eq_attr "isa" "avx")
|
|
|
780 (and (eq_attr "type" "ssemov")
|
|
|
781 (and (match_operand:SI 1 "register_operand")
|
|
|
782 (eq_attr "memory" "none"))))))
|
|
|
783 "znver1-direct,znver1-ieu2")
|
|
|
784
|
|
111
|
785 (define_insn_reservation "znver1_sseavx_mov" 1
|
|
145
|
786 (and (ior (and (eq_attr "cpu" "znver1")
|
|
|
787 (eq_attr "mode" "SF,DF,V4SF,V2DF,TI"))
|
|
|
788 (eq_attr "cpu" "znver2"))
|
|
|
789 (and (eq_attr "type" "ssemov")
|
|
|
790 (eq_attr "memory" "none")))
|
|
111
|
791 "znver1-direct,znver1-fpu")
|
|
|
792
|
|
|
793 (define_insn_reservation "znver1_sseavx_mov_store" 1
|
|
|
794 (and (eq_attr "cpu" "znver1")
|
|
|
795 (and (eq_attr "mode" "SF,DF,V4SF,V2DF,TI")
|
|
|
796 (and (eq_attr "type" "ssemov")
|
|
|
797 (eq_attr "memory" "store"))))
|
|
|
798 "znver1-direct,znver1-fpu,znver1-store")
|
|
145
|
799 (define_insn_reservation "znver2_sseavx_mov_store" 1
|
|
|
800 (and (eq_attr "cpu" "znver2")
|
|
|
801 (and (eq_attr "type" "ssemov")
|
|
|
802 (eq_attr "memory" "store")))
|
|
|
803 "znver1-direct,znver1-fpu,znver2-store")
|
|
111
|
804
|
|
|
805 (define_insn_reservation "znver1_sseavx_mov_load" 8
|
|
145
|
806 (and (ior (and (eq_attr "cpu" "znver1")
|
|
|
807 (eq_attr "mode" "SF,DF,V4SF,V2DF,TI"))
|
|
|
808 (eq_attr "cpu" "znver2"))
|
|
|
809 (and (eq_attr "type" "ssemov")
|
|
|
810 (eq_attr "memory" "load")))
|
|
111
|
811 "znver1-direct,znver1-load,znver1-fpu")
|
|
|
812
|
|
|
813 (define_insn_reservation "znver1_avx256_mov" 1
|
|
|
814 (and (eq_attr "cpu" "znver1")
|
|
|
815 (and (eq_attr "mode" "V8SF,V4DF,OI")
|
|
|
816 (and (eq_attr "type" "ssemov")
|
|
|
817 (eq_attr "memory" "none"))))
|
|
|
818 "znver1-double,znver1-fpu")
|
|
|
819
|
|
|
820 (define_insn_reservation "znver1_avx256_mov_store" 1
|
|
|
821 (and (eq_attr "cpu" "znver1")
|
|
|
822 (and (eq_attr "mode" "V8SF,V4DF,OI")
|
|
|
823 (and (eq_attr "type" "ssemov")
|
|
|
824 (eq_attr "memory" "store"))))
|
|
|
825 "znver1-double,znver1-fpu,znver1-store")
|
|
|
826
|
|
|
827 (define_insn_reservation "znver1_avx256_mov_load" 8
|
|
|
828 (and (eq_attr "cpu" "znver1")
|
|
|
829 (and (eq_attr "mode" "V8SF,V4DF,OI")
|
|
|
830 (and (eq_attr "type" "ssemov")
|
|
|
831 (eq_attr "memory" "load"))))
|
|
|
832 "znver1-double,znver1-load,znver1-fpu")
|
|
|
833
|
|
|
834 ;; SSE add
|
|
|
835 (define_insn_reservation "znver1_sseavx_add" 3
|
|
145
|
836 (and (ior (and (eq_attr "cpu" "znver1")
|
|
|
837 (eq_attr "mode" "SF,DF,V4SF,V2DF,TI"))
|
|
|
838 (eq_attr "cpu" "znver2"))
|
|
|
839 (and (eq_attr "type" "sseadd")
|
|
|
840 (eq_attr "memory" "none")))
|
|
111
|
841 "znver1-direct,znver1-fp2|znver1-fp3")
|
|
|
842
|
|
|
843 (define_insn_reservation "znver1_sseavx_add_load" 10
|
|
145
|
844 (and (ior (and (eq_attr "cpu" "znver1")
|
|
|
845 (eq_attr "mode" "SF,DF,V4SF,V2DF,TI"))
|
|
|
846 (eq_attr "cpu" "znver2"))
|
|
|
847 (and (eq_attr "type" "sseadd")
|
|
|
848 (eq_attr "memory" "load")))
|
|
111
|
849 "znver1-direct,znver1-load,znver1-fp2|znver1-fp3")
|
|
|
850
|
|
|
851 (define_insn_reservation "znver1_avx256_add" 3
|
|
|
852 (and (eq_attr "cpu" "znver1")
|
|
|
853 (and (eq_attr "mode" "V8SF,V4DF,OI")
|
|
|
854 (and (eq_attr "type" "sseadd")
|
|
|
855 (eq_attr "memory" "none"))))
|
|
|
856 "znver1-double,znver1-fp2|znver1-fp3")
|
|
|
857
|
|
|
858 (define_insn_reservation "znver1_avx256_add_load" 10
|
|
|
859 (and (eq_attr "cpu" "znver1")
|
|
|
860 (and (eq_attr "mode" "V8SF,V4DF,OI")
|
|
|
861 (and (eq_attr "type" "sseadd")
|
|
|
862 (eq_attr "memory" "load"))))
|
|
|
863 "znver1-double,znver1-load,znver1-fp2|znver1-fp3")
|
|
|
864
|
|
|
865 (define_insn_reservation "znver1_sseavx_fma" 5
|
|
145
|
866 (and (ior (and (eq_attr "cpu" "znver1")
|
|
|
867 (eq_attr "mode" "SF,DF,V4SF,V2DF"))
|
|
|
868 (eq_attr "cpu" "znver2"))
|
|
|
869 (and (eq_attr "type" "ssemuladd")
|
|
|
870 (eq_attr "memory" "none")))
|
|
111
|
871 "znver1-direct,znver1-fp0|znver1-fp1")
|
|
|
872
|
|
|
873 (define_insn_reservation "znver1_sseavx_fma_load" 12
|
|
145
|
874 (and (ior (and (eq_attr "cpu" "znver1")
|
|
|
875 (eq_attr "mode" "SF,DF,V4SF,V2DF"))
|
|
|
876 (eq_attr "cpu" "znver2"))
|
|
|
877 (and (eq_attr "type" "ssemuladd")
|
|
|
878 (eq_attr "memory" "load")))
|
|
111
|
879 "znver1-direct,znver1-load,znver1-fp0|znver1-fp1")
|
|
|
880
|
|
|
881 (define_insn_reservation "znver1_avx256_fma" 5
|
|
|
882 (and (eq_attr "cpu" "znver1")
|
|
|
883 (and (eq_attr "mode" "V8SF,V4DF")
|
|
|
884 (and (eq_attr "type" "ssemuladd")
|
|
|
885 (eq_attr "memory" "none"))))
|
|
|
886 "znver1-double,znver1-fp0|znver1-fp1")
|
|
|
887
|
|
|
888 (define_insn_reservation "znver1_avx256_fma_load" 12
|
|
|
889 (and (eq_attr "cpu" "znver1")
|
|
|
890 (and (eq_attr "mode" "V8SF,V4DF")
|
|
|
891 (and (eq_attr "type" "ssemuladd")
|
|
|
892 (eq_attr "memory" "load"))))
|
|
|
893 "znver1-double,znver1-load,znver1-fp0|znver1-fp1")
|
|
|
894
|
|
|
895 (define_insn_reservation "znver1_sseavx_iadd" 1
|
|
145
|
896 (and (ior (and (eq_attr "cpu" "znver1")
|
|
|
897 (eq_attr "mode" "DI,TI"))
|
|
|
898 (eq_attr "cpu" "znver2"))
|
|
|
899 (and (eq_attr "type" "sseiadd")
|
|
|
900 (eq_attr "memory" "none")))
|
|
111
|
901 "znver1-direct,znver1-fp0|znver1-fp1|znver1-fp3")
|
|
|
902
|
|
|
903 (define_insn_reservation "znver1_sseavx_iadd_load" 8
|
|
145
|
904 (and (ior (and (eq_attr "cpu" "znver1")
|
|
|
905 (eq_attr "mode" "DI,TI"))
|
|
|
906 (eq_attr "cpu" "znver2"))
|
|
|
907 (and (eq_attr "type" "sseiadd")
|
|
|
908 (eq_attr "memory" "load")))
|
|
111
|
909 "znver1-direct,znver1-load,znver1-fp0|znver1-fp1|znver1-fp3")
|
|
|
910
|
|
|
911 (define_insn_reservation "znver1_avx256_iadd" 1
|
|
|
912 (and (eq_attr "cpu" "znver1")
|
|
|
913 (and (eq_attr "mode" "OI")
|
|
|
914 (and (eq_attr "type" "sseiadd")
|
|
|
915 (eq_attr "memory" "none"))))
|
|
|
916 "znver1-double,znver1-fp0|znver1-fp1|znver1-fp3")
|
|
|
917
|
|
|
918 (define_insn_reservation "znver1_avx256_iadd_load" 8
|
|
|
919 (and (eq_attr "cpu" "znver1")
|
|
|
920 (and (eq_attr "mode" "OI")
|
|
|
921 (and (eq_attr "type" "sseiadd")
|
|
|
922 (eq_attr "memory" "load"))))
|
|
|
923 "znver1-double,znver1-load,znver1-fp0|znver1-fp1|znver1-fp3")
|
|
|
924
|
|
|
925 ;; SSE conversions.
|
|
|
926 (define_insn_reservation "znver1_ssecvtsf_si_load" 12
|
|
145
|
927 (and (eq_attr "cpu" "znver1,znver2")
|
|
111
|
928 (and (eq_attr "mode" "SI")
|
|
|
929 (and (eq_attr "type" "sseicvt")
|
|
|
930 (and (match_operand:SF 1 "memory_operand")
|
|
|
931 (eq_attr "memory" "load")))))
|
|
|
932 "znver1-double,znver1-load,znver1-fp3,znver1-ieu0")
|
|
|
933
|
|
|
934 (define_insn_reservation "znver1_ssecvtdf_si" 5
|
|
|
935 (and (eq_attr "cpu" "znver1")
|
|
|
936 (and (eq_attr "mode" "SI")
|
|
|
937 (and (match_operand:DF 1 "register_operand")
|
|
|
938 (and (eq_attr "type" "sseicvt")
|
|
|
939 (eq_attr "memory" "none")))))
|
|
|
940 "znver1-double,znver1-fp3,znver1-ieu0")
|
|
145
|
941 (define_insn_reservation "znver2_ssecvtdf_si" 4
|
|
|
942 (and (eq_attr "cpu" "znver2")
|
|
|
943 (and (eq_attr "mode" "SI")
|
|
|
944 (and (match_operand:DF 1 "register_operand")
|
|
|
945 (and (eq_attr "type" "sseicvt")
|
|
|
946 (eq_attr "memory" "none")))))
|
|
|
947 "znver1-double,znver1-fp3,znver1-ieu0")
|
|
111
|
948
|
|
|
949 (define_insn_reservation "znver1_ssecvtdf_si_load" 12
|
|
|
950 (and (eq_attr "cpu" "znver1")
|
|
|
951 (and (eq_attr "mode" "SI")
|
|
|
952 (and (eq_attr "type" "sseicvt")
|
|
|
953 (and (match_operand:DF 1 "memory_operand")
|
|
|
954 (eq_attr "memory" "load")))))
|
|
|
955 "znver1-double,znver1-load,znver1-fp3,znver1-ieu0")
|
|
|
956
|
|
145
|
957 (define_insn_reservation "znver2_ssecvtdf_si_load" 11
|
|
|
958 (and (eq_attr "cpu" "znver2")
|
|
|
959 (and (eq_attr "mode" "SI")
|
|
|
960 (and (eq_attr "type" "sseicvt")
|
|
|
961 (and (match_operand:DF 1 "memory_operand")
|
|
|
962 (eq_attr "memory" "load")))))
|
|
|
963 "znver1-double,znver1-load,znver1-fp3,znver1-ieu0")
|
|
|
964
|
|
111
|
965 ;; All other used ssecvt fp3 pipes
|
|
|
966 ;; Check: Need to revisit this again.
|
|
|
967 ;; Some SSE converts may use different pipe combinations.
|
|
|
968 (define_insn_reservation "znver1_ssecvt" 4
|
|
|
969 (and (eq_attr "cpu" "znver1")
|
|
|
970 (and (eq_attr "type" "ssecvt")
|
|
|
971 (eq_attr "memory" "none")))
|
|
|
972 "znver1-direct,znver1-fp3")
|
|
|
973
|
|
145
|
974 (define_insn_reservation "znver2_ssecvt" 3
|
|
|
975 (and (eq_attr "cpu" "znver2")
|
|
|
976 (and (eq_attr "type" "ssecvt")
|
|
|
977 (eq_attr "memory" "none")))
|
|
|
978 "znver1-direct,znver1-fp3")
|
|
|
979
|
|
111
|
980 (define_insn_reservation "znver1_ssecvt_load" 11
|
|
|
981 (and (eq_attr "cpu" "znver1")
|
|
|
982 (and (eq_attr "type" "ssecvt")
|
|
|
983 (eq_attr "memory" "load")))
|
|
|
984 "znver1-direct,znver1-load,znver1-fp3")
|
|
|
985
|
|
145
|
986 (define_insn_reservation "znver2_ssecvt_load" 11
|
|
|
987 (and (eq_attr "cpu" "znver2")
|
|
|
988 (and (eq_attr "type" "ssecvt")
|
|
|
989 (eq_attr "memory" "load")))
|
|
|
990 "znver1-direct,znver1-load,znver1-fp3")
|
|
|
991
|
|
111
|
992 ;; SSE div
|
|
|
993 (define_insn_reservation "znver1_ssediv_ss_ps" 10
|
|
145
|
994 (and (ior (and (eq_attr "cpu" "znver1")
|
|
|
995 (eq_attr "mode" "V4SF,SF"))
|
|
|
996 (and (eq_attr "cpu" "znver2")
|
|
|
997 (eq_attr "mode" "V8SF,V4SF,SF")))
|
|
|
998 (and (eq_attr "type" "ssediv")
|
|
|
999 (eq_attr "memory" "none")))
|
|
111
|
1000 "znver1-direct,znver1-fp3*10")
|
|
|
1001
|
|
|
1002 (define_insn_reservation "znver1_ssediv_ss_ps_load" 17
|
|
145
|
1003 (and (ior (and (eq_attr "cpu" "znver1")
|
|
|
1004 (eq_attr "mode" "V4SF,SF"))
|
|
|
1005 (and (eq_attr "cpu" "znver2")
|
|
|
1006 (eq_attr "mode" "V8SF,V4SF,SF")))
|
|
|
1007 (and (eq_attr "type" "ssediv")
|
|
|
1008 (eq_attr "memory" "load")))
|
|
111
|
1009 "znver1-direct,znver1-load,znver1-fp3*10")
|
|
|
1010
|
|
|
1011 (define_insn_reservation "znver1_ssediv_sd_pd" 13
|
|
145
|
1012 (and (ior (and (eq_attr "cpu" "znver1")
|
|
|
1013 (eq_attr "mode" "V2DF,DF"))
|
|
|
1014 (and (eq_attr "cpu" "znver2")
|
|
|
1015 (eq_attr "mode" "V4DF,V2DF,DF")))
|
|
|
1016 (and (eq_attr "type" "ssediv")
|
|
|
1017 (eq_attr "memory" "none")))
|
|
111
|
1018 "znver1-direct,znver1-fp3*13")
|
|
|
1019
|
|
|
1020 (define_insn_reservation "znver1_ssediv_sd_pd_load" 20
|
|
145
|
1021 (and (ior (and (eq_attr "cpu" "znver1")
|
|
|
1022 (eq_attr "mode" "V2DF,DF"))
|
|
|
1023 (and (eq_attr "cpu" "znver2")
|
|
|
1024 (eq_attr "mode" "V4DF,V2DF,DF")))
|
|
|
1025 (and (eq_attr "type" "ssediv")
|
|
|
1026 (eq_attr "memory" "load")))
|
|
111
|
1027 "znver1-direct,znver1-load,znver1-fp3*13")
|
|
|
1028
|
|
|
1029 (define_insn_reservation "znver1_ssediv_avx256_ps" 12
|
|
|
1030 (and (eq_attr "cpu" "znver1")
|
|
|
1031 (and (eq_attr "mode" "V8SF")
|
|
|
1032 (and (eq_attr "memory" "none")
|
|
|
1033 (eq_attr "type" "ssediv"))))
|
|
|
1034 "znver1-double,znver1-fp3*12")
|
|
|
1035
|
|
|
1036 (define_insn_reservation "znver1_ssediv_avx256_ps_load" 19
|
|
|
1037 (and (eq_attr "cpu" "znver1")
|
|
|
1038 (and (eq_attr "mode" "V8SF")
|
|
|
1039 (and (eq_attr "type" "ssediv")
|
|
|
1040 (eq_attr "memory" "load"))))
|
|
|
1041 "znver1-double,znver1-load,znver1-fp3*12")
|
|
|
1042
|
|
|
1043 (define_insn_reservation "znver1_ssediv_avx256_pd" 15
|
|
|
1044 (and (eq_attr "cpu" "znver1")
|
|
|
1045 (and (eq_attr "mode" "V4DF")
|
|
|
1046 (and (eq_attr "type" "ssediv")
|
|
|
1047 (eq_attr "memory" "none"))))
|
|
|
1048 "znver1-double,znver1-fp3*15")
|
|
|
1049
|
|
|
1050 (define_insn_reservation "znver1_ssediv_avx256_pd_load" 22
|
|
|
1051 (and (eq_attr "cpu" "znver1")
|
|
|
1052 (and (eq_attr "mode" "V4DF")
|
|
|
1053 (and (eq_attr "type" "ssediv")
|
|
|
1054 (eq_attr "memory" "load"))))
|
|
|
1055 "znver1-double,znver1-load,znver1-fp3*15")
|
|
|
1056 ;; SSE MUL
|
|
|
1057 (define_insn_reservation "znver1_ssemul_ss_ps" 3
|
|
145
|
1058 (and (ior (and (eq_attr "cpu" "znver1")
|
|
|
1059 (eq_attr "mode" "V4SF,SF"))
|
|
|
1060 (and (eq_attr "cpu" "znver2")
|
|
|
1061 (eq_attr "mode" "V8SF,V4SF,SF,V4DF,V2DF,DF")))
|
|
|
1062 (and (eq_attr "type" "ssemul")
|
|
|
1063 (eq_attr "memory" "none")))
|
|
111
|
1064 "znver1-direct,(znver1-fp0|znver1-fp1)*3")
|
|
|
1065
|
|
|
1066 (define_insn_reservation "znver1_ssemul_ss_ps_load" 10
|
|
145
|
1067 (and (ior (and (eq_attr "cpu" "znver1")
|
|
|
1068 (eq_attr "mode" "V4SF,SF"))
|
|
|
1069 (and (eq_attr "cpu" "znver2")
|
|
|
1070 (eq_attr "mode" "V8SF,V4SF,SF")))
|
|
|
1071 (and (eq_attr "type" "ssemul")
|
|
|
1072 (eq_attr "memory" "load")))
|
|
111
|
1073 "znver1-direct,znver1-load,(znver1-fp0|znver1-fp1)*3")
|
|
|
1074
|
|
|
1075 (define_insn_reservation "znver1_ssemul_avx256_ps" 3
|
|
|
1076 (and (eq_attr "cpu" "znver1")
|
|
|
1077 (and (eq_attr "mode" "V8SF")
|
|
|
1078 (and (eq_attr "type" "ssemul")
|
|
|
1079 (eq_attr "memory" "none"))))
|
|
|
1080 "znver1-double,(znver1-fp0|znver1-fp1)*3")
|
|
|
1081
|
|
|
1082 (define_insn_reservation "znver1_ssemul_avx256_ps_load" 10
|
|
|
1083 (and (eq_attr "cpu" "znver1")
|
|
|
1084 (and (eq_attr "mode" "V8SF")
|
|
|
1085 (and (eq_attr "type" "ssemul")
|
|
|
1086 (eq_attr "memory" "load"))))
|
|
|
1087 "znver1-double,znver1-load,(znver1-fp0|znver1-fp1)*3")
|
|
|
1088
|
|
|
1089 (define_insn_reservation "znver1_ssemul_sd_pd" 4
|
|
|
1090 (and (eq_attr "cpu" "znver1")
|
|
|
1091 (and (eq_attr "mode" "V2DF,DF")
|
|
|
1092 (and (eq_attr "type" "ssemul")
|
|
|
1093 (eq_attr "memory" "none"))))
|
|
|
1094 "znver1-direct,(znver1-fp0|znver1-fp1)*4")
|
|
|
1095
|
|
|
1096 (define_insn_reservation "znver1_ssemul_sd_pd_load" 11
|
|
|
1097 (and (eq_attr "cpu" "znver1")
|
|
|
1098 (and (eq_attr "mode" "V2DF,DF")
|
|
|
1099 (and (eq_attr "type" "ssemul")
|
|
|
1100 (eq_attr "memory" "load"))))
|
|
|
1101 "znver1-direct,znver1-load,(znver1-fp0|znver1-fp1)*4")
|
|
|
1102
|
|
145
|
1103 (define_insn_reservation "znver2_ssemul_sd_pd" 3
|
|
|
1104 (and (eq_attr "cpu" "znver2")
|
|
|
1105 (and (eq_attr "type" "ssemul")
|
|
|
1106 (eq_attr "memory" "none")))
|
|
|
1107 "znver1-direct,(znver1-fp0|znver1-fp1)*3")
|
|
|
1108
|
|
|
1109 (define_insn_reservation "znver2_ssemul_sd_pd_load" 10
|
|
|
1110 (and (eq_attr "cpu" "znver2")
|
|
|
1111 (and (eq_attr "type" "ssemul")
|
|
|
1112 (eq_attr "memory" "load")))
|
|
|
1113 "znver1-direct,znver1-load,(znver1-fp0|znver1-fp1)*3")
|
|
|
1114
|
|
111
|
1115 (define_insn_reservation "znver1_ssemul_avx256_pd" 5
|
|
|
1116 (and (eq_attr "cpu" "znver1")
|
|
|
1117 (and (eq_attr "mode" "V4DF")
|
|
145
|
1118 (and (eq_attr "type" "ssemul")
|
|
|
1119 (eq_attr "memory" "none"))))
|
|
111
|
1120 "znver1-double,(znver1-fp0|znver1-fp1)*4")
|
|
|
1121
|
|
|
1122 (define_insn_reservation "znver1_ssemul_avx256_pd_load" 12
|
|
|
1123 (and (eq_attr "cpu" "znver1")
|
|
|
1124 (and (eq_attr "mode" "V4DF")
|
|
|
1125 (and (eq_attr "type" "ssemul")
|
|
|
1126 (eq_attr "memory" "load"))))
|
|
|
1127 "znver1-double,znver1-load,(znver1-fp0|znver1-fp1)*4")
|
|
|
1128
|
|
|
1129 ;;SSE imul
|
|
|
1130 (define_insn_reservation "znver1_sseimul" 3
|
|
145
|
1131 (and (ior (and (eq_attr "cpu" "znver1")
|
|
|
1132 (eq_attr "mode" "TI"))
|
|
|
1133 (and (eq_attr "cpu" "znver2")
|
|
|
1134 (eq_attr "mode" "TI,OI")))
|
|
|
1135 (and (eq_attr "type" "sseimul")
|
|
|
1136 (eq_attr "memory" "none")))
|
|
111
|
1137 "znver1-direct,znver1-fp0*3")
|
|
|
1138
|
|
|
1139 (define_insn_reservation "znver1_sseimul_avx256" 4
|
|
145
|
1140 (and (eq_attr "cpu" "znver1,znver2")
|
|
111
|
1141 (and (eq_attr "mode" "OI")
|
|
|
1142 (and (eq_attr "type" "sseimul")
|
|
|
1143 (eq_attr "memory" "none"))))
|
|
|
1144 "znver1-double,znver1-fp0*4")
|
|
|
1145
|
|
|
1146 (define_insn_reservation "znver1_sseimul_load" 10
|
|
145
|
1147 (and (ior (and (eq_attr "cpu" "znver1")
|
|
|
1148 (eq_attr "mode" "TI"))
|
|
|
1149 (and (eq_attr "cpu" "znver2")
|
|
|
1150 (eq_attr "mode" "TI,OI")))
|
|
|
1151 (and (eq_attr "type" "sseimul")
|
|
|
1152 (eq_attr "memory" "load")))
|
|
111
|
1153 "znver1-direct,znver1-load,znver1-fp0*3")
|
|
|
1154
|
|
|
1155 (define_insn_reservation "znver1_sseimul_avx256_load" 11
|
|
145
|
1156 (and (eq_attr "cpu" "znver1,znver2")
|
|
111
|
1157 (and (eq_attr "mode" "OI")
|
|
|
1158 (and (eq_attr "type" "sseimul")
|
|
|
1159 (eq_attr "memory" "load"))))
|
|
|
1160 "znver1-double,znver1-load,znver1-fp0*4")
|
|
|
1161
|
|
|
1162 (define_insn_reservation "znver1_sseimul_di" 3
|
|
145
|
1163 (and (eq_attr "cpu" "znver1,znver2")
|
|
111
|
1164 (and (eq_attr "mode" "DI")
|
|
|
1165 (and (eq_attr "memory" "none")
|
|
|
1166 (eq_attr "type" "sseimul"))))
|
|
|
1167 "znver1-direct,znver1-fp0*3")
|
|
|
1168
|
|
|
1169 (define_insn_reservation "znver1_sseimul_load_di" 10
|
|
145
|
1170 (and (eq_attr "cpu" "znver1,znver2")
|
|
111
|
1171 (and (eq_attr "mode" "DI")
|
|
|
1172 (and (eq_attr "type" "sseimul")
|
|
|
1173 (eq_attr "memory" "load"))))
|
|
|
1174 "znver1-direct,znver1-load,znver1-fp0*3")
|
|
|
1175
|
|
|
1176 ;; SSE compares
|
|
|
1177 (define_insn_reservation "znver1_sse_cmp" 1
|
|
145
|
1178 (and (ior (and (eq_attr "cpu" "znver1")
|
|
|
1179 (eq_attr "mode" "SF,DF,V4SF,V2DF"))
|
|
|
1180 (and (eq_attr "cpu" "znver2")
|
|
|
1181 (eq_attr "mode" "SF,DF,V4SF,V2DF,V8SF,V4DF")))
|
|
|
1182 (and (eq_attr "type" "ssecmp")
|
|
|
1183 (eq_attr "memory" "none")))
|
|
111
|
1184 "znver1-direct,znver1-fp0|znver1-fp1")
|
|
|
1185
|
|
|
1186 (define_insn_reservation "znver1_sse_cmp_load" 8
|
|
145
|
1187 (and (ior (and (eq_attr "cpu" "znver1")
|
|
|
1188 (eq_attr "mode" "SF,DF,V4SF,V2DF"))
|
|
|
1189 (and (eq_attr "cpu" "znver2")
|
|
|
1190 (eq_attr "mode" "SF,DF,V4SF,V2DF,V8SF,V4DF")))
|
|
|
1191 (and (eq_attr "type" "ssecmp")
|
|
|
1192 (eq_attr "memory" "load")))
|
|
111
|
1193 "znver1-direct,znver1-load,znver1-fp0|znver1-fp1")
|
|
|
1194
|
|
|
1195 (define_insn_reservation "znver1_sse_cmp_avx256" 1
|
|
|
1196 (and (eq_attr "cpu" "znver1")
|
|
|
1197 (and (eq_attr "mode" "V8SF,V4DF")
|
|
|
1198 (and (eq_attr "type" "ssecmp")
|
|
|
1199 (eq_attr "memory" "none"))))
|
|
|
1200 "znver1-double,znver1-fp0|znver1-fp1")
|
|
|
1201
|
|
|
1202 (define_insn_reservation "znver1_sse_cmp_avx256_load" 8
|
|
|
1203 (and (eq_attr "cpu" "znver1")
|
|
|
1204 (and (eq_attr "mode" "V8SF,V4DF")
|
|
|
1205 (and (eq_attr "type" "ssecmp")
|
|
|
1206 (eq_attr "memory" "load"))))
|
|
|
1207 "znver1-double,znver1-load,znver1-fp0|znver1-fp1")
|
|
|
1208
|
|
|
1209 (define_insn_reservation "znver1_sse_icmp" 1
|
|
145
|
1210 (and (ior (and (eq_attr "cpu" "znver1")
|
|
|
1211 (eq_attr "mode" "QI,HI,SI,DI,TI"))
|
|
|
1212 (and (eq_attr "cpu" "znver2")
|
|
|
1213 (eq_attr "mode" "QI,HI,SI,DI,TI,OI")))
|
|
|
1214 (and (eq_attr "type" "ssecmp")
|
|
|
1215 (eq_attr "memory" "none")))
|
|
111
|
1216 "znver1-direct,znver1-fp0|znver1-fp3")
|
|
|
1217
|
|
|
1218 (define_insn_reservation "znver1_sse_icmp_load" 8
|
|
145
|
1219 (and (ior (and (eq_attr "cpu" "znver1")
|
|
|
1220 (eq_attr "mode" "QI,HI,SI,DI,TI"))
|
|
|
1221 (and (eq_attr "cpu" "znver2")
|
|
|
1222 (eq_attr "mode" "QI,HI,SI,DI,TI,OI")))
|
|
|
1223 (and (eq_attr "type" "ssecmp")
|
|
|
1224 (eq_attr "memory" "load")))
|
|
111
|
1225 "znver1-direct,znver1-load,znver1-fp0|znver1-fp3")
|
|
|
1226
|
|
|
1227 (define_insn_reservation "znver1_sse_icmp_avx256" 1
|
|
|
1228 (and (eq_attr "cpu" "znver1")
|
|
|
1229 (and (eq_attr "mode" "OI")
|
|
|
1230 (and (eq_attr "type" "ssecmp")
|
|
|
1231 (eq_attr "memory" "none"))))
|
|
|
1232 "znver1-double,znver1-fp0|znver1-fp3")
|
|
|
1233
|
|
|
1234 (define_insn_reservation "znver1_sse_icmp_avx256_load" 8
|
|
|
1235 (and (eq_attr "cpu" "znver1")
|
|
|
1236 (and (eq_attr "mode" "OI")
|
|
|
1237 (and (eq_attr "type" "ssecmp")
|
|
|
1238 (eq_attr "memory" "load"))))
|
|
|
1239 "znver1-double,znver1-load,znver1-fp0|znver1-fp3")
|
