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1 ;; Machine Descriptions for R8C/M16C/M32C
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2 ;; Copyright (C) 2005-2020 Free Software Foundation, Inc.
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3 ;; Contributed by Red Hat.
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4 ;;
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5 ;; This file is part of GCC.
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6 ;;
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7 ;; GCC is free software; you can redistribute it and/or modify it
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8 ;; under the terms of the GNU General Public License as published
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9 ;; by the Free Software Foundation; either version 3, or (at your
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10 ;; option) any later version.
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11 ;;
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12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
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13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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15 ;; License for more details.
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16 ;;
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17 ;; You should have received a copy of the GNU General Public License
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18 ;; along with GCC; see the file COPYING3. If not see
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19 ;; <http://www.gnu.org/licenses/>.
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20
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21 ;; bit shifting
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22
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23 ; Shifts are unusual for m32c. We only support shifting in one
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24 ; "direction" but the shift count is signed. Also, immediate shift
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25 ; counts have a limited range, and variable shift counts have to be in
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26 ; $r1h which GCC normally doesn't even know about.
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27
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28 ; Other than compensating for the above, the patterns below are pretty
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29 ; straightforward.
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30
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31 (define_insn "ashlqi3_i"
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32 [(set (match_operand:QI 0 "mra_operand" "=RqiSd*Rmm,RqiSd*Rmm")
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33 (ashift:QI (match_operand:QI 1 "mra_operand" "0,0")
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34 (match_operand:QI 2 "mrai_operand" "In4,RqiSd")))
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35 (clobber (match_scratch:HI 3 "=X,R1w"))]
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36 ""
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37 "@
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38 sha.b\t%2,%0
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39 mov.b\t%2,r1h\n\tsha.b\tr1h,%0"
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40 [(set_attr "flags" "oszc,oszc")]
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41 )
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42
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43 (define_insn "ashrqi3_i"
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44 [(set (match_operand:QI 0 "mra_operand" "=RqiSd*Rmm,RqiSd*Rmm")
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45 (ashiftrt:QI (match_operand:QI 1 "mra_operand" "0,0")
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46 (neg:QI (match_operand:QI 2 "mrai_operand" "In4,RqiSd"))))
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47 (clobber (match_scratch:HI 3 "=X,R1w"))]
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48 ""
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49 "@
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50 sha.b\t%2,%0
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51 mov.b\t%2,r1h\n\tsha.b\tr1h,%0"
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52 [(set_attr "flags" "oszc,oszc")]
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53 )
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54
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55 (define_insn "lshrqi3_i"
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56 [(set (match_operand:QI 0 "mra_operand" "=RqiSd*Rmm,RqiSd*Rmm")
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57 (lshiftrt:QI (match_operand:QI 1 "mra_operand" "0,0")
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58 (neg:QI (match_operand:QI 2 "mrai_operand" "In4,RqiSd"))))
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59 (clobber (match_scratch:HI 3 "=X,R1w"))]
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60 ""
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61 "@
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62 shl.b\t%2,%0
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63 mov.b\t%2,r1h\n\tshl.b\tr1h,%0"
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64 [(set_attr "flags" "szc,szc")]
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65 )
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66
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67
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68 (define_expand "ashlqi3"
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69 [(parallel [(set (match_operand:QI 0 "mra_operand" "")
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70 (ashift:QI (match_operand:QI 1 "mra_operand" "")
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71 (match_operand:QI 2 "general_operand" "")))
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72 (clobber (match_scratch:HI 3 ""))])]
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73 ""
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74 "if (m32c_prepare_shift (operands, 1, ASHIFT))
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75 DONE;"
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76 )
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77
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78 (define_expand "ashrqi3"
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79 [(parallel [(set (match_operand:QI 0 "mra_operand" "")
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80 (ashiftrt:QI (match_operand:QI 1 "mra_operand" "")
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81 (neg:QI (match_operand:QI 2 "general_operand" ""))))
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82 (clobber (match_scratch:HI 3 ""))])]
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83 ""
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84 "if (m32c_prepare_shift (operands, -1, ASHIFTRT))
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85 DONE;"
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86 )
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87
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88 (define_expand "lshrqi3"
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89 [(parallel [(set (match_operand:QI 0 "mra_operand" "")
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90 (lshiftrt:QI (match_operand:QI 1 "mra_operand" "")
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91 (neg:QI (match_operand:QI 2 "general_operand" ""))))
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92 (clobber (match_scratch:HI 3 ""))])]
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93 ""
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94 "if (m32c_prepare_shift (operands, -1, LSHIFTRT))
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95 DONE;"
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96 )
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97
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98 ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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99
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100 (define_insn "ashlhi3_i"
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101 [(set (match_operand:HI 0 "mra_operand" "=SdRhi*Rmm,SdRhi*Rmm")
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102 (ashift:HI (match_operand:HI 1 "mra_operand" "0,0")
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103 (match_operand:QI 2 "mrai_operand" "In4,RqiSd")))
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104 (clobber (match_scratch:HI 3 "=X,R1w"))]
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105 ""
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106 "@
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107 sha.w\t%2,%0
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108 mov.b\t%2,r1h\n\tsha.w\tr1h,%0"
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109 [(set_attr "flags" "oszc,oszc")]
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110 )
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111
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112 (define_insn "ashrhi3_i"
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113 [(set (match_operand:HI 0 "mra_operand" "=SdRhi*Rmm,SdRhi*Rmm")
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114 (ashiftrt:HI (match_operand:HI 1 "mra_operand" "0,0")
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115 (neg:QI (match_operand:QI 2 "mrai_operand" "In4,RqiSd"))))
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116 (clobber (match_scratch:HI 3 "=X,R1w"))]
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117 ""
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118 "@
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119 sha.w\t%2,%0
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120 mov.b\t%2,r1h\n\tsha.w\tr1h,%0"
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121 [(set_attr "flags" "oszc,oszc")]
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122 )
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123
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124 (define_insn "lshrhi3_i"
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125 [(set (match_operand:HI 0 "mra_operand" "=RhiSd*Rmm,RhiSd*Rmm")
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126 (lshiftrt:HI (match_operand:HI 1 "mra_operand" "0,0")
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127 (neg:QI (match_operand:QI 2 "mrai_operand" "In4,RqiSd"))))
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128 (clobber (match_scratch:HI 3 "=X,R1w"))]
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129 ""
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130 "@
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131 shl.w\t%2,%0
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132 mov.b\t%2,r1h\n\tshl.w\tr1h,%0"
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133 [(set_attr "flags" "szc,szc")]
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134 )
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135
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136
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137 (define_expand "ashlhi3"
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138 [(parallel [(set (match_operand:HI 0 "mra_operand" "")
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139 (ashift:HI (match_operand:HI 1 "mra_operand" "")
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140 (match_operand:QI 2 "general_operand" "")))
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141 (clobber (match_scratch:HI 3 ""))])]
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142 ""
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143 "if (m32c_prepare_shift (operands, 1, ASHIFT))
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144 DONE;"
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145 )
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146
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147 (define_expand "ashrhi3"
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148 [(parallel [(set (match_operand:HI 0 "mra_operand" "")
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149 (ashiftrt:HI (match_operand:HI 1 "mra_operand" "")
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150 (neg:QI (match_operand:QI 2 "general_operand" ""))))
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151 (clobber (match_scratch:HI 3 ""))])]
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152 ""
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153 "if (m32c_prepare_shift (operands, -1, ASHIFTRT))
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154 DONE;"
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155 )
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156
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157 (define_expand "lshrhi3"
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158 [(parallel [(set (match_operand:HI 0 "mra_operand" "")
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159 (lshiftrt:HI (match_operand:HI 1 "mra_operand" "")
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160 (neg:QI (match_operand:QI 2 "general_operand" ""))))
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161 (clobber (match_scratch:HI 3 ""))])]
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162 ""
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163 "if (m32c_prepare_shift (operands, -1, LSHIFTRT))
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164 DONE;"
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165 )
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166
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167
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168
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169
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170 ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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171
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172
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173 (define_insn "ashlpsi3_i"
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174 [(set (match_operand:PSI 0 "mra_operand" "=R02RaaSd*Rmm,R02RaaSd*Rmm")
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175 (ashift:PSI (match_operand:PSI 1 "mra_operand" "0,0")
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176 (match_operand:QI 2 "shiftcount_operand" "In4,RqiSd")))
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177 (clobber (match_scratch:HI 3 "=X,R1w"))]
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178 "TARGET_A24"
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179 "@
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180 sha.l\t%2,%0
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181 mov.b\t%2,r1h\n\tsha.l\tr1h,%0"
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182 [(set_attr "flags" "oszc,oszc")]
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183 )
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184
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185 (define_insn "ashrpsi3_i"
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186 [(set (match_operand:PSI 0 "mra_operand" "=R02RaaSd*Rmm,R02RaaSd*Rmm")
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187 (ashiftrt:PSI (match_operand:PSI 1 "mra_operand" "0,0")
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188 (neg:QI (match_operand:QI 2 "shiftcount_operand" "In4,RqiSd"))))
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189 (clobber (match_scratch:HI 3 "=X,R1w"))]
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190 "TARGET_A24"
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191 "@
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192 sha.l\t%2,%0
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193 mov.b\t%2,r1h\n\tsha.l\tr1h,%0"
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194 [(set_attr "flags" "oszc,oszc")]
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195 )
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196
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197 (define_insn "lshrpsi3_i"
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198 [(set (match_operand:PSI 0 "mra_operand" "=R02RaaSd,??Rmm")
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199 (lshiftrt:PSI (match_operand:PSI 1 "mra_operand" "0,0")
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200 (neg:QI (match_operand:QI 2 "shiftcount_operand" "In4,RqiSd"))))
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201 (clobber (match_scratch:HI 3 "=X,R1w"))]
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202 "TARGET_A24"
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203 "@
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204 shl.l\t%2,%0
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205 mov.b\t%2,r1h\n\tshl.l\tr1h,%0"
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206 [(set_attr "flags" "szc,szc")]
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207 )
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208
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209
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210 (define_expand "ashlpsi3"
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211 [(parallel [(set (match_operand:PSI 0 "mra_operand" "")
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212 (ashift:PSI (match_operand:PSI 1 "mra_operand" "")
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213 (match_operand:QI 2 "shiftcount_operand" "")))
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214 (clobber (match_scratch:HI 3 ""))])]
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215 "TARGET_A24"
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216 "if (m32c_prepare_shift (operands, 1, ASHIFT))
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217 DONE;"
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218 )
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219
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220 (define_expand "ashrpsi3"
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221 [(parallel [(set (match_operand:PSI 0 "mra_operand" "")
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222 (ashiftrt:PSI (match_operand:PSI 1 "mra_operand" "")
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223 (neg:QI (match_operand:QI 2 "shiftcount_operand" ""))))
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224 (clobber (match_scratch:HI 3 ""))])]
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225 "TARGET_A24"
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226 "if (m32c_prepare_shift (operands, -1, ASHIFTRT))
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227 DONE;"
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228 )
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229
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230 (define_expand "lshrpsi3"
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231 [(parallel [(set (match_operand:PSI 0 "mra_operand" "")
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232 (lshiftrt:PSI (match_operand:PSI 1 "mra_operand" "")
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233 (neg:QI (match_operand:QI 2 "shiftcount_operand" ""))))
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234 (clobber (match_scratch:HI 3 ""))])]
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235 "TARGET_A24"
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236 "if (m32c_prepare_shift (operands, -1, LSHIFTRT))
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237 DONE;"
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238 )
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239
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240 ; - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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241
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242 ; The m16c has a maximum shift count of -16..16, even when in a
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243 ; register. It's optimal to use multiple shifts of -8..8 rather than
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244 ; loading larger constants into R1H multiple time. The m32c can shift
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245 ; -32..32 either via immediates or in registers. Hence, separate
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246 ; patterns.
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247
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248
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249 (define_insn "ashlsi3_16"
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250 [(set (match_operand:SI 0 "r0123_operand" "=R03,R03")
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251 (ashift:SI (match_operand:SI 1 "r0123_operand" "0,0")
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252 (match_operand:QI 2 "shiftcount_operand" "In4,RqiSd")))
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253 (clobber (match_scratch:HI 3 "=X,R1w"))]
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254 "TARGET_A16"
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255 "@
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256 sha.l\t%2,%0
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257 mov.b\t%2,r1h\n\tsha.l\tr1h,%0"
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258 [(set_attr "flags" "oszc,oszc")]
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259 )
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260
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261 (define_insn "ashrsi3_16"
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262 [(set (match_operand:SI 0 "r0123_operand" "=R03,R03")
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263 (ashiftrt:SI (match_operand:SI 1 "r0123_operand" "0,0")
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264 (neg:QI (match_operand:QI 2 "shiftcount_operand" "In4,RqiSd"))))
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265 (clobber (match_scratch:HI 3 "=X,R1w"))]
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266 "TARGET_A16"
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267 "@
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268 sha.l\t%2,%0
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269 mov.b\t%2,r1h\n\tsha.l\tr1h,%0"
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270 [(set_attr "flags" "oszc,oszc")]
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271 )
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272
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273 (define_insn "lshrsi3_16"
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274 [(set (match_operand:SI 0 "r0123_operand" "=R03,R03")
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275 (lshiftrt:SI (match_operand:SI 1 "r0123_operand" "0,0")
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276 (neg:QI (match_operand:QI 2 "shiftcount_operand" "In4,RqiSd"))))
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277 (clobber (match_scratch:HI 3 "=X,R1w"))]
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278 "TARGET_A16"
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279 "@
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280 shl.l\t%2,%0
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281 mov.b\t%2,r1h\n\tshl.l\tr1h,%0"
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282 [(set_attr "flags" "szc,szc")]
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283 )
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284
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285
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286
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287 (define_insn "ashlsi3_24"
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288 [(set (match_operand:SI 0 "r0123_operand" "=R03,R03")
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289 (ashift:SI (match_operand:SI 1 "r0123_operand" "0,0")
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290 (match_operand:QI 2 "longshiftcount_operand" "In6,RqiSd")))
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291 (clobber (match_scratch:HI 3 "=X,R1w"))]
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292 "TARGET_A24"
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293 "@
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294 sha.l\t%2,%0
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295 mov.b\t%2,r1h\n\tsha.l\tr1h,%0"
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296 )
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297
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298 (define_insn "ashrsi3_24"
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299 [(set (match_operand:SI 0 "r0123_operand" "=R03,R03")
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300 (ashiftrt:SI (match_operand:SI 1 "r0123_operand" "0,0")
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301 (neg:QI (match_operand:QI 2 "longshiftcount_operand" "In6,RqiSd"))))
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302 (clobber (match_scratch:HI 3 "=X,R1w"))]
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303 "TARGET_A24"
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304 "@
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305 sha.l\t%2,%0
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306 mov.b\t%2,r1h\n\tsha.l\tr1h,%0"
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307 )
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308
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309 (define_insn "lshrsi3_24"
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310 [(set (match_operand:SI 0 "r0123_operand" "=R03,R03")
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311 (lshiftrt:SI (match_operand:SI 1 "r0123_operand" "0,0")
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312 (neg:QI (match_operand:QI 2 "longshiftcount_operand" "In6,RqiSd"))))
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313 (clobber (match_scratch:HI 3 "=X,R1w"))]
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314 "TARGET_A24"
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315 "@
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316 shl.l\t%2,%0
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317 mov.b\t%2,r1h\n\tshl.l\tr1h,%0"
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318 )
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319
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320
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321
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322
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323 (define_expand "ashlsi3"
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324 [(parallel [(set (match_operand:SI 0 "r0123_operand" "")
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325 (ashift:SI (match_operand:SI 1 "r0123_operand" "")
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326 (match_operand:QI 2 "mrai_operand" "")))
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327 (clobber (match_scratch:HI 3 ""))])]
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328 ""
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329 "if (m32c_prepare_shift (operands, 1, ASHIFT))
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330 DONE;"
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331 )
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332
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333 (define_expand "ashrsi3"
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334 [(parallel [(set (match_operand:SI 0 "r0123_operand" "")
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335 (ashiftrt:SI (match_operand:SI 1 "r0123_operand" "")
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336 (neg:QI (match_operand:QI 2 "mrai_operand" ""))))
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337 (clobber (match_scratch:HI 3 ""))])]
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338 ""
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339 "if (m32c_prepare_shift (operands, -1, ASHIFTRT))
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340 DONE;"
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341 )
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342
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343 (define_expand "lshrsi3"
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344 [(parallel [(set (match_operand:SI 0 "r0123_operand" "")
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345 (lshiftrt:SI (match_operand:SI 1 "r0123_operand" "")
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346 (neg:QI (match_operand:QI 2 "mrai_operand" ""))))
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347 (clobber (match_scratch:HI 3 ""))])]
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348 ""
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349 "if (m32c_prepare_shift (operands, -1, LSHIFTRT))
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350 DONE;"
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351 )
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