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1 ;; GCC machine description for m68k synchronization instructions.
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2 ;; Copyright (C) 2011-2020 Free Software Foundation, Inc.
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111
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3 ;;
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4 ;; This file is part of GCC.
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5 ;;
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6 ;; GCC is free software; you can redistribute it and/or modify
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7 ;; it under the terms of the GNU General Public License as published by
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8 ;; the Free Software Foundation; either version 3, or (at your option)
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9 ;; any later version.
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10 ;;
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11 ;; GCC is distributed in the hope that it will be useful,
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12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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14 ;; GNU General Public License for more details.
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15 ;;
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16 ;; You should have received a copy of the GNU General Public License
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17 ;; along with GCC; see the file COPYING3. If not see
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18 ;; <http://www.gnu.org/licenses/>.
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19
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20
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21 (define_expand "atomic_compare_and_swap<mode>"
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22 [(match_operand:QI 0 "register_operand" "") ;; bool success output
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23 (match_operand:I 1 "register_operand" "") ;; oldval output
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24 (match_operand:I 2 "memory_operand" "") ;; memory
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25 (match_operand:I 3 "register_operand" "") ;; expected input
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26 (match_operand:I 4 "register_operand" "") ;; newval input
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27 (match_operand:SI 5 "const_int_operand" "") ;; is_weak
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28 (match_operand:SI 6 "const_int_operand" "") ;; success model
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29 (match_operand:SI 7 "const_int_operand" "")] ;; failure model
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30 "TARGET_CAS"
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31 {
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32 emit_insn (gen_atomic_compare_and_swap<mode>_1
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33 (operands[0], operands[1], operands[2],
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34 operands[3], operands[4]));
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35 emit_insn (gen_negqi2 (operands[0], operands[0]));
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36 DONE;
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37 })
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38
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39 (define_insn "atomic_compare_and_swap<mode>_1"
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40 [(set (match_operand:I 1 "register_operand" "=d")
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41 (unspec_volatile:I
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42 [(match_operand:I 2 "memory_operand" "+m")
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43 (match_operand:I 3 "register_operand" "1")
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44 (match_operand:I 4 "register_operand" "d")]
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45 UNSPECV_CAS_1))
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46 (set (match_dup 2)
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47 (unspec_volatile:I
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48 [(match_dup 2) (match_dup 3) (match_dup 4)]
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49 UNSPECV_CAS_2))
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50 (set (match_operand:QI 0 "register_operand" "=d")
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51 (unspec_volatile:QI
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52 [(match_dup 2) (match_dup 3) (match_dup 4)]
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53 UNSPECV_CAS_2))]
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54 "TARGET_CAS"
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55 ;; Elide the seq if operands[0] is dead.
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56 "cas<sz> %1,%4,%2\;seq %0")
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57
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58 (define_expand "atomic_test_and_set"
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59 [(match_operand:QI 0 "register_operand" "") ;; bool success output
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60 (match_operand:QI 1 "memory_operand" "") ;; memory
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61 (match_operand:SI 2 "const_int_operand" "")] ;; model
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62 "ISA_HAS_TAS"
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63 {
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64 rtx t = gen_reg_rtx (QImode);
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65 emit_insn (gen_atomic_test_and_set_1 (t, operands[1]));
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66 t = expand_simple_unop (QImode, NEG, t, operands[0], 0);
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67 if (t != operands[0])
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68 emit_move_insn (operands[0], t);
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69 DONE;
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70 })
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71
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72 (define_insn "atomic_test_and_set_1"
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73 [(set (match_operand:QI 0 "register_operand" "=d")
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74 (unspec_volatile:QI
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75 [(match_operand:QI 1 "memory_operand" "+m")]
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76 UNSPECV_TAS_1))
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77 (set (match_dup 1)
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78 (unspec_volatile:QI [(match_dup 1)] UNSPECV_TAS_2))]
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79 "ISA_HAS_TAS"
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80 "tas %1\;sne %0")
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