annotate gcc/config/mips/mips-modes.def @ 145:1830386684a0

gcc-9.2.0
author anatofuz
date Thu, 13 Feb 2020 11:34:05 +0900
parents 84e7813d76e9
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1 /* MIPS extra machine modes.
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2 Copyright (C) 2003-2020 Free Software Foundation, Inc.
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4 This file is part of GCC.
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6 GCC is free software; you can redistribute it and/or modify
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7 it under the terms of the GNU General Public License as published by
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8 the Free Software Foundation; either version 3, or (at your option)
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9 any later version.
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10
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11 GCC is distributed in the hope that it will be useful,
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12 but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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14 GNU General Public License for more details.
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16 You should have received a copy of the GNU General Public License
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17 along with GCC; see the file COPYING3. If not see
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18 <http://www.gnu.org/licenses/>. */
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19
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20 FLOAT_MODE (TF, 16, ieee_quad_format);
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22 /* Vector modes. */
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23 VECTOR_MODES (INT, 4); /* V4QI V2HI */
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24 VECTOR_MODES (INT, 8); /* V8QI V4HI V2SI */
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25 VECTOR_MODES (FLOAT, 8); /* V4HF V2SF */
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26
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27 /* For MIPS MSA 128 bits. */
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28 VECTOR_MODES (INT, 16); /* V16QI V8HI V4SI V2DI */
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29 VECTOR_MODES (FLOAT, 16); /* V4SF V2DF */
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30
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31 /* Double-sized vector modes for vec_concat. */
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32 VECTOR_MODE (INT, QI, 32); /* V32QI */
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33 VECTOR_MODE (INT, HI, 16); /* V16HI */
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34 VECTOR_MODE (INT, SI, 8); /* V8SI */
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35 VECTOR_MODE (INT, DI, 4); /* V4DI */
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36 VECTOR_MODE (FLOAT, SF, 8); /* V8SF */
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37 VECTOR_MODE (FLOAT, DF, 4); /* V4DF */
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39 VECTOR_MODES (FRACT, 4); /* V4QQ V2HQ */
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40 VECTOR_MODES (UFRACT, 4); /* V4UQQ V2UHQ */
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41 VECTOR_MODES (ACCUM, 4); /* V2HA */
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42 VECTOR_MODES (UACCUM, 4); /* V2UHA */
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44 /* Paired single comparison instructions use 2 or 4 CC. */
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45 CC_MODE (CCV2);
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46 ADJUST_BYTESIZE (CCV2, 8);
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47 ADJUST_ALIGNMENT (CCV2, 8);
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49 CC_MODE (CCV4);
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50 ADJUST_BYTESIZE (CCV4, 16);
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51 ADJUST_ALIGNMENT (CCV4, 16);
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53 /* For MIPS DSP control registers. */
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54 CC_MODE (CCDSP);
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55
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56 /* For floating point conditions in FP registers. */
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57 CC_MODE (CCF);