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1 ;; Pipeline descriptions of Andes NDS32 cpu for GNU compiler
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2 ;; Copyright (C) 2012-2020 Free Software Foundation, Inc.
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3 ;; Contributed by Andes Technology Corporation.
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4 ;;
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5 ;; This file is part of GCC.
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6 ;;
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7 ;; GCC is free software; you can redistribute it and/or modify it
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8 ;; under the terms of the GNU General Public License as published
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9 ;; by the Free Software Foundation; either version 3, or (at your
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10 ;; option) any later version.
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11 ;;
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12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
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13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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15 ;; License for more details.
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16 ;;
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17 ;; You should have received a copy of the GNU General Public License
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18 ;; along with GCC; see the file COPYING3. If not see
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19 ;; <http://www.gnu.org/licenses/>.
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20
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21
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22 ;; ------------------------------------------------------------------------
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23 ;; Define N8 pipeline settings.
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24 ;; ------------------------------------------------------------------------
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25
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26 (define_automaton "nds32_n7_machine")
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27
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28 ;; ------------------------------------------------------------------------
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29 ;; Pipeline Stages
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30 ;; ------------------------------------------------------------------------
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31 ;; IF - Instruction Fetch
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32 ;; Instruction Alignment
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33 ;; Instruction Pre-decode
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34 ;; II - Instruction Issue
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35 ;; Instruction Decode
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36 ;; Register File Access
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37 ;; Instruction Execution
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38 ;; Interrupt Handling
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39 ;; EXD - Psuedo Stage
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40 ;; Load Data Completion
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41
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42 (define_cpu_unit "n7_ii" "nds32_n7_machine")
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43
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44 (define_insn_reservation "nds_n7_unknown" 1
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45 (and (eq_attr "type" "unknown")
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46 (eq_attr "pipeline_model" "n7"))
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47 "n7_ii")
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48
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49 (define_insn_reservation "nds_n7_misc" 1
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50 (and (eq_attr "type" "misc")
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51 (eq_attr "pipeline_model" "n7"))
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52 "n7_ii")
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53
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54 (define_insn_reservation "nds_n7_alu" 1
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55 (and (eq_attr "type" "alu")
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56 (eq_attr "pipeline_model" "n7"))
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57 "n7_ii")
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58
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59 (define_insn_reservation "nds_n7_load" 1
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60 (and (match_test "nds32::load_single_p (insn)")
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61 (eq_attr "pipeline_model" "n7"))
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62 "n7_ii")
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63
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64 (define_insn_reservation "nds_n7_store" 1
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65 (and (match_test "nds32::store_single_p (insn)")
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66 (eq_attr "pipeline_model" "n7"))
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67 "n7_ii")
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68
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69 (define_insn_reservation "nds_n7_load_multiple_1" 1
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70 (and (and (eq_attr "type" "load_multiple")
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71 (eq_attr "combo" "1"))
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72 (eq_attr "pipeline_model" "n7"))
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73 "n7_ii")
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74
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75 (define_insn_reservation "nds_n7_load_multiple_2" 1
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76 (and (ior (and (eq_attr "type" "load_multiple")
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77 (eq_attr "combo" "2"))
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78 (match_test "nds32::load_double_p (insn)"))
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79 (eq_attr "pipeline_model" "n7"))
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80 "n7_ii*2")
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81
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82 (define_insn_reservation "nds_n7_load_multiple_3" 1
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83 (and (and (eq_attr "type" "load_multiple")
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84 (eq_attr "combo" "3"))
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85 (eq_attr "pipeline_model" "n7"))
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86 "n7_ii*3")
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87
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88 (define_insn_reservation "nds_n7_load_multiple_4" 1
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89 (and (and (eq_attr "type" "load_multiple")
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90 (eq_attr "combo" "4"))
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91 (eq_attr "pipeline_model" "n7"))
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92 "n7_ii*4")
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93
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94 (define_insn_reservation "nds_n7_load_multiple_5" 1
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95 (and (and (eq_attr "type" "load_multiple")
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96 (eq_attr "combo" "5"))
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97 (eq_attr "pipeline_model" "n7"))
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98 "n7_ii*5")
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99
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100 (define_insn_reservation "nds_n7_load_multiple_6" 1
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101 (and (and (eq_attr "type" "load_multiple")
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102 (eq_attr "combo" "6"))
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103 (eq_attr "pipeline_model" "n7"))
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104 "n7_ii*6")
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105
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106 (define_insn_reservation "nds_n7_load_multiple_7" 1
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107 (and (and (eq_attr "type" "load_multiple")
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108 (eq_attr "combo" "7"))
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109 (eq_attr "pipeline_model" "n7"))
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110 "n7_ii*7")
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111
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112 (define_insn_reservation "nds_n7_load_multiple_8" 1
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113 (and (and (eq_attr "type" "load_multiple")
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114 (eq_attr "combo" "8"))
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115 (eq_attr "pipeline_model" "n7"))
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116 "n7_ii*8")
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117
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118 (define_insn_reservation "nds_n7_load_multiple_12" 1
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119 (and (and (eq_attr "type" "load_multiple")
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120 (eq_attr "combo" "12"))
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121 (eq_attr "pipeline_model" "n7"))
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122 "n7_ii*12")
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123
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124 (define_insn_reservation "nds_n7_store_multiple_1" 1
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125 (and (and (eq_attr "type" "store_multiple")
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126 (eq_attr "combo" "1"))
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127 (eq_attr "pipeline_model" "n7"))
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128 "n7_ii")
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129
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130 (define_insn_reservation "nds_n7_store_multiple_2" 1
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131 (and (ior (and (eq_attr "type" "store_multiple")
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132 (eq_attr "combo" "2"))
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133 (match_test "nds32::store_double_p (insn)"))
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134 (eq_attr "pipeline_model" "n7"))
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135 "n7_ii*2")
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136
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137 (define_insn_reservation "nds_n7_store_multiple_3" 1
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138 (and (and (eq_attr "type" "store_multiple")
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139 (eq_attr "combo" "3"))
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140 (eq_attr "pipeline_model" "n7"))
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141 "n7_ii*3")
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142
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143 (define_insn_reservation "nds_n7_store_multiple_4" 1
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144 (and (and (eq_attr "type" "store_multiple")
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145 (eq_attr "combo" "4"))
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146 (eq_attr "pipeline_model" "n7"))
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147 "n7_ii*4")
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148
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149 (define_insn_reservation "nds_n7_store_multiple_5" 1
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150 (and (and (eq_attr "type" "store_multiple")
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151 (eq_attr "combo" "5"))
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152 (eq_attr "pipeline_model" "n7"))
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153 "n7_ii*5")
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154
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155 (define_insn_reservation "nds_n7_store_multiple_6" 1
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156 (and (and (eq_attr "type" "store_multiple")
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157 (eq_attr "combo" "6"))
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158 (eq_attr "pipeline_model" "n7"))
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159 "n7_ii*6")
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160
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161 (define_insn_reservation "nds_n7_store_multiple_7" 1
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162 (and (and (eq_attr "type" "store_multiple")
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163 (eq_attr "combo" "7"))
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164 (eq_attr "pipeline_model" "n7"))
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165 "n7_ii*7")
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166
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167 (define_insn_reservation "nds_n7_store_multiple_8" 1
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168 (and (and (eq_attr "type" "store_multiple")
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169 (eq_attr "combo" "8"))
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170 (eq_attr "pipeline_model" "n7"))
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171 "n7_ii*8")
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172
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173 (define_insn_reservation "nds_n7_store_multiple_12" 1
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174 (and (and (eq_attr "type" "store_multiple")
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175 (eq_attr "combo" "12"))
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176 (eq_attr "pipeline_model" "n7"))
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177 "n7_ii*12")
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178
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179 (define_insn_reservation "nds_n7_mul_fast" 1
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180 (and (match_test "nds32_mul_config != MUL_TYPE_SLOW")
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181 (and (eq_attr "type" "mul")
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182 (eq_attr "pipeline_model" "n7")))
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183 "n7_ii")
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184
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185 (define_insn_reservation "nds_n7_mul_slow" 1
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186 (and (match_test "nds32_mul_config == MUL_TYPE_SLOW")
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187 (and (eq_attr "type" "mul")
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188 (eq_attr "pipeline_model" "n7")))
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189 "n7_ii*17")
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190
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191 (define_insn_reservation "nds_n7_mac_fast" 1
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192 (and (match_test "nds32_mul_config != MUL_TYPE_SLOW")
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193 (and (eq_attr "type" "mac")
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194 (eq_attr "pipeline_model" "n7")))
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195 "n7_ii*2")
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196
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197 (define_insn_reservation "nds_n7_mac_slow" 1
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198 (and (match_test "nds32_mul_config == MUL_TYPE_SLOW")
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199 (and (eq_attr "type" "mac")
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200 (eq_attr "pipeline_model" "n7")))
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201 "n7_ii*18")
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202
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203 (define_insn_reservation "nds_n7_div" 1
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204 (and (eq_attr "type" "div")
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205 (eq_attr "pipeline_model" "n7"))
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206 "n7_ii*37")
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207
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208 (define_insn_reservation "nds_n7_branch" 1
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209 (and (eq_attr "type" "branch")
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210 (eq_attr "pipeline_model" "n7"))
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211 "n7_ii")
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212
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213 ;; ------------------------------------------------------------------------
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214 ;; Comment Notations and Bypass Rules
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215 ;; ------------------------------------------------------------------------
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216 ;; Producers (LHS)
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217 ;; LD_!bi
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218 ;; Load data from the memory (without updating the base register) and
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219 ;; produce the loaded data. The result is ready at EXD.
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220 ;; LMW(N, M)
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221 ;; There are N micro-operations within an instruction that loads multiple
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222 ;; words. The result produced by the M-th micro-operation is sent to
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223 ;; consumers. The result is ready at EXD. If the base register should be
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224 ;; updated, an extra micro-operation is inserted to the sequence, and the
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225 ;; result is ready at II.
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226 ;;
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227 ;; Consumers (RHS)
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228 ;; ALU, MUL, DIV
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229 ;; Require operands at II.
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230 ;; MOVD44_E
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231 ;; A double-word move instruction needs two micro-operations because the
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232 ;; reigster ports is 2R1W. The first micro-operation writes an even number
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233 ;; register, and the second micro-operation writes an odd number register.
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234 ;; Each input operand is required at II for each micro-operation. The letter
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235 ;; 'E' stands for even.
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236 ;; MAC_RaRb
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237 ;; A MAC instruction is separated into two micro-operations. The first
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238 ;; micro-operation does the multiplication, which requires operands Ra
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239 ;; and Rb at II. The second micro-options does the accumulation, which
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240 ;; requires the operand Rt at II.
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241 ;; ADDR_IN_MOP(N)
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242 ;; Because the reigster port is 2R1W, some load/store instructions are
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243 ;; separated into many micro-operations. N denotes the address input is
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244 ;; required by the N-th micro-operation. Such operand is required at II.
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245 ;; ST_bi
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246 ;; A post-increment store instruction requires its data at II.
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247 ;; ST_!bi_RI
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248 ;; A store instruction with an immediate offset requires its data at II.
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249 ;; If the offset field is a register (ST_!bi_RR), the instruction will be
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250 ;; separated into two micro-operations, and the second one requires the
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251 ;; input operand at II in order to store it to the memory.
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252 ;; SMW(N, M)
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253 ;; There are N micro-operations within an instruction that stores multiple
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254 ;; words. Each M-th micro-operation requires its data at II. If the base
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255 ;; register should be updated, an extra micro-operation is inserted to the
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256 ;; sequence.
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257 ;; BR_COND
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258 ;; If a branch instruction is conditional, its input data is required at II.
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259
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260 ;; LD_!bi
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261 ;; -> ALU, MOVD44_E, MUL, MAC_RaRb, DIV, BR, ADDR_IN_MOP(1), ST_bi, ST_!bi_RI, SMW(N, 1)
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262 (define_bypass 2
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263 "nds_n7_load"
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264 "nds_n7_alu,\
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265 nds_n7_mul_fast, nds_n7_mul_slow,\
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266 nds_n7_mac_fast, nds_n7_mac_slow,\
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267 nds_n7_div,\
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268 nds_n7_branch,\
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269 nds_n7_load, nds_n7_store,\
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270 nds_n7_load_multiple_1,nds_n7_load_multiple_2, nds_n7_load_multiple_3,\
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271 nds_n7_load_multiple_4,nds_n7_load_multiple_5, nds_n7_load_multiple_6,\
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272 nds_n7_load_multiple_7,nds_n7_load_multiple_8, nds_n7_load_multiple_12,\
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273 nds_n7_store_multiple_1,nds_n7_store_multiple_2, nds_n7_store_multiple_3,\
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274 nds_n7_store_multiple_4,nds_n7_store_multiple_5, nds_n7_store_multiple_6,\
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275 nds_n7_store_multiple_7,nds_n7_store_multiple_8, nds_n7_store_multiple_12"
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276 "nds32_n7_load_to_ii_p"
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277 )
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278
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279 ;; LMW(N, N)
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280 ;; -> ALU, MOVD44_E, MUL, MAC_RaRb, DIV, BR, AADR_IN_MOP(1), ST_bi, ST_!bi_RI, SMW(N, 1)
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281 (define_bypass 2
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282 "nds_n7_load_multiple_1,nds_n7_load_multiple_2, nds_n7_load_multiple_3,\
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283 nds_n7_load_multiple_4,nds_n7_load_multiple_5, nds_n7_load_multiple_6,\
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284 nds_n7_load_multiple_7,nds_n7_load_multiple_8, nds_n7_load_multiple_12"
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285 "nds_n7_alu,\
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286 nds_n7_mul_fast, nds_n7_mul_slow,\
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287 nds_n7_mac_fast, nds_n7_mac_slow,\
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288 nds_n7_div,\
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289 nds_n7_branch,\
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290 nds_n7_load, nds_n7_store,\
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291 nds_n7_load_multiple_1,nds_n7_load_multiple_2, nds_n7_load_multiple_3,\
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292 nds_n7_load_multiple_4,nds_n7_load_multiple_5, nds_n7_load_multiple_6,\
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293 nds_n7_load_multiple_7,nds_n7_load_multiple_8, nds_n7_load_multiple_12,\
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294 nds_n7_store_multiple_1,nds_n7_store_multiple_2, nds_n7_store_multiple_3,\
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295 nds_n7_store_multiple_4,nds_n7_store_multiple_5, nds_n7_store_multiple_6,\
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296 nds_n7_store_multiple_7,nds_n7_store_multiple_8, nds_n7_store_multiple_12"
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297 "nds32_n7_last_load_to_ii_p"
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298 )
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