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1 /* Definitions for option handling of Andes NDS32 cpu for GNU compiler
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2 Copyright (C) 2012-2020 Free Software Foundation, Inc.
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3 Contributed by Andes Technology Corporation.
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4
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5 This file is part of GCC.
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6
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7 GCC is free software; you can redistribute it and/or modify it
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8 under the terms of the GNU General Public License as published
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9 by the Free Software Foundation; either version 3, or (at your
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10 option) any later version.
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11
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12 GCC is distributed in the hope that it will be useful, but WITHOUT
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13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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15 License for more details.
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16
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17 You should have received a copy of the GNU General Public License
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18 along with GCC; see the file COPYING3. If not see
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19 <http://www.gnu.org/licenses/>. */
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20
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21 #ifndef NDS32_OPTS_H
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22 #define NDS32_OPTS_H
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23
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24 #define NDS32_DEFAULT_CACHE_BLOCK_SIZE 16
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25 #define NDS32_DEFAULT_ISR_VECTOR_SIZE (TARGET_ISA_V3 ? 4 : 16)
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26
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27 /* The various ANDES ISA. */
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28 enum nds32_arch_type
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29 {
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30 ARCH_V2,
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31 ARCH_V3,
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32 ARCH_V3J,
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33 ARCH_V3M,
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34 ARCH_V3F,
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35 ARCH_V3S
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36 };
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37
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38 /* The various ANDES CPU. */
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39 enum nds32_cpu_type
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40 {
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41 CPU_N6,
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42 CPU_N7,
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43 CPU_N8,
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44 CPU_E8,
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45 CPU_N9,
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46 CPU_N10,
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47 CPU_GRAYWOLF,
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48 CPU_N12,
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49 CPU_N13,
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50 CPU_SIMPLE
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51 };
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52
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53 /* The code model defines the address generation strategy. */
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54 enum nds32_cmodel_type
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55 {
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56 CMODEL_SMALL,
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57 CMODEL_MEDIUM,
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58 CMODEL_LARGE
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59 };
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60
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61 /* The code model defines the address generation strategy. */
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62 enum nds32_ict_model_type
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63 {
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64 ICT_MODEL_SMALL,
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65 ICT_MODEL_LARGE
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66 };
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67
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68 /* Multiply instruction configuration. */
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69 enum nds32_mul_type
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70 {
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71 MUL_TYPE_FAST_1,
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72 MUL_TYPE_FAST_2,
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73 MUL_TYPE_SLOW
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74 };
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75
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76 /* Register ports configuration. */
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77 enum nds32_register_ports
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78 {
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79 REG_PORT_3R2W,
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80 REG_PORT_2R1W
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81 };
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82
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83 /* Which ABI to use. */
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84 enum abi_type
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85 {
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86 NDS32_ABI_V2,
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87 NDS32_ABI_V2_FP_PLUS
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88 };
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89
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90 /* The various FPU number of registers. */
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91 enum float_reg_number
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92 {
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93 NDS32_CONFIG_FPU_0,
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94 NDS32_CONFIG_FPU_1,
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95 NDS32_CONFIG_FPU_2,
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96 NDS32_CONFIG_FPU_3,
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97 NDS32_CONFIG_FPU_4,
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98 NDS32_CONFIG_FPU_5,
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99 NDS32_CONFIG_FPU_6,
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100 NDS32_CONFIG_FPU_7
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101 };
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102
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103 #endif
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