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annotate gcc/config/pdp11/constraints.md @ 145:1830386684a0

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gcc-9.2.0
author anatofuz
date Thu, 13 Feb 2020 11:34:05 +0900
parents 84e7813d76e9
children
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1 ;;- Constraint definitions for the pdp11 for GNU C compiler
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2 ;; Copyright (C) 2010-2020 Free Software Foundation, Inc.
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3 ;; Contributed by Michael K. Gschwind (mike@vlsivie.tuwien.ac.at).
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4
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5 ;; This file is part of GCC.
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6
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7 ;; GCC is free software; you can redistribute it and/or modify
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8 ;; it under the terms of the GNU General Public License as published by
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9 ;; the Free Software Foundation; either version 3, or (at your option)
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10 ;; any later version.
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11
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12 ;; GCC is distributed in the hope that it will be useful,
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13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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15 ;; GNU General Public License for more details.
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16
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17 ;; You should have received a copy of the GNU General Public License
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18 ;; along with GCC; see the file COPYING3. If not see
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19 ;; <http://www.gnu.org/licenses/>.
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20
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21 (define_register_constraint "a" "LOAD_FPU_REGS"
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22 "FPU register that can be directly loaded from memory")
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23
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24 (define_register_constraint "f" "FPU_REGS"
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25 "Any FPU register")
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27 (define_register_constraint "h" "NO_LOAD_FPU_REGS"
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28 "FPU register that cannot be directly loaded from memory")
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29
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30 (define_register_constraint "d" "MUL_REGS"
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31 "General register that can be used for 16-bit multiply (odd numbered)")
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32
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33 (define_constraint "I"
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34 "Integer constant that fits in 16 bits unsigned"
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35 (and (match_code "const_int")
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36 (match_test "(ival & 0xffff0000) == 0")))
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37
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38 (define_constraint "J"
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39 "Integer constant whose low 16 bits are zero"
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40 (and (match_code "const_int")
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41 (match_test "(ival & 0xffff) == 0")))
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42
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43 (define_constraint "K"
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44 "Integer constant whose lower and upper 16 bit half are both non-zero"
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45 (and (match_code "const_int")
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46 (match_test "(ival & 0xffff) != 0 && (ival & 0xffff0000) != 0")))
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47
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48 (define_constraint "L"
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49 "Integer constant 1"
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50 (and (match_code "const_int")
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51 (match_test "ival == 1")))
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52
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53 (define_constraint "M"
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54 "Integer constant -1"
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55 (and (match_code "const_int")
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56 (match_test "ival == -1")))
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57
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58 (define_constraint "N"
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59 "Integer constant 0"
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60 (and (match_code "const_int")
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61 (match_test "ival == 0")))
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62
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63 (define_constraint "O"
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64 "Integer constant for which several individual shifts are better than one big one"
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65 (and (match_code "const_int")
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66 (match_test "pdp11_small_shift (ival)")))
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67
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68 (define_constraint "G"
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69 "Defines a real zero constant."
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70 (and (match_code "const_double")
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71 (match_test "op == CONST0_RTX (GET_MODE (op))")))
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73 (define_memory_constraint "Q"
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74 "Memory reference that requires an additional word after the opcode"
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75 (and (match_code "mem")
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76 (match_test "memory_address_p (GET_MODE (op), XEXP (op, 0))
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77 && !simple_memory_operand (op, GET_MODE (op))")))
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79 (define_memory_constraint "R"
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80 "Memory reference that is encoded within the opcode"
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81 (and (match_code "mem")
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82 (match_test "memory_address_p (GET_MODE (op), XEXP (op, 0))
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83 && simple_memory_operand (op, GET_MODE (op))")))
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85 (define_memory_constraint "D"
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86 "Memory reference that is encoded within the opcode, and not push or pop"
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87 (and (match_code "mem")
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88 (match_test "memory_address_p (GET_MODE (op), XEXP (op, 0))
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89 && no_side_effect_operand (op, GET_MODE (op))")))
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90
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91 ;; What follows is a set of constraints used to prevent the generation
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92 ;; of insns that have a register as source, and an auto-increment or
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93 ;; auto-decrement memory reference as the destination where the register
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94 ;; is the same as the source. On the PDP11, such instructions are not
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95 ;; implemented consistently across the models and often do something
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96 ;; different from what the RTL intends.
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97 (define_register_constraint "Z0" "NOTR0_REG" "Register other than 0")
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98 (define_register_constraint "Z1" "NOTR1_REG" "Register other than 1")
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99 (define_register_constraint "Z2" "NOTR2_REG" "Register other than 2")
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100 (define_register_constraint "Z3" "NOTR3_REG" "Register other than 3")
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101 (define_register_constraint "Z4" "NOTR4_REG" "Register other than 4")
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102 (define_register_constraint "Z5" "NOTR5_REG" "Register other than 5")
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103 (define_register_constraint "Z6" "NOTSP_REG"
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104 "Register other than stack pointer (register 6)")
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105 (define_memory_constraint "Za" "R0 push/pop"
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106 (match_test "pushpop_regeq (op, 0)"))
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107 (define_memory_constraint "Zb" "R1 push/pop"
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108 (match_test "pushpop_regeq (op, 1)"))
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109 (define_memory_constraint "Zc" "R2 push/pop"
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110 (match_test "pushpop_regeq (op, 2)"))
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111 (define_memory_constraint "Zd" "R3 push/pop"
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112 (match_test "pushpop_regeq (op, 3)"))
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113 (define_memory_constraint "Ze" "R4 push/pop"
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114 (match_test "pushpop_regeq (op, 4)"))
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115 (define_memory_constraint "Zf" "R5 push/pop"
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116 (match_test "pushpop_regeq (op, 5)"))
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117 (define_memory_constraint "Zg" "SP push/pop"
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118 (match_test "pushpop_regeq (op, 6)"))
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119