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1 ;; Predicate description for RISC-V target.
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2 ;; Copyright (C) 2011-2020 Free Software Foundation, Inc.
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3 ;; Contributed by Andrew Waterman (andrew@sifive.com).
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4 ;; Based on MIPS target for GNU compiler.
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5 ;;
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6 ;; This file is part of GCC.
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7 ;;
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8 ;; GCC is free software; you can redistribute it and/or modify
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9 ;; it under the terms of the GNU General Public License as published by
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10 ;; the Free Software Foundation; either version 3, or (at your option)
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11 ;; any later version.
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12 ;;
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13 ;; GCC is distributed in the hope that it will be useful,
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14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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16 ;; GNU General Public License for more details.
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17 ;;
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18 ;; You should have received a copy of the GNU General Public License
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19 ;; along with GCC; see the file COPYING3. If not see
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20 ;; <http://www.gnu.org/licenses/>.
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21
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22 (define_predicate "const_arith_operand"
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23 (and (match_code "const_int")
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24 (match_test "SMALL_OPERAND (INTVAL (op))")))
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25
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26 (define_predicate "arith_operand"
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27 (ior (match_operand 0 "const_arith_operand")
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28 (match_operand 0 "register_operand")))
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29
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145
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30 (define_predicate "lui_operand"
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31 (and (match_code "const_int")
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32 (match_test "LUI_OPERAND (INTVAL (op))")))
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33
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34 (define_predicate "sfb_alu_operand"
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35 (ior (match_operand 0 "arith_operand")
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36 (match_operand 0 "lui_operand")))
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37
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111
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38 (define_predicate "const_csr_operand"
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39 (and (match_code "const_int")
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40 (match_test "IN_RANGE (INTVAL (op), 0, 31)")))
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41
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42 (define_predicate "csr_operand"
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43 (ior (match_operand 0 "const_csr_operand")
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44 (match_operand 0 "register_operand")))
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45
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46 (define_predicate "sle_operand"
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47 (and (match_code "const_int")
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48 (match_test "SMALL_OPERAND (INTVAL (op) + 1)")))
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49
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50 (define_predicate "sleu_operand"
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51 (and (match_operand 0 "sle_operand")
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52 (match_test "INTVAL (op) + 1 != 0")))
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53
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54 (define_predicate "const_0_operand"
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55 (and (match_code "const_int,const_wide_int,const_double,const_vector")
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56 (match_test "op == CONST0_RTX (GET_MODE (op))")))
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57
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58 (define_predicate "reg_or_0_operand"
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59 (ior (match_operand 0 "const_0_operand")
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60 (match_operand 0 "register_operand")))
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61
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62 ;; Only use branch-on-bit sequences when the mask is not an ANDI immediate.
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63 (define_predicate "branch_on_bit_operand"
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64 (and (match_code "const_int")
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65 (match_test "INTVAL (op) >= IMM_BITS - 1")))
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66
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67 ;; A legitimate CONST_INT operand that takes more than one instruction
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68 ;; to load.
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69 (define_predicate "splittable_const_int_operand"
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70 (match_code "const_int")
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71 {
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72 /* Don't handle multi-word moves this way; we don't want to introduce
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73 the individual word-mode moves until after reload. */
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74 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD)
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75 return false;
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76
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77 /* Otherwise check whether the constant can be loaded in a single
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78 instruction. */
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79 return !LUI_OPERAND (INTVAL (op)) && !SMALL_OPERAND (INTVAL (op));
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80 })
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81
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82 (define_predicate "p2m1_shift_operand"
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83 (match_code "const_int")
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84 {
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85 int val = exact_log2 (INTVAL (op) + 1);
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86 if (val < 12)
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87 return false;
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88 return true;
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89 })
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90
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91 (define_predicate "high_mask_shift_operand"
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92 (match_code "const_int")
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93 {
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94 int val1 = clz_hwi (~ INTVAL (op));
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95 int val0 = ctz_hwi (INTVAL (op));
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96 if ((val0 + val1 == BITS_PER_WORD)
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97 && val0 > 31 && val0 < 64)
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98 return true;
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99 return false;
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100 })
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101
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102 (define_predicate "move_operand"
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103 (match_operand 0 "general_operand")
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104 {
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105 enum riscv_symbol_type symbol_type;
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106
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107 /* The thinking here is as follows:
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108
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109 (1) The move expanders should split complex load sequences into
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110 individual instructions. Those individual instructions can
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111 then be optimized by all rtl passes.
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112
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113 (2) The target of pre-reload load sequences should not be used
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114 to store temporary results. If the target register is only
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115 assigned one value, reload can rematerialize that value
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116 on demand, rather than spill it to the stack.
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117
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118 (3) If we allowed pre-reload passes like combine and cse to recreate
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119 complex load sequences, we would want to be able to split the
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120 sequences before reload as well, so that the pre-reload scheduler
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121 can see the individual instructions. This falls foul of (2);
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122 the splitter would be forced to reuse the target register for
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123 intermediate results.
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124
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125 (4) We want to define complex load splitters for combine. These
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126 splitters can request a temporary scratch register, which avoids
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127 the problem in (2). They allow things like:
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128
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129 (set (reg T1) (high SYM))
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130 (set (reg T2) (low (reg T1) SYM))
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131 (set (reg X) (plus (reg T2) (const_int OFFSET)))
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132
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133 to be combined into:
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134
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135 (set (reg T3) (high SYM+OFFSET))
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136 (set (reg X) (lo_sum (reg T3) SYM+OFFSET))
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137
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138 if T2 is only used this once. */
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139 switch (GET_CODE (op))
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140 {
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141 case CONST_INT:
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142 return !splittable_const_int_operand (op, mode);
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143
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144 case CONST:
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145 case SYMBOL_REF:
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146 case LABEL_REF:
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147 return riscv_symbolic_constant_p (op, &symbol_type)
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148 && !riscv_split_symbol_type (symbol_type);
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149
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150 case HIGH:
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151 op = XEXP (op, 0);
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152 return riscv_symbolic_constant_p (op, &symbol_type)
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153 && riscv_split_symbol_type (symbol_type)
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154 && symbol_type != SYMBOL_PCREL;
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155
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156 default:
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157 return true;
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158 }
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159 })
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160
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161 (define_predicate "symbolic_operand"
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162 (match_code "const,symbol_ref,label_ref")
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163 {
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164 enum riscv_symbol_type type;
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165 return riscv_symbolic_constant_p (op, &type);
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166 })
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167
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168 (define_predicate "absolute_symbolic_operand"
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169 (match_code "const,symbol_ref,label_ref")
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170 {
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171 enum riscv_symbol_type type;
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172 return (riscv_symbolic_constant_p (op, &type)
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173 && (type == SYMBOL_ABSOLUTE || type == SYMBOL_PCREL));
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174 })
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175
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176 (define_predicate "plt_symbolic_operand"
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177 (match_code "const,symbol_ref,label_ref")
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178 {
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179 enum riscv_symbol_type type;
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180 return (riscv_symbolic_constant_p (op, &type)
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181 && type == SYMBOL_GOT_DISP && !SYMBOL_REF_WEAK (op) && TARGET_PLT);
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182 })
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183
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184 (define_predicate "call_insn_operand"
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185 (ior (match_operand 0 "absolute_symbolic_operand")
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186 (match_operand 0 "plt_symbolic_operand")
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187 (match_operand 0 "register_operand")))
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188
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189 (define_predicate "modular_operator"
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190 (match_code "plus,minus,mult,ashift"))
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191
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192 (define_predicate "equality_operator"
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193 (match_code "eq,ne"))
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194
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195 (define_predicate "order_operator"
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196 (match_code "eq,ne,lt,ltu,le,leu,ge,geu,gt,gtu"))
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197
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198 (define_predicate "signed_order_operator"
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199 (match_code "eq,ne,lt,le,ge,gt"))
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200
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201 (define_predicate "fp_native_comparison"
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202 (match_code "eq,lt,le,gt,ge"))
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203
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204 (define_predicate "fp_scc_comparison"
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205 (match_code "unordered,ordered,unlt,unge,unle,ungt,ltgt,ne,eq,lt,le,gt,ge"))
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206
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207 (define_predicate "fp_branch_comparison"
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208 (match_code "unordered,ordered,unlt,unge,unle,ungt,uneq,ltgt,ne,eq,lt,le,gt,ge"))
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