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1 ;; Machine Description for Renesas RL78 processors
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2 ;; Copyright (C) 2011-2020 Free Software Foundation, Inc.
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3 ;; Contributed by Red Hat.
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4
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5 ;; This file is part of GCC.
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6
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7 ;; GCC is free software; you can redistribute it and/or modify
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8 ;; it under the terms of the GNU General Public License as published by
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9 ;; the Free Software Foundation; either version 3, or (at your option)
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10 ;; any later version.
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11
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12 ;; GCC is distributed in the hope that it will be useful,
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13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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15 ;; GNU General Public License for more details.
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16
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17 ;; You should have received a copy of the GNU General Public License
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18 ;; along with GCC; see the file COPYING3. If not see
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19 ;; <http://www.gnu.org/licenses/>.
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20
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21 ;;---------- Moving ------------------------
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22
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23 (define_expand "movqi"
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24 [(set (match_operand:QI 0 "nonimmediate_operand")
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25 (match_operand:QI 1 "general_operand"))]
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26 ""
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27 {
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28 if (MEM_P (operands[0]) && MEM_P (operands[1]))
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29 operands[1] = copy_to_mode_reg (QImode, operands[1]);
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30 if (rl78_far_p (operands[0]) && rl78_far_p (operands[1]))
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31 operands[1] = copy_to_mode_reg (QImode, operands[1]);
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32
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33 /* GCC can generate (SUBREG (SYMBOL_REF)) when it has to store a symbol
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34 into a bitfield, or a packed ordinary field. We can handle this
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35 provided that the destination is a register. If not, then load the
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36 source into a register first. */
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37 if (GET_CODE (operands[1]) == SUBREG
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38 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
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39 && ! REG_P (operands[0]))
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40 operands[1] = copy_to_mode_reg (QImode, operands[1]);
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41
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42 /* Similarly for (SUBREG (CONST (PLUS (SYMBOL_REF)))).
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43 cf. g++.dg/abi/packed.C. */
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44 if (GET_CODE (operands[1]) == SUBREG
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45 && GET_CODE (XEXP (operands[1], 0)) == CONST
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46 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == PLUS
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47 && GET_CODE (XEXP (XEXP (XEXP (operands[1], 0), 0), 0)) == SYMBOL_REF
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48 && ! REG_P (operands[0]))
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49 operands[1] = copy_to_mode_reg (QImode, operands[1]);
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50
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51 if (CONST_INT_P (operands[1]) && ! IN_RANGE (INTVAL (operands[1]), (HOST_WIDE_INT_M1U << 8) + 1, (1 << 8) - 1))
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52 FAIL;
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53 }
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54 )
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55
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56 (define_expand "movhi"
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57 [(set (match_operand:HI 0 "nonimmediate_operand")
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58 (match_operand:HI 1 "general_operand"))]
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59 ""
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60 {
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61 if (MEM_P (operands[0]) && MEM_P (operands[1]))
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62 operands[1] = copy_to_mode_reg (HImode, operands[1]);
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63 if (rl78_far_p (operands[0]) && rl78_far_p (operands[1]))
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64 operands[1] = copy_to_mode_reg (HImode, operands[1]);
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65
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66 /* FIXME: Not sure how GCC can generate (SUBREG (SYMBOL_REF)),
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67 but it does. Since this makes no sense, reject it here. */
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68 if (GET_CODE (operands[1]) == SUBREG
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69 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
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70 FAIL;
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71 /* Similarly for (SUBREG (CONST (PLUS (SYMBOL_REF)))). */
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72 if (GET_CODE (operands[1]) == SUBREG
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73 && GET_CODE (XEXP (operands[1], 0)) == CONST
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74 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == PLUS
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75 && GET_CODE (XEXP (XEXP (XEXP (operands[1], 0), 0), 0)) == SYMBOL_REF)
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76 FAIL;
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77 }
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78 )
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79
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80 (define_insn_and_split "movsi"
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81 [(set (match_operand:SI 0 "nonimmediate_operand" "=vYS,v,Wfr")
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82 (match_operand:SI 1 "general_operand" "viYS,Wfr,v"))]
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83 ""
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84 "#"
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85 ""
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86 [(set (match_operand:HI 2 "nonimmediate_operand")
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87 (match_operand:HI 4 "general_operand"))
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88 (set (match_operand:HI 3 "nonimmediate_operand")
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89 (match_operand:HI 5 "general_operand"))]
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90 "rl78_split_movsi (operands, SImode);"
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91 [(set_attr "valloc" "op1")]
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92 )
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93
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94 (define_insn_and_split "movsf"
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95 [(set (match_operand:SF 0 "nonimmediate_operand" "=vYS,v,Wfr")
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96 (match_operand:SF 1 "general_operand" "viYS,Wfr,v"))]
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97 ""
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98 "#"
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99 ""
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100 [(set (match_operand:HI 2 "nonimmediate_operand")
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101 (match_operand:HI 4 "general_operand"))
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102 (set (match_operand:HI 3 "nonimmediate_operand")
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103 (match_operand:HI 5 "general_operand"))]
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104 "rl78_split_movsi (operands, SFmode);"
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105 [(set_attr "valloc" "op1")]
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106 )
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107
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108 (define_expand "bswaphi2"
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109 [(set (match_operand:HI 0 "nonimmediate_operand")
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110 (bswap:HI (match_operand:HI 1 "general_operand")))]
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111 ""
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112 "if (rl78_force_nonfar_2 (operands, gen_bswaphi2))
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113 DONE;"
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114 )
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115
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111
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116 ;;---------- Conversions ------------------------
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117
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118 (define_expand "zero_extendqihi2"
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119 [(set (match_operand:HI 0 "nonimmediate_operand")
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120 (zero_extend:HI (match_operand:QI 1 "general_operand")))]
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121 ""
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122 "if (rl78_force_nonfar_2 (operands, gen_zero_extendqihi2))
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123 DONE;"
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124 )
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125
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126 (define_expand "extendqihi2"
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127 [(set (match_operand:HI 0 "nonimmediate_operand")
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128 (sign_extend:HI (match_operand:QI 1 "general_operand")))]
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129 ""
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130 "if (rl78_force_nonfar_2 (operands, gen_extendqihi2))
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131 DONE;"
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132 )
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133
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134 ;;---------- Arithmetic ------------------------
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135
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136 (define_expand "add<mode>3"
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137 [(set (match_operand:QHI 0 "nonimmediate_operand")
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138 (plus:QHI (match_operand:QHI 1 "general_operand")
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139 (match_operand:QHI 2 "general_operand")))
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140 ]
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141 ""
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142 "if (rl78_force_nonfar_3 (operands, gen_add<mode>3))
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143 DONE;"
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144 )
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145
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146 (define_expand "sub<mode>3"
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147 [(set (match_operand:QHI 0 "nonimmediate_operand")
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148 (minus:QHI (match_operand:QHI 1 "general_operand")
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149 (match_operand:QHI 2 "general_operand")))
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150 ]
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151 ""
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152 "if (rl78_force_nonfar_3 (operands, gen_sub<mode>3))
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153 DONE;"
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154 )
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155
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156 (define_expand "neg<mode>2"
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157 [(set (match_operand:QHI 0 "nonimmediate_operand")
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158 (minus:QHI (const_int 0)
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159 (match_operand:QHI 1 "general_operand")))
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160 ]
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161 ""
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162 "if (rl78_force_nonfar_2 (operands, gen_neg<mode>2))
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163 DONE;"
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164 )
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165
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166 (define_expand "umulqihi3"
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167 [(set (match_operand:HI 0 "register_operand")
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168 (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand"))
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169 (zero_extend:HI (match_operand:QI 2 "register_operand"))))]
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170 ""
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171 ""
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172 )
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173
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174 (define_expand "andqi3"
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175 [(set (match_operand:QI 0 "rl78_nonimmediate_operand")
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176 (and:QI (match_operand:QI 1 "rl78_general_operand")
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177 (match_operand:QI 2 "rl78_general_operand")))
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178 ]
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179 ""
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180 "if (rl78_force_nonfar_3 (operands, gen_andqi3))
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181 DONE;"
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182 )
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183
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184 (define_expand "iorqi3"
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185 [(set (match_operand:QI 0 "rl78_nonimmediate_operand")
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186 (ior:QI (match_operand:QI 1 "rl78_general_operand")
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187 (match_operand:QI 2 "rl78_general_operand")))
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188 ]
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189 ""
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190 "if (rl78_force_nonfar_3 (operands, gen_iorqi3))
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191 DONE;"
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192 )
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193
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194 (define_expand "xorqi3"
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195 [(set (match_operand:QI 0 "rl78_nonimmediate_operand")
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196 (xor:QI (match_operand:QI 1 "rl78_general_operand")
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197 (match_operand:QI 2 "rl78_general_operand")))
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198 ]
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199 ""
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200 "if (rl78_force_nonfar_3 (operands, gen_xorqi3))
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201 DONE;"
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202 )
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203
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204 (define_expand "one_cmplqi2"
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205 [(set (match_operand:QI 0 "nonimmediate_operand")
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206 (xor:QI (match_operand:QI 1 "general_operand")
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207 (const_int -1)))
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208 ]
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209 ""
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210 "if (rl78_force_nonfar_2 (operands, gen_one_cmplqi2))
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211 DONE;"
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212 )
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213
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214 ;;---------- Shifts ------------------------
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215
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216 (define_expand "ashl<mode>3"
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217 [(set (match_operand:QHI 0 "nonimmediate_operand")
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218 (ashift:QHI (match_operand:QHI 1 "general_operand")
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219 (match_operand:QI 2 "general_operand")))
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220 ]
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221 ""
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222 "if (rl78_force_nonfar_3 (operands, gen_ashl<mode>3))
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223 DONE;"
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224 )
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225
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226 (define_expand "ashr<mode>3"
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227 [(set (match_operand:QHI 0 "nonimmediate_operand")
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228 (ashiftrt:QHI (match_operand:QHI 1 "general_operand")
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229 (match_operand:QI 2 "general_operand")))
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230 ]
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231 ""
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232 "if (rl78_force_nonfar_3 (operands, gen_ashr<mode>3))
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233 DONE;"
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234 )
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235
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236 (define_expand "lshr<mode>3"
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237 [(set (match_operand:QHI 0 "nonimmediate_operand")
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238 (lshiftrt:QHI (match_operand:QHI 1 "general_operand")
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239 (match_operand:QI 2 "general_operand")))
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240 ]
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241 ""
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242 "if (rl78_force_nonfar_3 (operands, gen_lshr<mode>3))
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243 DONE;"
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244 )
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245
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246 (define_expand "ashrsi3"
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247 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand")
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248 (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand")
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249 (match_operand:SI 2 "nonmemory_operand")))
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250 (clobber (reg:HI X_REG))])
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251 ]
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252 ""
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253 ""
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254 )
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255
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256 (define_expand "lshrsi3"
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257 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand")
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258 (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand")
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259 (match_operand:SI 2 "nonmemory_operand")))
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260 (clobber (reg:HI X_REG))])
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261 ]
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262 ""
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263 ""
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264 )
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265
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266 (define_expand "ashlsi3"
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267 [(parallel [(set (match_operand:SI 0 "nonimmediate_operand")
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268 (ashift:SI (match_operand:SI 1 "nonimmediate_operand")
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269 (match_operand:SI 2 "nonmemory_operand")))
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270 (clobber (reg:HI X_REG))])
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271 ]
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272 ""
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273 ""
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274 )
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275
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276 ;;---------- Branching ------------------------
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277
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278 (define_expand "indirect_jump"
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279 [(set (pc)
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280 (match_operand:HI 0 "nonimmediate_operand"))]
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281 ""
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282 ""
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283 )
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284
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285 (define_expand "call"
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286 [(call (match_operand:HI 0 "memory_operand")
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287 (match_operand 1 ""))]
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288 ""
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289 ""
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290 )
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291
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292 (define_expand "call_value"
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293 [(set (match_operand 0 "register_operand")
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294 (call (match_operand:HI 1 "memory_operand")
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295 (match_operand 2 "")))]
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296 ""
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297 ""
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298 )
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299
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300 (define_expand "cbranchqi4"
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301 [(set (pc) (if_then_else
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302 (match_operator 0 "rl78_cmp_operator"
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303 [(match_operand:QI 1 "general_operand")
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304 (match_operand:QI 2 "general_operand")])
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305 (label_ref (match_operand 3 "" ""))
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306 (pc)))]
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307 ""
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308 "rl78_expand_compare (operands);"
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309 )
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310
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311 (define_expand "cbranchhi4"
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312 [(set (pc) (if_then_else
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313 (match_operator 0 "rl78_cmp_operator"
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314 [(match_operand:HI 1 "general_operand")
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315 (match_operand:HI 2 "general_operand")])
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316 (label_ref (match_operand 3 "" ""))
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317 (pc)))]
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318 ""
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319 "rl78_expand_compare (operands);"
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320 )
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321
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322 (define_expand "cbranchsi4"
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323 [(parallel [(set (pc) (if_then_else
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324 (match_operator 0 "rl78_cmp_operator"
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325 [(match_operand:SI 1 "general_operand")
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326 (match_operand:SI 2 "nonmemory_operand")])
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327 (label_ref (match_operand 3 "" ""))
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328 (pc)))
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329 (clobber (reg:HI AX_REG))
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330 ])]
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331 "1"
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332 "rl78_expand_compare (operands);"
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333 )
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