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1 ;; Scheduling description for Renesas SH4a
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2 ;; Copyright (C) 2003-2020 Free Software Foundation, Inc.
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3 ;;
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4 ;; This file is part of GCC.
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5 ;;
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6 ;; GNU CC is free software; you can redistribute it and/or modify
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7 ;; it under the terms of the GNU General Public License as published by
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8 ;; the Free Software Foundation; either version 3, or (at your option)
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9 ;; any later version.
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10 ;;
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11 ;; GNU CC is distributed in the hope that it will be useful,
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12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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14 ;; GNU General Public License for more details.
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15 ;;
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16 ;; You should have received a copy of the GNU General Public License
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17 ;; along with GCC; see the file COPYING3. If not see
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18 ;; <http://www.gnu.org/licenses/>.
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19
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20 ;; The following description models the SH4A pipeline
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21 ;; using the DFA based scheduler.
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22 (define_automaton "sh4a")
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23
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24 (define_cpu_unit "sh4a_ex" "sh4a")
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25 (define_cpu_unit "sh4a_ls" "sh4a")
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26 (define_cpu_unit "sh4a_fex" "sh4a")
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27 (define_cpu_unit "sh4a_fls" "sh4a")
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28 (define_cpu_unit "sh4a_mult" "sh4a")
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29 (define_cpu_unit "sh4a_fdiv" "sh4a")
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30
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31 ;; Decoding is done on the integer pipeline like the
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32 ;; sh4. Define issue to be the | of the two pipelines
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33 ;; to control how often instructions are issued.
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34 (define_reservation "ID_or" "sh4a_ex|sh4a_ls")
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35 (define_reservation "ID_and" "sh4a_ex+sh4a_ls")
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36
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37 ;; =======================================================
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38 ;; Locking Descriptions
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39
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40 ;; Sh4a_Memory access on the LS pipeline.
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41 (define_cpu_unit "sh4a_memory" "sh4a")
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42
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43 ;; Other access on the LS pipeline.
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44 (define_cpu_unit "sh4a_load_store" "sh4a")
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45
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46 ;; The address calculator used for branch instructions.
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47 ;; This will be reserved after "issue" of branch instructions
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48 ;; and this is to make sure that no two branch instructions
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49 ;; can be issued in parallel.
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50 (define_reservation "sh4a_addrcalc" "sh4a_ex")
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51
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52 ;; =======================================================
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53 ;; Reservations
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54
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55 ;; Branch (BF,BF/S,BT,BT/S,BRA,BSR)
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56 ;; Group: BR
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57 ;; Latency when taken: 2
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58 (define_insn_reservation "sh4a_branch" 2
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59 (and (eq_attr "cpu" "sh4a")
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60 (eq_attr "type" "cbranch,jump"))
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61 "ID_or+sh4a_addrcalc")
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62
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63 ;; Jump (JSR,JMP,RTS)
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64 ;; Group: BR
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65 ;; Latency: 3
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66 (define_insn_reservation "sh4a_jump" 3
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67 (and (eq_attr "cpu" "sh4a")
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68 (eq_attr "type" "return,jump_ind"))
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69 "ID_or+sh4a_addrcalc")
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70
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71 ;; RTE
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72 ;; Group: CO
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73 ;; Latency: 3
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74 (define_insn_reservation "sh4a_rte" 3
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75 (and (eq_attr "cpu" "sh4a")
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76 (eq_attr "type" "rte"))
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77 "ID_and*4")
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78
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79 ;; EX Group Single
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80 ;; Group: EX
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81 ;; Latency: 0
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82 (define_insn_reservation "sh4a_ex" 0
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83 (and (eq_attr "cpu" "sh4a")
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84 (eq_attr "insn_class" "ex_group"))
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85 "sh4a_ex")
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86
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87 ;; MOVA
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88 ;; Group: LS
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89 ;; Latency: 1
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90 (define_insn_reservation "sh4a_mova" 1
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91 (and (eq_attr "cpu" "sh4a")
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92 (eq_attr "type" "mova"))
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93 "sh4a_ls+sh4a_load_store")
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94
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95 ;; MOV
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96 ;; Group: MT
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97 ;; Latency: 0
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98 ;; ??? not sure if movi8 belongs here, but that's where it was
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99 ;; effectively before.
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100 (define_insn_reservation "sh4a_mov" 0
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101 (and (eq_attr "cpu" "sh4a")
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102 (eq_attr "type" "move,movi8,gp_mac"))
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103 "ID_or")
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104
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105 ;; Load
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106 ;; Group: LS
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107 ;; Latency: 3
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108 (define_insn_reservation "sh4a_load" 3
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109 (and (eq_attr "cpu" "sh4a")
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110 (eq_attr "type" "load,pcload,mem_mac"))
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111 "sh4a_ls+sh4a_memory")
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112
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113 (define_insn_reservation "sh4a_load_si" 3
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114 (and (eq_attr "cpu" "sh4a")
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115 (eq_attr "type" "load_si,pcload_si"))
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116 "sh4a_ls+sh4a_memory")
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117
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118 ;; Store
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119 ;; Group: LS
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120 ;; Latency: 0
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121 (define_insn_reservation "sh4a_store" 0
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122 (and (eq_attr "cpu" "sh4a")
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123 (eq_attr "type" "store,fstore,mac_mem"))
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124 "sh4a_ls+sh4a_memory")
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125
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126 ;; CWB TYPE
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127
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128 ;; MOVUA
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129 ;; Group: LS
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130 ;; Latency: 3
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131 (define_insn_reservation "sh4a_movua" 3
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132 (and (eq_attr "cpu" "sh4a")
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133 (eq_attr "type" "movua"))
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134 "sh4a_ls+sh4a_memory*2")
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135
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136 ;; Fixed point multiplication (single)
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137 ;; Group: CO
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138 ;; Latency: 2
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139 (define_insn_reservation "sh4a_smult" 2
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140 (and (eq_attr "cpu" "sh4a")
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141 (eq_attr "type" "smpy"))
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142 "ID_or+sh4a_mult")
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143
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144 ;; Fixed point multiplication (double)
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145 ;; Group: CO
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146 ;; Latency: 3
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147 (define_insn_reservation "sh4a_dmult" 3
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148 (and (eq_attr "cpu" "sh4a")
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149 (eq_attr "type" "dmpy"))
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150 "ID_or+sh4a_mult")
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151
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152 (define_insn_reservation "sh4a_mac_gp" 3
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153 (and (eq_attr "cpu" "sh4a")
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154 (eq_attr "type" "mac_gp"))
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155 "ID_and")
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156
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157 ;; Other MT group instructions(1 step operations)
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158 ;; Group: MT
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159 ;; Latency: 1
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160 (define_insn_reservation "sh4a_mt" 1
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161 (and (eq_attr "cpu" "sh4a")
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162 (eq_attr "type" "mt_group"))
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163 "ID_or")
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164
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165 ;; Floating point reg move
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166 ;; Group: LS
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167 ;; Latency: 2
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168 (define_insn_reservation "sh4a_freg_mov" 2
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169 (and (eq_attr "cpu" "sh4a")
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170 (eq_attr "type" "fmove"))
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171 "sh4a_ls,sh4a_fls")
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172
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173 ;; Single precision floating point computation FCMP/EQ,
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174 ;; FCMP/GT, FADD, FLOAT, FMAC, FMUL, FSUB, FTRC, FRVHG, FSCHG
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175 ;; Group: FE
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176 ;; Latency: 3
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177 (define_insn_reservation "sh4a_fp_arith" 3
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178 (and (eq_attr "cpu" "sh4a")
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179 (eq_attr "type" "fp,fp_cmp,fpscr_toggle"))
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180 "ID_or,sh4a_fex")
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181
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182 (define_insn_reservation "sh4a_fp_arith_ftrc" 3
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183 (and (eq_attr "cpu" "sh4a")
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184 (eq_attr "type" "ftrc_s"))
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185 "ID_or,sh4a_fex")
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186
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187 ;; Single-precision FDIV/FSQRT
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188 ;; Group: FE
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189 ;; Latency: 20
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190 (define_insn_reservation "sh4a_fdiv" 20
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191 (and (eq_attr "cpu" "sh4a")
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192 (eq_attr "type" "fdiv"))
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193 "ID_or,sh4a_fex+sh4a_fdiv,sh4a_fex")
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194
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195 ;; Double Precision floating point computation
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196 ;; (FCNVDS, FCNVSD, FLOAT, FTRC)
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197 ;; Group: FE
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198 ;; Latency: 3
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199 (define_insn_reservation "sh4a_dp_float" 3
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200 (and (eq_attr "cpu" "sh4a")
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201 (eq_attr "type" "dfp_conv"))
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202 "ID_or,sh4a_fex")
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203
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204 ;; Double-precision floating-point (FADD,FMUL,FSUB)
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205 ;; Group: FE
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206 ;; Latency: 5
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207 (define_insn_reservation "sh4a_fp_double_arith" 5
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208 (and (eq_attr "cpu" "sh4a")
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209 (eq_attr "type" "dfp_arith,dfp_mul"))
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210 "ID_or,sh4a_fex*3")
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211
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212 ;; Double precision FDIV/SQRT
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213 ;; Group: FE
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214 ;; Latency: 36
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215 (define_insn_reservation "sh4a_dp_div" 36
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216 (and (eq_attr "cpu" "sh4a")
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217 (eq_attr "type" "dfdiv"))
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218 "ID_or,sh4a_fex+sh4a_fdiv,sh4a_fex*2")
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219
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220 ;; FSRRA
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221 ;; Group: FE
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222 ;; Latency: 5
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223 (define_insn_reservation "sh4a_fsrra" 5
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224 (and (eq_attr "cpu" "sh4a")
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225 (eq_attr "type" "fsrra"))
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226 "ID_or,sh4a_fex")
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227
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228 ;; FSCA
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229 ;; Group: FE
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230 ;; Latency: 7
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231 (define_insn_reservation "sh4a_fsca" 7
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232 (and (eq_attr "cpu" "sh4a")
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233 (eq_attr "type" "fsca"))
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234 "ID_or,sh4a_fex*3")
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