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1 ;; Scheduling description for GR5.
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2 ;; Copyright (C) 2013-2020 Free Software Foundation, Inc.
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3 ;;
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4 ;; This file is part of GCC.
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5 ;;
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6 ;; GCC is free software; you can redistribute it and/or modify
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7 ;; it under the terms of the GNU General Public License as published by
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8 ;; the Free Software Foundation; either version 3, or (at your option)
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9 ;; any later version.
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10 ;;
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11 ;; GCC is distributed in the hope that it will be useful,
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12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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14 ;; GNU General Public License for more details.
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15 ;;
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16 ;; You should have received a copy of the GNU General Public License
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17 ;; along with GCC; see the file COPYING3. If not see
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18 ;; <http://www.gnu.org/licenses/>.
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19
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20 ;; GR5 is a single-issue processor.
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21
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22 ;; CPU execution units:
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23 ;;
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24 ;; issue Only one instruction can be issued on a given cycle.
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25 ;; There is no need to model the CPU pipeline in any
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26 ;; more detail than this.
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27 ;;
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28 ;; mem Memory Unit: all accesses to memory.
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29 ;;
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30 ;; eam Extended Arithmetic Module: multiply, divide and
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31 ;; 64-bit shifts.
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32 ;;
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33 ;; fp_slot[0|1|2|3] The 4 FIFO slots of the floating-point unit. Only
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34 ;; the instruction at slot 0 can execute, but an FP
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35 ;; instruction can issue if any of the slots is free.
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36
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37 (define_automaton "gr5,gr5_fpu")
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38
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39 (define_cpu_unit "gr5_issue" "gr5")
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40 (define_cpu_unit "gr5_mem" "gr5")
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41 (define_cpu_unit "gr5_eam" "gr5")
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42 (define_cpu_unit "gr5_fp_slot0,gr5_fp_slot1,gr5_fp_slot2,gr5_fp_slot3" "gr5_fpu")
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43
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44 ;; The CPU instructions which write to general registers and so do not totally
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45 ;; complete until they reach the store stage of the pipeline. This is not the
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46 ;; complete storage register class: mem_reg, eam_reg and fpu_reg are excluded
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47 ;; since we must keep the reservation sets non-overlapping.
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48 (define_insn_reservation "gr5_storage_register" 1
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49 (and (eq_attr "cpu" "gr5")
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50 (eq_attr "type" "imm_reg,arith,arith2,logic,call"))
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51 "gr5_issue")
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52
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53 (define_insn_reservation "gr5_read_mem" 1
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54 (and (eq_attr "cpu" "gr5")
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55 (eq_attr "type" "mem_reg"))
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56 "gr5_issue + gr5_mem")
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57
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58 ;; The latency of 2 and the reservation of gr5_mem on the second cycle ensures
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59 ;; that no reads will be scheduled on the second cycle, which would otherwise
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60 ;; stall the pipeline for 1 cycle.
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61 (define_insn_reservation "gr5_write_mem" 2
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62 (and (eq_attr "cpu" "gr5")
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63 (eq_attr "type" "reg_mem"))
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64 "gr5_issue, gr5_mem")
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65
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66 ;; Try to avoid the pipeline hazard of addressing off a register that has
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67 ;; not yet been stored.
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68 (define_bypass 2 "gr5_storage_register" "gr5_read_mem" "gr5_hazard_bypass_p")
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69 (define_bypass 2 "gr5_storage_register" "gr5_write_mem" "gr5_hazard_bypass_p")
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70 (define_bypass 2 "gr5_read_mem" "gr5_read_mem" "gr5_hazard_bypass_p")
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71 (define_bypass 2 "gr5_read_mem" "gr5_write_mem" "gr5_hazard_bypass_p")
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72
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73 ;; Other CPU instructions complete by the process stage.
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74 (define_insn_reservation "gr5_cpu_other" 1
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75 (and (eq_attr "cpu" "gr5")
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76 (eq_attr "type" "abs_branch,branch,cmp,ret,rfi,dsi,nop"))
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77 "gr5_issue")
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78
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79 ;; EAM instructions.
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80
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81 (define_insn_reservation "gr5_write_eam" 1
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82 (and (eq_attr "cpu" "gr5")
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83 (eq_attr "type" "reg_eam"))
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84 "gr5_issue")
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85
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86 (define_reservation "gr5_issue_eam" "(gr5_issue + gr5_eam)")
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87
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88 (define_insn_reservation "gr5_read_eam" 1
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89 (and (eq_attr "cpu" "gr5")
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90 (eq_attr "type" "eam_reg"))
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91 "gr5_issue_eam")
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92
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93 ;; Try to avoid the pipeline hazard of addressing off a register that has
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94 ;; not yet been stored.
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95 (define_bypass 2 "gr5_read_eam" "gr5_read_mem" "gr5_hazard_bypass_p")
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96 (define_bypass 2 "gr5_read_eam" "gr5_write_mem" "gr5_hazard_bypass_p")
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97
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98 (define_insn_reservation "gr5_shiftdi" 1
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99 (and (eq_attr "cpu" "gr5")
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100 (eq_attr "type" "shiftdi"))
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101 "gr5_issue_eam")
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102
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103 (define_insn_reservation "gr5_mul" 3
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104 (and (eq_attr "cpu" "gr5")
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105 (eq_attr "type" "mul"))
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106 "gr5_issue_eam, gr5_eam*2")
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107
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108 (define_insn_reservation "gr5_div" 34
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109 (and (eq_attr "cpu" "gr5")
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110 (eq_attr "type" "div"))
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111 "gr5_issue_eam, gr5_eam*33")
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112
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113 (define_insn_reservation "gr5_divd" 66
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114 (and (eq_attr "cpu" "gr5")
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115 (eq_attr "type" "divd"))
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116 "gr5_issue_eam, gr5_eam*65")
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117
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118 ;; FPU instructions.
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119
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120 (define_reservation "gr5_fp_slotany" "(gr5_fp_slot0 | gr5_fp_slot1 | gr5_fp_slot2 | gr5_fp_slot3)")
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121
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122 (define_insn_reservation "gr5_fp_other" 1
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123 (and (eq_attr "cpu" "gr5")
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124 (eq_attr "type" "fp_reg,reg_fp,fcmp"))
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125 "gr5_issue")
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126
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127 (define_insn_reservation "gr5_fp_1cycle" 2
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128 (and (eq_attr "cpu" "gr5")
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129 (eq_attr "type" "fmove,ftoi"))
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130 "gr5_issue + gr5_fp_slotany, gr5_fp_slot0")
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131
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132 (define_insn_reservation "gr5_fp_2cycle" 3
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133 (and (eq_attr "cpu" "gr5")
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134 (eq_attr "type" "itof"))
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135 "gr5_issue + gr5_fp_slotany, gr5_fp_slot0*2")
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136
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137 (define_insn_reservation "gr5_fp_3cycle" 4
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138 (and (eq_attr "cpu" "gr5")
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139 (eq_attr "type" "fp"))
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140 "gr5_issue + gr5_fp_slotany, gr5_fp_slot0*3")
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141
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142 (define_insn_reservation "gr5_fp_30cycle" 31
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143 (and (eq_attr "cpu" "gr5")
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144 (eq_attr "type" "fdiv,fsqrt"))
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145 "gr5_issue + gr5_fp_slotany, gr5_fp_slot0*30")
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