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1 ;; Cavium ThunderX 3 CN11xx pipeline description
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2 ;; Copyright (C) 2020 Free Software Foundation, Inc.
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3 ;;
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4 ;; Contributed by Marvell
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5
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6 ;; This file is part of GCC.
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7
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8 ;; GCC is free software; you can redistribute it and/or modify
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9 ;; it under the terms of the GNU General Public License as published by
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10 ;; the Free Software Foundation; either version 3, or (at your option)
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11 ;; any later version.
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12
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13 ;; GCC is distributed in the hope that it will be useful,
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14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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16 ;; GNU General Public License for more details.
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17
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18 ;; You should have received a copy of the GNU General Public License
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19 ;; along with GCC; see the file COPYING3. If not see
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20 ;; <http://www.gnu.org/licenses/>.
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21
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22 (define_automaton "thunderx3t110, thunderx3t110_advsimd, thunderx3t110_ldst")
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23 (define_automaton "thunderx3t110_mult")
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24
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25 (define_cpu_unit "thunderx3t110_i0" "thunderx3t110")
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26 (define_cpu_unit "thunderx3t110_i1" "thunderx3t110")
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27 (define_cpu_unit "thunderx3t110_i2" "thunderx3t110")
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28 (define_cpu_unit "thunderx3t110_i3" "thunderx3t110")
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29
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30 (define_cpu_unit "thunderx3t110_ls0" "thunderx3t110_ldst")
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31 (define_cpu_unit "thunderx3t110_ls1" "thunderx3t110_ldst")
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32 (define_cpu_unit "thunderx3t110_sd" "thunderx3t110_ldst")
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33
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34 ; Pseudo-units for multiply pipeline.
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35 ; unchanged from TX2, occupies I1 for four (1 + 3 additional) slots
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36
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37 (define_cpu_unit "thunderx3t110_i1m1" "thunderx3t110_mult")
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38 (define_cpu_unit "thunderx3t110_i1m2" "thunderx3t110_mult")
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39 (define_cpu_unit "thunderx3t110_i1m3" "thunderx3t110_mult")
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40
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41 ; Pseudo-units for load delay (assuming dcache hit).
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42
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43 (define_cpu_unit "thunderx3t110_ls0d1" "thunderx3t110_ldst")
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44 (define_cpu_unit "thunderx3t110_ls0d2" "thunderx3t110_ldst")
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45 (define_cpu_unit "thunderx3t110_ls0d3" "thunderx3t110_ldst")
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46
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47 (define_cpu_unit "thunderx3t110_ls1d1" "thunderx3t110_ldst")
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48 (define_cpu_unit "thunderx3t110_ls1d2" "thunderx3t110_ldst")
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49 (define_cpu_unit "thunderx3t110_ls1d3" "thunderx3t110_ldst")
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50
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51 ; Define FP units f0/f1/f2/f3.
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52 (define_cpu_unit "thunderx3t110_f0" "thunderx3t110_advsimd")
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53 (define_cpu_unit "thunderx3t110_f1" "thunderx3t110_advsimd")
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54 (define_cpu_unit "thunderx3t110_f2" "thunderx3t110_advsimd")
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55 (define_cpu_unit "thunderx3t110_f3" "thunderx3t110_advsimd")
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56
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57 (define_reservation "thunderx3t110_i23" "thunderx3t110_i2|thunderx3t110_i3")
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58 (define_reservation "thunderx3t110_i01"
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59 "thunderx3t110_i0|thunderx3t110_i1")
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60 (define_reservation "thunderx3t110_i012"
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61 "thunderx3t110_i0|thunderx3t110_i1|thunderx3t110_i2")
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62 (define_reservation "thunderx3t110_i0123"
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63 "thunderx3t110_i0|thunderx3t110_i1|thunderx3t110_i2|thunderx3t110_i3")
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64 (define_reservation "thunderx3t110_ls01" "thunderx3t110_ls0|thunderx3t110_ls1")
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65 (define_reservation "thunderx3t110_f01" "thunderx3t110_f0|thunderx3t110_f1")
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66 (define_reservation "thunderx3t110_f23" "thunderx3t110_f2|thunderx3t110_f3")
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67 (define_reservation "thunderx3t110_f0123"
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68 "thunderx3t110_f0|thunderx3t110_f1|thunderx3t110_f2|thunderx3t110_f3")
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69
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70 ; A load with delay in the ls0/ls1 pipes.
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71 ; this is always a delay of four
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72 (define_reservation "thunderx3t110_l0delay"
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73 "thunderx3t110_ls0,thunderx3t110_ls0d1,thunderx3t110_ls0d2,\
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74 thunderx3t110_ls0d3")
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75 (define_reservation "thunderx3t110_l1delay"
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76 "thunderx3t110_ls1,thunderx3t110_ls1d1,thunderx3t110_ls1d2,\
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77 thunderx3t110_ls1d3")
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78 (define_reservation "thunderx3t110_l01delay"
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79 "thunderx3t110_l0delay|thunderx3t110_l1delay")
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80 ;; Branch and call instructions.
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81
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82 (define_insn_reservation "thunderx3t110_branch" 1
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83 (and (eq_attr "tune" "thunderx3t110")
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84 (eq_attr "type" "call,branch,trap"))
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85 "thunderx3t110_i23")
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86
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87 ;; Misc instructions.
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88
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89 ; Speculation barrier
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90 (define_insn_reservation "thunderx3t110_nothing" 0
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91 (and (eq_attr "tune" "thunderx3t110")
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92 (eq_attr "type" "block"))
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93 "nothing")
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94
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95 (define_insn_reservation "thunderx3t110_mrs" 0
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96 (and (eq_attr "tune" "thunderx3t110")
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97 (eq_attr "type" "mrs"))
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98 "thunderx3t110_i2")
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99
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100 (define_insn_reservation "thunderx3t110_multiple" 1
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101 (and (eq_attr "tune" "thunderx3t110")
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102 (eq_attr "type" "multiple"))
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103 "thunderx3t110_i0+thunderx3t110_i1+thunderx3t110_i3+thunderx3t110_ls0+\
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104 thunderx3t110_ls1+thunderx3t110_sd+thunderx3t110_i1m1+thunderx3t110_i1m2+\
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105 thunderx3t110_i1m3+thunderx3t110_f0+thunderx3t110_f1")
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106
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107 ;; Integer arithmetic/logic instructions.
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108
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109 ; Plain register moves are handled by renaming,
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110 ; and don't create any uops.
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111 (define_insn_reservation "thunderx3t110_regmove" 0
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112 (and (eq_attr "tune" "thunderx3t110")
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113 (eq_attr "type" "mov_reg"))
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114 "nothing")
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115
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116 (define_insn_reservation "thunderx3t110_alu_basic" 1
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117 (and (eq_attr "tune" "thunderx3t110")
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118 (eq_attr "type" "alu_imm,alu_sreg,alus_imm,alus_sreg,\
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119 adc_reg,adc_imm,adcs_reg,adcs_imm,\
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120 logic_reg,logic_imm,logics_reg,logics_imm,\
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121 csel,adr,mov_imm,shift_reg,shift_imm,bfm,\
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122 bfx,rbit,rev,extend,rotate_imm"))
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123 "thunderx3t110_i0123")
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124
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125 ; distinguish between latency 1|2 and throughput 1/4|2/4?
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126 ; is it actually 1,1/2,{i0,i1} vs 2,1/4,{i0,i1,i2,i3}
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127 (define_insn_reservation "thunderx3t110_alu_shift" 2
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128 (and (eq_attr "tune" "thunderx3t110")
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129 (eq_attr "type" "alu_shift_imm,alu_ext,\
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130 alus_shift_imm,alus_ext,\
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131 logic_shift_imm,logics_shift_imm"))
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132 "thunderx3t110_i0123")
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133
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134 (define_insn_reservation "thunderx3t110_alu_shift1" 1
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135 (and (eq_attr "tune" "thunderx3t110")
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136 (eq_attr "type" "alu_shift_imm,alu_ext,\
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137 alus_shift_imm,alus_ext,\
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138 logic_shift_imm,logics_shift_imm"))
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139 "thunderx3t110_i01")
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140
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141 ; we are going for the the optimistic answer (13)
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142 ; for now, the worst case is 23
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143 (define_insn_reservation "thunderx3t110_div" 13
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144 (and (eq_attr "tune" "thunderx3t110")
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145 (eq_attr "type" "sdiv,udiv"))
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146 "thunderx3t110_i1*3")
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147
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148 (define_insn_reservation "thunderx3t110_madd" 5
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149 (and (eq_attr "tune" "thunderx3t110")
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150 (eq_attr "type" "mla,smlal,umlal"))
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151 "thunderx3t110_i0123,thunderx3t110_i1m1,thunderx3t110_i1m2,thunderx3t110_i1m3,\
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152 thunderx3t110_i012")
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153
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154 ; NOTE: smull, umull are used for "high part" multiplies too.
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155 ; mul is alias for MADD
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156 ; it has to be distinguished between smulh, umulh (4,1) and
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157 ; other (5,1) but there is no such a type, so, we go for the
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158 ; conservative approach of (5,1) for now
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159 ; smulh, umulh only runs on I1
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160 (define_insn_reservation "thunderx3t110_mul" 5
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161 (and (eq_attr "tune" "thunderx3t110")
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162 (eq_attr "type" "mul,smull,umull"))
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163 "thunderx3t110_i0123,thunderx3t110_i1m1,thunderx3t110_i1m2,thunderx3t110_i1m3")
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164
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165 (define_insn_reservation "thunderx3t110_countbits" 3
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166 (and (eq_attr "tune" "thunderx3t110")
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167 (eq_attr "type" "clz"))
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168 "thunderx3t110_i1")
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169
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170 ;; Integer loads and stores.
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171
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172 ; load_4 matches prefetch, a multitude of move/str/dup variants,
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173 ; sign extend
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174 (define_insn_reservation "thunderx3t110_load_basic" 4
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175 (and (eq_attr "tune" "thunderx3t110")
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176 (eq_attr "type" "load_4"))
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177 "thunderx3t110_ls01")
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178
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179 ; model use of I0/I1/I2 for index versions only, model 4|8 2nd on load
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180 (define_insn_reservation "thunderx3t110_loadpair" 5
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181 (and (eq_attr "tune" "thunderx3t110")
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182 (eq_attr "type" "load_8,load_16"))
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183 "thunderx3t110_i012,thunderx3t110_ls01")
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184
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185 (define_insn_reservation "thunderx3t110_store_basic" 1
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186 (and (eq_attr "tune" "thunderx3t110")
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187 (eq_attr "type" "store_4"))
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188 "thunderx3t110_ls01,thunderx3t110_sd")
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189
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190 ; model use of I0/I1/I2/I3 for index versions, model differing
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191 ; throughputs
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192 (define_insn_reservation "thunderx3t110_storepair_basic" 1
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193 (and (eq_attr "tune" "thunderx3t110")
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194 (eq_attr "type" "store_8,store_16"))
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195 "thunderx3t110_ls01,thunderx3t110_sd")
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196
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197 ;; FP data processing instructions.
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198
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199 (define_insn_reservation "thunderx3t110_fp_simple" 5
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200 (and (eq_attr "tune" "thunderx3t110")
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201 (eq_attr "type" "ffariths,ffarithd,f_minmaxs,f_minmaxd"))
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202 "thunderx3t110_f0123")
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203
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204 ; distinguish latency 3/4 throughput 1/2|1/4
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205 (define_insn_reservation "thunderx3t110_fp_addsub3" 3
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206 (and (eq_attr "tune" "thunderx3t110")
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207 (eq_attr "type" "fadds,faddd"))
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208 "thunderx3t110_f23")
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209 (define_insn_reservation "thunderx3t110_fp_addsub4" 4
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210 (and (eq_attr "tune" "thunderx3t110")
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211 (eq_attr "type" "fadds,faddd"))
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212 "thunderx3t110_f0123")
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213
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214 (define_insn_reservation "thunderx3t110_fp_cmp" 4
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215 (and (eq_attr "tune" "thunderx3t110")
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216 (eq_attr "type" "fcmps,fcmpd,fccmps,fccmpd"))
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217 "thunderx3t110_f0123")
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218
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219 ; need to split out latency 23 throughput 23/4: F64 from
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220 ; latency 16 throughput 16/4: FDIV F32
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221 (define_insn_reservation "thunderx3t110_fp_divsqrt_s" 16
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222 (and (eq_attr "tune" "thunderx3t110")
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223 (eq_attr "type" "fdivs,fsqrts"))
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224 "thunderx3t110_f0*3|thunderx3t110_f1*3|\
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225 thunderx3t110_f2*3|thunderx3t110_f3*3")
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226
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227 (define_insn_reservation "thunderx3t110_fp_divsqrt_d" 23
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228 (and (eq_attr "tune" "thunderx3t110")
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229 (eq_attr "type" "fdivd,fsqrtd"))
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230 "thunderx3t110_f0*5|thunderx3t110_f1*5|\
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231 thunderx3t110_f2*5|thunderx3t110_f3*5")
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232
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233 (define_insn_reservation "thunderx3t110_fp_mul_mac" 5
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234 (and (eq_attr "tune" "thunderx3t110")
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235 (eq_attr "type" "fmuls,fmuld,fmacs,fmacd"))
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236 "thunderx3t110_f01")
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237
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238 (define_insn_reservation "thunderx3t110_frint" 5
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239 (and (eq_attr "tune" "thunderx3t110")
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240 (eq_attr "type" "f_rints,f_rintd"))
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241 "thunderx3t110_f0123")
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242
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243 ; mimic latency 3|4 throughput 1/2|1/4
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244 (define_insn_reservation "thunderx3t110_fcsel3" 3
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245 (and (eq_attr "tune" "thunderx3t110")
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246 (eq_attr "type" "fcsel"))
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247 "thunderx3t110_f23")
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248
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249 (define_insn_reservation "thunderx3t110_fcsel4" 4
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250 (and (eq_attr "tune" "thunderx3t110")
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251 (eq_attr "type" "fcsel"))
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252 "thunderx3t110_f0123")
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253
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254 ;; FP miscellaneous instructions.
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255
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256 (define_insn_reservation "thunderx3t110_fp_cvt" 5
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257 (and (eq_attr "tune" "thunderx3t110")
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258 (eq_attr "type" "f_cvtf2i,f_cvt,f_cvti2f"))
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259 "thunderx3t110_f0123")
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260
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261 ; even though f_mrc has to belong to fp_mov_to_gen
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262 ; we retain this for the sake of legacy as codegen
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263 ; doesn't use it anyway
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264 (define_insn_reservation "thunderx3t110_fp_mov3" 3
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265 (and (eq_attr "tune" "thunderx3t110")
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266 (eq_attr "type" "fconsts,fconstd,fmov,f_mrc"))
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267 "thunderx3t110_f23")
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268
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269 (define_insn_reservation "thunderx3t110_fp_mov" 4
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270 (and (eq_attr "tune" "thunderx3t110")
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271 (eq_attr "type" "fconsts,fconstd,fmov,f_mrc"))
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272 "thunderx3t110_f0123")
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273
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274 (define_insn_reservation "thunderx3t110_fp_mov_to_gen" 4
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275 (and (eq_attr "tune" "thunderx3t110")
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276 (eq_attr "type" "f_mcr"))
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277 "thunderx3t110_f0123")
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278
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279 ;; FP loads and stores.
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280 ; model use of I0/I1/I2 for post/pre index modes
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281
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282 (define_insn_reservation "thunderx3t110_fp_load_basic" 4
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283 (and (eq_attr "tune" "thunderx3t110")
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284 (eq_attr "type" "f_loads,f_loadd"))
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285 "thunderx3t110_ls01")
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286
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287 ; model throughput 1
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288 (define_insn_reservation "thunderx3t110_fp_store_basic" 1
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289 (and (eq_attr "tune" "thunderx3t110")
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290 (eq_attr "type" "f_stores,f_stored"))
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291 "thunderx3t110_ls01,thunderx3t110_sd")
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292
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293 ;; ASIMD integer instructions.
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294
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295 (define_insn_reservation "thunderx3t110_asimd_int" 5
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296 (and (eq_attr "tune" "thunderx3t110")
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297 (eq_attr "type" "neon_abd,neon_abd_q,\
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298 neon_arith_acc,neon_arith_acc_q,\
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299 neon_abs,neon_abs_q,\
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300 neon_add,neon_add_q,\
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301 neon_sub,neon_sub_q,\
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302 neon_neg,neon_neg_q,\
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303 neon_add_long,neon_add_widen,\
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304 neon_add_halve,neon_add_halve_q,\
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305 neon_sub_long,neon_sub_widen,\
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306 neon_sub_halve,neon_sub_halve_q,\
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307 neon_add_halve_narrow_q,neon_sub_halve_narrow_q,\
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308 neon_qabs,neon_qabs_q,\
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309 neon_qadd,neon_qadd_q,\
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310 neon_qneg,neon_qneg_q,\
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311 neon_qsub,neon_qsub_q,\
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312 neon_minmax,neon_minmax_q,\
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313 neon_reduc_minmax,neon_reduc_minmax_q,\
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314 neon_mul_b,neon_mul_h,neon_mul_s,\
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315 neon_mul_b_q,neon_mul_h_q,neon_mul_s_q,\
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316 neon_sat_mul_b,neon_sat_mul_h,neon_sat_mul_s,\
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317 neon_sat_mul_b_q,neon_sat_mul_h_q,neon_sat_mul_s_q,\
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318 neon_mla_b,neon_mla_h,neon_mla_s,\
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319 neon_mla_b_q,neon_mla_h_q,neon_mla_s_q,\
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320 neon_mul_b_long,neon_mul_h_long,\
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321 neon_mul_s_long,neon_mul_d_long,\
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322 neon_sat_mul_b_long,neon_sat_mul_h_long,\
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323 neon_sat_mul_s_long,\
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324 neon_mla_b_long,neon_mla_h_long,neon_mla_s_long,\
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325 neon_sat_mla_b_long,neon_sat_mla_h_long,\
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326 neon_sat_mla_s_long,\
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327 neon_shift_acc,neon_shift_acc_q,\
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328 neon_shift_imm,neon_shift_imm_q,\
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329 neon_shift_reg,neon_shift_reg_q,\
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330 neon_shift_imm_long,neon_shift_imm_narrow_q,\
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331 neon_sat_shift_imm,neon_sat_shift_imm_q,\
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332 neon_sat_shift_reg,neon_sat_shift_reg_q,\
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333 neon_sat_shift_imm_narrow_q"))
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334 "thunderx3t110_f0123")
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335
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336 ; neon_reduc_add is used for both addp and [su]adalp
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337 (define_insn_reservation "thunderx3t110_asimd_reduc_add" 5
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338 (and (eq_attr "tune" "thunderx3t110")
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339 (eq_attr "type" "neon_reduc_add,neon_reduc_add_q"))
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340 "thunderx3t110_f01")
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341
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342 (define_insn_reservation "thunderx3t110_asimd_cmp" 5
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343 (and (eq_attr "tune" "thunderx3t110")
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344 (eq_attr "type" "neon_compare,neon_compare_q,neon_compare_zero,\
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345 neon_tst,neon_tst_q"))
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346 "thunderx3t110_f0123")
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347
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348 ; neon_logic used in ldr, str, mov, umov, fmov, mov; orn; bic; and,
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349 ; simd mov immediate; orr, simd mov immediate; eor; not (mvn)
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350 ; latency 4 throughput 1/2 LS0/LS1: ldr
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351 ; latency 1 throughput 1 LS0/LS1,SDI,I0/I1/I2: str
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352 ; latency 3|4 throughput 1/2|1/4 F2/F3 F0/F1/F2/F3: fmov immed, orn,
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353 ; bic, and, orr, eor, not (mvn)
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354 ; latency 4 throughput 1/4 F0/F1/F2/F3: fmov register, fmov gen to vec
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355 ; latency 5 throughput 1/4 F0/F1/F2/F3: fmov vec to gen, umov, fmov
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356 (define_insn_reservation "thunderx3t110_asimd_logic4" 4
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357 (and (eq_attr "tune" "thunderx3t110")
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358 (eq_attr "type" "neon_logic,neon_logic_q"))
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359 "thunderx3t110_f23")
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360
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361 (define_insn_reservation "thunderx3t110_asimd_logic5" 5
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362 (and (eq_attr "tune" "thunderx3t110")
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363 (eq_attr "type" "neon_logic,neon_logic_q"))
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364 "thunderx3t110_f0123")
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365
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366 ;; ASIMD floating-point instructions.
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367
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368 ; Distinguish between latency 5 throughput 1/4: fabs, fmax, fmin, fneg
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369 ; latency 4 throughput 1/4: fcmp
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370 (define_insn_reservation "thunderx3t110_asimd_fp_simple" 5
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371 (and (eq_attr "tune" "thunderx3t110")
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372 (eq_attr "type" "neon_fp_abs_s,neon_fp_abs_d,\
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373 neon_fp_abs_s_q,neon_fp_abs_d_q,\
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374 neon_fp_compare_s,neon_fp_compare_d,\
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375 neon_fp_compare_s_q,neon_fp_compare_d_q,\
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376 neon_fp_minmax_s,neon_fp_minmax_d,\
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377 neon_fp_minmax_s_q,neon_fp_minmax_d_q,\
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378 neon_fp_reduc_minmax_s,neon_fp_reduc_minmax_d,\
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379 neon_fp_reduc_minmax_s_q,neon_fp_reduc_minmax_d_q,\
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380 neon_fp_neg_s,neon_fp_neg_d,\
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381 neon_fp_neg_s_q,neon_fp_neg_d_q"))
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382 "thunderx3t110_f0123")
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383
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384 ; distinguish between latency 3 throughput 1/2,
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385 ; latency 4 throughput 1/4
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386 ; neon_fp_reduc_add_<stype><q> is used for both faddp and
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387 ; vector reduction add. On TX3, faddp is 3|4 1/2|1/4 and reduction is 5 1/4
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388 (define_insn_reservation "thunderx3t110_asimd_fp_arith3" 3
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389 (and (eq_attr "tune" "thunderx3t110")
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390 (eq_attr "type" "neon_fp_abd_s,neon_fp_abd_d,\
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391 neon_fp_abd_s_q,neon_fp_abd_d_q,\
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392 neon_fp_addsub_s,neon_fp_addsub_d,\
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393 neon_fp_addsub_s_q,neon_fp_addsub_d_q,\
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|
394 neon_fp_reduc_add_s,neon_fp_reduc_add_d,\
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|
395 neon_fp_reduc_add_s_q,neon_fp_reduc_add_d_q"))
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396 "thunderx3t110_f23")
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397
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398 (define_insn_reservation "thunderx3t110_asimd_fp_arith4" 4
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399 (and (eq_attr "tune" "thunderx3t110")
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400 (eq_attr "type" "neon_fp_abd_s,neon_fp_abd_d,\
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401 neon_fp_abd_s_q,neon_fp_abd_d_q,\
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|
402 neon_fp_addsub_s,neon_fp_addsub_d,\
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|
|
403 neon_fp_addsub_s_q,neon_fp_addsub_d_q,\
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|
404 neon_fp_reduc_add_s,neon_fp_reduc_add_d,\
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|
|
405 neon_fp_reduc_add_s_q,neon_fp_reduc_add_d_q"))
|
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|
406 "thunderx3t110_f0123")
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407
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|
408 (define_insn_reservation "thunderx3t110_asimd_fp_arith5" 5
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|
409 (and (eq_attr "tune" "thunderx3t110")
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|
410 (eq_attr "type" "neon_fp_mul_s,neon_fp_mul_d,\
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|
411 neon_fp_mul_s_q,neon_fp_mul_d_q,\
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|
412 neon_fp_mul_s_scalar_q,neon_fp_mul_d_scalar_q,\
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|
|
413 neon_fp_mla_s,neon_fp_mla_d,\
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|
|
414 neon_fp_mla_s_q,neon_fp_mla_d_q"))
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|
415 "thunderx3t110_f0123")
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416
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417 ; neon_fp_cvt_widen_s,neon_fp_cvt_narrow_d_q: fcvtl,fctvl2,fcvtn,fcvtn2
|
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|
418 ; neon_fp_to_int_s,neon_fp_to_int_d: fcvt{<frint_suffix><su>,z<su>}
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|
419 ; where frint_suffix: zpmixan, su: su (plus other sign/unsign/extract...
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420 ; neon_fp_to_int_s_q,neon_fp_to_int_d_q: fcvtz<su> other
|
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|
421 ; The int_to_fp* is complicated
|
|
|
422 ; neon_int_to_fp_s,neon_int_to_fp_d: <su_optab>cvtf
|
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|
423 ; neon_int_to_fp_s_q,neon_int_to_fp_d_q
|
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|
424 ; Round matches single define_insn, frint<frint_suffix>
|
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|
425 ; neon_fp_round_s,neon_fp_round_d,neon_fp_round_s_q,
|
|
|
426 ; neon_fp_round_d_q: frint<frint_suffix>
|
|
|
427 ; FCVT*,VCVTAU,[SU]CVTF: latency 5 throughput 1/4
|
|
|
428 ; FRINT*: latency 5 throughput 1/4
|
|
|
429 (define_insn_reservation "thunderx3t110_asimd_fp_conv" 5
|
|
|
430 (and (eq_attr "tune" "thunderx3t110")
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|
|
431 (eq_attr "type" "neon_fp_cvt_widen_s,neon_fp_cvt_narrow_d_q,\
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|
432 neon_fp_to_int_s,neon_fp_to_int_d,\
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|
|
433 neon_fp_to_int_s_q,neon_fp_to_int_d_q,\
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|
|
434 neon_int_to_fp_s,neon_int_to_fp_d,\
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|
|
435 neon_int_to_fp_s_q,neon_int_to_fp_d_q,\
|
|
|
436 neon_fp_round_s,neon_fp_round_d,\
|
|
|
437 neon_fp_round_s_q,neon_fp_round_d_q"))
|
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|
438 "thunderx3t110_f0123")
|
|
|
439
|
|
|
440 ; model that pipeline is occupied the whole time D/F32, Q/F32: 16/4
|
|
|
441 ; Q/F64: 23/4
|
|
|
442 (define_insn_reservation "thunderx3t110_asimd_fp_div_s" 16
|
|
|
443 (and (eq_attr "tune" "thunderx3t110")
|
|
|
444 (eq_attr "type" "neon_fp_div_s,neon_fp_div_s_q"))
|
|
|
445 "thunderx3t110_f0123")
|
|
|
446
|
|
|
447 (define_insn_reservation "thunderx3t110_asimd_fp_div_d" 23
|
|
|
448 (and (eq_attr "tune" "thunderx3t110")
|
|
|
449 (eq_attr "type" "neon_fp_div_d,neon_fp_div_d_q"))
|
|
|
450 "thunderx3t110_f0123")
|
|
|
451
|
|
|
452 ;; ASIMD miscellaneous instructions.
|
|
|
453
|
|
|
454 ; divided out:
|
|
|
455 ; rbit,bsl,bsl_q,cls,cls_q,cnt,cnt_q,move,move_q: 3|4 1/2 | 1/4
|
|
|
456 ; from_gp,from_gp_q : 4 | 1/4
|
|
|
457 ; dup,dup_q,ext,ext_q,ins,ins_q,all recpe forms, rev,rev_q: 5 1/4
|
|
|
458 ; permute,permute_q needs to depend on aarch64_expand_vec_perm_const does
|
|
|
459 ; on TX3
|
|
|
460 (define_insn_reservation "thunderx3t110_asimd_misc3" 3
|
|
|
461 (and (eq_attr "tune" "thunderx3t110")
|
|
|
462 (eq_attr "type" "neon_rbit,\
|
|
|
463 neon_bsl,neon_bsl_q,\
|
|
|
464 neon_cls,neon_cls_q,\
|
|
|
465 neon_cnt,neon_cnt_q,\
|
|
|
466 neon_move,neon_move_q"))
|
|
|
467 "thunderx3t110_f23")
|
|
|
468
|
|
|
469 (define_insn_reservation "thunderx3t110_asimd_misc4" 4
|
|
|
470 (and (eq_attr "tune" "thunderx3t110")
|
|
|
471 (eq_attr "type" "neon_rbit,\
|
|
|
472 neon_bsl,neon_bsl_q,\
|
|
|
473 neon_cls,neon_cls_q,\
|
|
|
474 neon_cnt,neon_cnt_q,\
|
|
|
475 neon_from_gp,neon_from_gp_q,\
|
|
|
476 neon_move,neon_move_q"))
|
|
|
477 "thunderx3t110_f0123")
|
|
|
478
|
|
|
479 (define_insn_reservation "thunderx3t110_asimd_misc" 5
|
|
|
480 (and (eq_attr "tune" "thunderx3t110")
|
|
|
481 (eq_attr "type" "
|
|
|
482 neon_dup,neon_dup_q,\
|
|
|
483 neon_ext,neon_ext_q,\
|
|
|
484 neon_ins,neon_ins_q,\
|
|
|
485 neon_move,neon_move_q,\
|
|
|
486 neon_fp_recpe_s,neon_fp_recpe_d,\
|
|
|
487 neon_fp_recpe_s_q,neon_fp_recpe_d_q,\
|
|
|
488 neon_fp_recpx_s,neon_fp_recpx_d,\
|
|
|
489 neon_fp_recpx_s_q,neon_fp_recpx_d_q,\
|
|
|
490 neon_rev,neon_rev_q,\
|
|
|
491 neon_permute,neon_permute_q"))
|
|
|
492 "thunderx3t110_f0123")
|
|
|
493
|
|
|
494 (define_insn_reservation "thunderx3t110_asimd_recip_step" 5
|
|
|
495 (and (eq_attr "tune" "thunderx3t110")
|
|
|
496 (eq_attr "type" "neon_fp_recps_s,neon_fp_recps_s_q,\
|
|
|
497 neon_fp_recps_d,neon_fp_recps_d_q,\
|
|
|
498 neon_fp_sqrt_s,neon_fp_sqrt_s_q,\
|
|
|
499 neon_fp_sqrt_d,neon_fp_sqrt_d_q,\
|
|
|
500 neon_fp_rsqrte_s, neon_fp_rsqrte_s_q,\
|
|
|
501 neon_fp_rsqrte_d, neon_fp_rsqrte_d_q,\
|
|
|
502 neon_fp_rsqrts_s, neon_fp_rsqrts_s_q,\
|
|
|
503 neon_fp_rsqrts_d, neon_fp_rsqrts_d_q"))
|
|
|
504 "thunderx3t110_f0123")
|
|
|
505
|
|
|
506 (define_insn_reservation "thunderx3t110_asimd_lut1" 5
|
|
|
507 (and (eq_attr "tune" "thunderx3t110")
|
|
|
508 (eq_attr "type" "neon_tbl1,neon_tbl1_q"))
|
|
|
509 "thunderx3t110_f0123")
|
|
|
510
|
|
|
511 (define_insn_reservation "thunderx3t110_asimd_lut2" 10
|
|
|
512 (and (eq_attr "tune" "thunderx3t110")
|
|
|
513 (eq_attr "type" "neon_tbl2,neon_tbl2_q"))
|
|
|
514 "thunderx3t110_f0123")
|
|
|
515
|
|
|
516 (define_insn_reservation "thunderx3t110_asimd_lut3" 15
|
|
|
517 (and (eq_attr "tune" "thunderx3t110")
|
|
|
518 (eq_attr "type" "neon_tbl3,neon_tbl3_q"))
|
|
|
519 "thunderx3t110_f0123")
|
|
|
520
|
|
|
521 (define_insn_reservation "thunderx3t110_asimd_lut4" 20
|
|
|
522 (and (eq_attr "tune" "thunderx3t110")
|
|
|
523 (eq_attr "type" "neon_tbl4,neon_tbl4_q"))
|
|
|
524 "thunderx3t110_f0123")
|
|
|
525
|
|
|
526 (define_insn_reservation "thunderx3t110_asimd_elt_to_gr" 5
|
|
|
527 (and (eq_attr "tune" "thunderx3t110")
|
|
|
528 (eq_attr "type" "neon_to_gp,neon_to_gp_q"))
|
|
|
529 "thunderx3t110_f0123")
|
|
|
530
|
|
|
531 ;; ASIMD load instructions.
|
|
|
532
|
|
|
533 ; NOTE: These reservations attempt to model latency and throughput
|
|
|
534 ; correctly, but the cycle timing of unit allocation is not
|
|
|
535 ; necessarily accurate (because insns are split into uops, and those
|
|
|
536 ; may be issued out-of-order).
|
|
|
537
|
|
|
538 ; the LDP/LDNP imm-offset S/D/Q suppplies the first arg with latency 4
|
|
|
539 ; and the 2nd at 5 (Q form) or 8 (S/D form). Can this be modeled? These
|
|
|
540 ;forms, as documented, do not use the I0/I1/I2 units (no I3), but the
|
|
|
541 ; other LDP ones do.
|
|
|
542 (define_insn_reservation "thunderx3t110_asimd_load1_ldp" 5
|
|
|
543 (and (eq_attr "tune" "thunderx3t110")
|
|
|
544 (eq_attr "type" "neon_ldp,neon_ldp_q"))
|
|
|
545 "thunderx3t110_i012,thunderx3t110_ls01")
|
|
|
546
|
|
|
547 ; Need to distinguish latency 6 throughput 2: 4 reg D/Q
|
|
|
548 ; latency 5 throughput 3/2: 3 reg D/Q
|
|
|
549 ; latency 4 throughput 1: 2 reg D/Q
|
|
|
550 ; latency 4 throughput 1/2: 1 reg D/Q
|
|
|
551 (define_insn_reservation "thunderx3t110_asimd_load1" 4
|
|
|
552 (and (eq_attr "tune" "thunderx3t110")
|
|
|
553 (eq_attr "type" "neon_load1_1reg,neon_load1_1reg_q,\
|
|
|
554 neon_load1_2reg,neon_load1_2reg_q,\
|
|
|
555 neon_load1_3reg,neon_load1_3reg_q,\
|
|
|
556 neon_load1_4reg,neon_load1_4reg_q"))
|
|
|
557 "thunderx3t110_ls01")
|
|
|
558
|
|
|
559 (define_insn_reservation "thunderx3t110_asimd_load1_onelane" 5
|
|
|
560 (and (eq_attr "tune" "thunderx3t110")
|
|
|
561 (eq_attr "type" "neon_load1_one_lane,neon_load1_one_lane_q"))
|
|
|
562 "thunderx3t110_l01delay,thunderx3t110_f0123")
|
|
|
563
|
|
|
564 (define_insn_reservation "thunderx3t110_asimd_load1_all" 5
|
|
|
565 (and (eq_attr "tune" "thunderx3t110")
|
|
|
566 (eq_attr "type" "neon_load1_all_lanes,neon_load1_all_lanes_q"))
|
|
|
567 "thunderx3t110_l01delay,thunderx3t110_f0123")
|
|
|
568
|
|
|
569 (define_insn_reservation "thunderx3t110_asimd_load2" 5
|
|
|
570 (and (eq_attr "tune" "thunderx3t110")
|
|
|
571 (eq_attr "type" "neon_load2_2reg,neon_load2_2reg_q,\
|
|
|
572 neon_load2_one_lane,neon_load2_one_lane_q,\
|
|
|
573 neon_load2_all_lanes,neon_load2_all_lanes_q"))
|
|
|
574 "thunderx3t110_l01delay,thunderx3t110_f0123")
|
|
|
575
|
|
|
576 (define_insn_reservation "thunderx3t110_asimd_load3" 7
|
|
|
577 (and (eq_attr "tune" "thunderx3t110")
|
|
|
578 (eq_attr "type" "neon_load3_3reg,neon_load3_3reg_q,\
|
|
|
579 neon_load3_one_lane,neon_load3_one_lane_q,\
|
|
|
580 neon_load3_all_lanes,neon_load3_all_lanes_q"))
|
|
|
581 "thunderx3t110_l01delay,thunderx3t110_f0123")
|
|
|
582
|
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583 (define_insn_reservation "thunderx3t110_asimd_load4" 8
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584 (and (eq_attr "tune" "thunderx3t110")
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585 (eq_attr "type" "neon_load4_4reg,neon_load4_4reg_q,\
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586 neon_load4_one_lane,neon_load4_one_lane_q,\
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587 neon_load4_all_lanes,neon_load4_all_lanes_q"))
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588 "thunderx3t110_l01delay,thunderx3t110_f0123")
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589
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590 ;; ASIMD store instructions.
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591
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592 ; Same note applies as for ASIMD load instructions.
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593
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594 ; Vector Store pair Need to distinguish:
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595 ; 5 throughput: imm-offset S/D; imm-postindex S/D; imm-preindex S/D
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596 ; 2 throughput: imm-offset Q; imm-postindex Q; imm-preindex Q
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597 ; all index modes use I0/I1/I2
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598 (define_insn_reservation "thunderx3t110_asimd_store_stp" 1
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599 (and (eq_attr "tune" "thunderx3t110")
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600 (eq_attr "type" "neon_stp,neon_stp_q"))
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601 "thunderx3t110_ls01,thunderx3t110_sd")
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602
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603 ; There are multiple forms of ST1
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604 ; The following two groups, as documented, do not use the FP pipelines.
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605 ; multiple, 1 reg, D-form ST1
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606 ; tx2_ltp: x 1/2 LS0/LS1
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607 ; tx3_ltp: x 1/2 LS0/LS1
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608 ; multiple, 1 reg, Q-form ST1
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609 ; tx2_ltp: x 1/2 LS0/LS1
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610 ; tx3_ltp: x 1/2 LS0/LS1
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611 ;
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612 ; one lane, B/H/S ST1
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613 ; tx2_ltp: x 1/2 LS0/LS1,F0/F1
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614 ; tx3_ltp: x 1/2 LS0/LS1,F0/F1/F2/F3
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615 ; one lane, D ST1
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616 ; tx2_ltp: x 1/2 LS0/LS1,F0/F1
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617 ; tx3_ltp: x 1/2 LS0/LS1,F0/F1/F2/F3
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618 ;; Model for st1 insn needs refinement for different register forms
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619 ; multiple, 2 reg, D-form ST1 x 1 LS0/LS1
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620 ; multiple, 2 reg, Q-form ST1 x 1 LS0/LS1
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621 ; multiple, 3 reg, D-form ST1 x 3/2 LS0/LS1
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622 ; multiple, 3 reg, Q-form ST1 x 3/2 LS0/LS1
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623 ; multiple,4 reg, D-form ST1 x 2 LS0/LS1
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624 ; multiple,4 reg, Q-form ST1 x 2 LS0/LS1
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625 (define_insn_reservation "thunderx3t110_asimd_store1" 1
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626 (and (eq_attr "tune" "thunderx3t110")
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627 (eq_attr "type" "neon_store1_1reg,neon_store1_1reg_q,\
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628 neon_store1_2reg,neon_store1_2reg_q,\
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629 neon_store1_3reg,neon_store1_4reg"))
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630 "thunderx3t110_ls01")
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631
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632 (define_insn_reservation "thunderx3t110_asimd_store1_onelane" 1
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633 (and (eq_attr "tune" "thunderx3t110")
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634 (eq_attr "type" "neon_store1_one_lane,neon_store1_one_lane_q"))
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635 "thunderx3t110_ls01,thunderx3t110_f0123")
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636
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637 ; distinguish between throughput 1: D/Q-form B/H/S, Q-form D and
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638 ; throughput 1/2: one lane B/H/S/D
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639 (define_insn_reservation "thunderx3t110_asimd_store2" 1
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640 (and (eq_attr "tune" "thunderx3t110")
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641 (eq_attr "type" "neon_store2_2reg,neon_store2_2reg_q,\
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642 neon_store2_one_lane,neon_store2_one_lane_q"))
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643 "thunderx3t110_ls01,thunderx3t110_f0123")
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644
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645 ; distinguish between throughput 3: D/Q-form B/H/S, Q-form D and
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646 ; throughput 1: one lane B/H/S/D
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647 (define_insn_reservation "thunderx3t110_asimd_store3" 1
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648 (and (eq_attr "tune" "thunderx3t110")
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649 (eq_attr "type" "neon_store3_3reg,neon_store3_3reg_q,\
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650 neon_store3_one_lane,neon_store3_one_lane_q"))
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651 "thunderx3t110_ls01,thunderx3t110_f0123")
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652
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653 ; distinguish between throughput 4: D/Q-form B/H/S, Q-form D and
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654 ; throughput 1: one lane B/H/S/D? (not in doc)
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655 (define_insn_reservation "thunderx3t110_asimd_store4" 1
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656 (and (eq_attr "tune" "thunderx3t110")
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657 (eq_attr "type" "neon_store4_4reg,neon_store4_4reg_q,\
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658 neon_store4_one_lane,neon_store4_one_lane_q"))
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659 "thunderx3t110_ls01,thunderx3t110_f0123")
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660
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661 ;; Crypto extensions.
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662
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663 (define_insn_reservation "thunderx3t110_aes" 4
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664 (and (eq_attr "tune" "thunderx3t110")
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665 (eq_attr "type" "crypto_aese,crypto_aesmc"))
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666 "thunderx3t110_f0123")
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667
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668 (define_insn_reservation "thunderx3t110_sha" 5
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669 (and (eq_attr "tune" "thunderx3t110")
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670 (eq_attr "type" "crypto_sha1_fast,crypto_sha1_xor,crypto_sha1_slow,\
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671 crypto_sha256_fast,crypto_sha256_slow"))
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672 "thunderx3t110_f0123")
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673
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674 ;; CRC extension.
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675
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676 (define_insn_reservation "thunderx3t110_crc" 3
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677 (and (eq_attr "tune" "thunderx3t110")
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678 (eq_attr "type" "crc"))
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679 "thunderx3t110_i1")
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680
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681 ;; PMULL extension.
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682
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683 (define_insn_reservation "thunderx3t110_pmull" 5
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684 (and (eq_attr "tune" "thunderx3t110")
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685 (eq_attr "type" "crypto_pmull"))
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686 "thunderx3t110_f0123")
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