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annotate gcc/config/arm/cortex-m4.md @ 68:561a7518be6b

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update gcc-4.6
author Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
date Sun, 21 Aug 2011 07:07:55 +0900
parents
children 04ced10e8804
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rev   line source
68
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
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1 ;; ARM Cortex-M4 pipeline description
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
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2 ;; Copyright (C) 2010 Free Software Foundation, Inc.
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
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3 ;; Contributed by CodeSourcery.
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
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4 ;;
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
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5 ;; This file is part of GCC.
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
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6 ;;
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
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7 ;; GCC is free software; you can redistribute it and/or modify it
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
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8 ;; under the terms of the GNU General Public License as published by
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9 ;; the Free Software Foundation; either version 3, or (at your option)
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10 ;; any later version.
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11 ;;
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12 ;; GCC is distributed in the hope that it will be useful, but
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13 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
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14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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15 ;; General Public License for more details.
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
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16 ;;
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
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17 ;; You should have received a copy of the GNU General Public License
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18 ;; along with GCC; see the file COPYING3. If not see
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19 ;; <http://www.gnu.org/licenses/>.
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20
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21 (define_automaton "cortex_m4")
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22
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23 ;; We model the pipelining of LDR instructions by using two artificial units.
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24
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25 (define_cpu_unit "cortex_m4_a" "cortex_m4")
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26
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27 (define_cpu_unit "cortex_m4_b" "cortex_m4")
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28
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29 (define_reservation "cortex_m4_ex" "cortex_m4_a+cortex_m4_b")
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30
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31 ;; ALU and multiply is one cycle.
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32 (define_insn_reservation "cortex_m4_alu" 1
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33 (and (eq_attr "tune" "cortexm4")
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34 (eq_attr "type" "alu,alu_shift,alu_shift_reg,mult"))
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35 "cortex_m4_ex")
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36
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37 ;; Byte, half-word and word load is two cycles.
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38 (define_insn_reservation "cortex_m4_load1" 2
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39 (and (eq_attr "tune" "cortexm4")
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40 (eq_attr "type" "load_byte,load1"))
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41 "cortex_m4_a, cortex_m4_b")
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42
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43 ;; str rx, [ry, #imm] is always one cycle.
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44 (define_insn_reservation "cortex_m4_store1_1" 1
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45 (and (and (eq_attr "tune" "cortexm4")
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46 (eq_attr "type" "store1"))
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47 (ne (symbol_ref ("arm_address_offset_is_imm (insn)")) (const_int 0)))
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48 "cortex_m4_a")
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49
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50 ;; Other byte, half-word and word load is two cycles.
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51 (define_insn_reservation "cortex_m4_store1_2" 2
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52 (and (and (eq_attr "tune" "cortexm4")
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53 (eq_attr "type" "store1"))
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54 (eq (symbol_ref ("arm_address_offset_is_imm (insn)")) (const_int 0)))
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55 "cortex_m4_a*2")
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56
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57 (define_insn_reservation "cortex_m4_load2" 3
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58 (and (eq_attr "tune" "cortexm4")
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59 (eq_attr "type" "load2"))
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60 "cortex_m4_ex*3")
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61
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62 (define_insn_reservation "cortex_m4_store2" 3
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63 (and (eq_attr "tune" "cortexm4")
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64 (eq_attr "type" "store2"))
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65 "cortex_m4_ex*3")
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66
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67 (define_insn_reservation "cortex_m4_load3" 4
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68 (and (eq_attr "tune" "cortexm4")
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69 (eq_attr "type" "load3"))
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70 "cortex_m4_ex*4")
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71
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72 (define_insn_reservation "cortex_m4_store3" 4
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73 (and (eq_attr "tune" "cortexm4")
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74 (eq_attr "type" "store3"))
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75 "cortex_m4_ex*4")
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76
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77 (define_insn_reservation "cortex_m4_load4" 5
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78 (and (eq_attr "tune" "cortexm4")
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79 (eq_attr "type" "load4"))
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80 "cortex_m4_ex*5")
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81
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82 (define_insn_reservation "cortex_m4_store4" 5
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83 (and (eq_attr "tune" "cortexm4")
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84 (eq_attr "type" "store4"))
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85 "cortex_m4_ex*5")
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86
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87 ;; If the address of load or store depends on the result of the preceding
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88 ;; instruction, the latency is increased by one.
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89
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90 (define_bypass 2 "cortex_m4_alu"
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91 "cortex_m4_load1"
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92 "arm_early_load_addr_dep")
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93
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94 (define_bypass 2 "cortex_m4_alu"
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95 "cortex_m4_store1_1,cortex_m4_store1_2"
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96 "arm_early_store_addr_dep")
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97
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98 (define_insn_reservation "cortex_m4_branch" 3
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99 (and (eq_attr "tune" "cortexm4")
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100 (eq_attr "type" "branch"))
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101 "cortex_m4_ex*3")
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102
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103 (define_insn_reservation "cortex_m4_call" 3
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104 (and (eq_attr "tune" "cortexm4")
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105 (eq_attr "type" "call"))
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106 "cortex_m4_ex*3")
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107
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108 (define_insn_reservation "cortex_m4_block" 1
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109 (and (eq_attr "tune" "cortexm4")
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110 (eq_attr "type" "block"))
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111 "cortex_m4_ex")