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update gcc-4.6
author Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
date Sun, 21 Aug 2011 07:07:55 +0900
parents
children 04ced10e8804
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rev   line source
68
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
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1 ;; Pipeline description for the AppliedMicro Titan core.
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
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2 ;; Copyright (C) 2010 Free Software Foundation, Inc.
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
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3 ;; Contributed by Theobroma Systems Design und Consulting GmbH
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
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4 ;;
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
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5 ;; This file is part of GCC.
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
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6 ;;
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
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7 ;; GCC is free software; you can redistribute it and/or modify it
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
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8 ;; under the terms of the GNU General Public License as published
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9 ;; by the Free Software Foundation; either version 3, or (at your
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
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10 ;; option) any later version.
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11 ;;
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
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12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
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13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
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14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
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15 ;; License for more details.
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
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16 ;;
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
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17 ;; You should have received a copy of the GNU General Public License
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
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18 ;; along with GCC; see the file COPYING3. If not see
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19 ;; <http://www.gnu.org/licenses/>.
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20
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
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21 ;; AppliedMicro Titan core complex
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22
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23 (automata_option "progress")
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24
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25 (define_automaton "titan_core,titan_fpu,titan_fxu,titan_bpu,titan_lsu")
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
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26 (define_cpu_unit "titan_issue_0,titan_issue_1" "titan_core")
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27
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
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28 ;; Some useful abbreviations.
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
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29 (define_reservation "titan_issue" "titan_issue_0|titan_issue_1")
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30
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31 ;; === FXU scheduling ===
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32
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33 (define_cpu_unit "titan_fxu_sh,titan_fxu_wb" "titan_fxu")
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34
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35 ;; The 1-cycle adder executes add, addi, subf, neg, compare and trap
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36 ;; instructions. It provides its own, dedicated result-bus, so we
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37 ;; don't need the titan_fxu_wb reservation to complete.
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38 (define_insn_reservation "titan_fxu_adder" 1
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39 (and (eq_attr "type" "cmp,fast_compare,trap")
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40 (eq_attr "cpu" "titan"))
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41 "titan_issue,titan_fxu_sh")
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42
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43 ;; Keep the titan_imul and titan_mulhw (half-word) rules in order, to
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44 ;; ensure the proper match: the half-word instructions are tagged as
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45 ;; imul3 only, whereas regular multiplys will always carry a imul tag.
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46
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47 (define_insn_reservation "titan_imul" 5
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48 (and (eq_attr "type" "imul,imul2,imul_compare")
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49 (eq_attr "cpu" "titan"))
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50 "titan_issue,titan_fxu_sh,nothing*5,titan_fxu_wb")
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51
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52 (define_insn_reservation "titan_mulhw" 4
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53 (and (eq_attr "type" "imul3")
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54 (eq_attr "cpu" "titan"))
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55 "titan_issue,titan_fxu_sh,nothing*4,titan_fxu_wb")
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56
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57 (define_bypass 2 "titan_mulhw" "titan_mulhw")
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58
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59 (define_insn_reservation "titan_fxu_shift_and_rotate" 2
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60 (and (eq_attr "type" "insert_word,shift,var_shift_rotate,cntlz")
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61 (eq_attr "cpu" "titan"))
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62 "titan_issue,titan_fxu_sh,nothing*2,titan_fxu_wb")
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63
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64 ;; We model the divider for the worst-case (i.e. a full 32-bit
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65 ;; divide). To model the bypass for byte-wise completion, a
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66 ;; define_bypass with a guard-function could be used... however, this
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67 ;; would be an optimization of doubtful value, as a large number of
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68 ;; divides will operate on 32-bit variables.
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69
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70 ;; To avoid an unmanagably large automata (generating the automata
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71 ;; would require well over 2GB in memory), we don't model the shared
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72 ;; result bus on this one. The divider-pipeline is thus modeled
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73 ;; through its latency and initial disptach bottlenecks (i.e. issue
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74 ;; slots and fxu scheduler availability)
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75 (define_insn_reservation "titan_fxu_div" 34
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76 (and (eq_attr "type" "idiv")
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77 (eq_attr "cpu" "titan"))
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78 "titan_issue,titan_fxu_sh")
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79
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80 (define_insn_reservation "titan_fxu_alu" 1
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81 (and (eq_attr "type" "integer,exts")
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82 (eq_attr "cpu" "titan"))
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83 "titan_issue,titan_fxu_sh,nothing,titan_fxu_wb")
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84
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85 ;; === BPU scheduling ===
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86
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87 (define_cpu_unit "titan_bpu_sh" "titan_bpu")
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88
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89 (define_insn_reservation "titan_bpu" 2
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90 (and (eq_attr "type" "branch,jmpreg,cr_logical,delayed_cr")
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91 (eq_attr "cpu" "titan"))
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92 "titan_issue,titan_bpu_sh")
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93
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94 ;; === LSU scheduling ===
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95
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96 (define_cpu_unit "titan_lsu_sh" "titan_lsu")
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97
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98 ;; Loads.
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99 (define_insn_reservation "titan_lsu_load" 3
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100 (and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,\
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101 load_l,sync")
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102 (eq_attr "cpu" "titan"))
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103 "titan_issue,titan_lsu_sh")
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104
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105 (define_insn_reservation "titan_lsu_fpload" 12
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106 (and (eq_attr "type" "fpload,fpload_ux,fpload_u")
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107 (eq_attr "cpu" "titan"))
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108 "titan_issue,titan_lsu_sh")
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109
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110 ;; Note that the isync is not clearly placed within any execution
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111 ;; unit. We've made the assumption that it will be running out of the
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112 ;; LSU, as msync is also executed within the LSU.
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113 (define_insn_reservation "titan_lsu_sync" 20
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114 (and (eq_attr "type" "sync")
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115 (eq_attr "cpu" "titan"))
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116 "titan_issue,titan_lsu_sh*20")
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117
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118 ;; Stores.
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119 (define_insn_reservation "titan_lsu_store" 12
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120 (and (eq_attr "type" "store,store_ux,store_u,store_c")
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121 (eq_attr "cpu" "titan"))
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122 "titan_issue,titan_lsu_sh")
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123
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
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124 (define_insn_reservation "titan_lsu_fpstore" 12
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125 (and (eq_attr "type" "fpstore,fpstore_ux,fpstore_u")
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126 (eq_attr "cpu" "titan"))
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127 "titan_issue,titan_lsu_sh")
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
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128
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
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129 ;; === FPU scheduling ===
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130
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
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131 ;; In order to keep the automaton for the Titan FPU efficient and
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132 ;; maintainable, we've kept in as concise as possible and created a
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
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133 ;; mapping for the main "choke points" only instead of modelling the
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
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134 ;; overall flow of instructions through the FP-pipeline(s).
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135
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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136 ;; The key elements modelled are:
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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137 ;; * each FP-instruction takes up one of the two issue slots
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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138 ;; * the FPU runs at half the core frequency
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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139 ;; * divides are not pipelined (but execute in a separate unit)
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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140 ;; * the FPU has a shared result bus for all its units
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141
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
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142 (define_cpu_unit "titan_fp0,titan_fpdiv,titan_fpwb" "titan_fpu")
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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143
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
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144 (define_insn_reservation "titan_fp_div_double" 72
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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145 (and (eq_attr "type" "ddiv")
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parents:
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146 (eq_attr "cpu" "titan"))
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
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147 "titan_issue,titan_fpdiv*72,titan_fpwb")
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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148
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
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149 (define_insn_reservation "titan_fp_div_single" 46
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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150 (and (eq_attr "type" "sdiv")
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parents:
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151 (eq_attr "cpu" "titan"))
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
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152 "titan_issue,titan_fpdiv*46,titan_fpwb")
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
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153
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
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154 (define_insn_reservation "titan_fp_single" 12
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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155 (and (eq_attr "fp_type" "fp_addsub_s,fp_mul_s,fp_maddsub_s")
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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156 (eq_attr "cpu" "titan"))
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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157 "titan_issue,titan_fp0*2,nothing*10,titan_fpwb")
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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158
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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159 ;; Make sure the "titan_fp" rule stays last, as it's a catch all for
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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160 ;; double-precision and unclassified (e.g. fsel) FP-instructions
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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161 (define_insn_reservation "titan_fp" 10
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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162 (and (eq_attr "type" "fpcompare,fp,dmul")
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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163 (eq_attr "cpu" "titan"))
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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164 "titan_issue,titan_fp0*2,nothing*8,titan_fpwb")
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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165
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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166 ;; Please note, that the non-pipelined FP-instructions "mcrfs",
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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167 ;; "mtfsb0[.]", "mtfsb1[.]", "mtfsf[.]", "mtfsfi[.]" are not
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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168 ;; accessible from regular language constructs (i.e. they are not used
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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169 ;; by the code generator, except for special purpose sequences defined
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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170 ;; in rs6000.md), no special provisions are made for these.
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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171