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annotate gcc/config/alpha/vms-unwind.h @ 55:77e2b8dfacca gcc-4.4.5

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update it from 4.4.3 to 4.5.0
author ryoma <e075725@ie.u-ryukyu.ac.jp>
date Fri, 12 Feb 2010 23:39:51 +0900
parents a06113de4d67
children f6334be47118
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55
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1 /* Fallback frame unwinding for Alpha/VMS.
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2 Copyright (C) 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2009
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3 Free Software Foundation, Inc.
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4
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5 This file is part of GCC.
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6
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7 GCC is free software; you can redistribute it and/or modify it
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8 under the terms of the GNU General Public License as published
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9 by the Free Software Foundation; either version 3, or (at your
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10 option) any later version.
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11
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12 GCC is distributed in the hope that it will be useful, but WITHOUT
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13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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15 License for more details.
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16
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17 Under Section 7 of GPL version 3, you are granted additional
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18 permissions described in the GCC Runtime Library Exception, version
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19 3.1, as published by the Free Software Foundation.
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20
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21 You should have received a copy of the GNU General Public License and
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22 a copy of the GCC Runtime Library Exception along with this program;
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23 see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
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24 <http://www.gnu.org/licenses/>. */
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25
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26 #include <stdlib.h>
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27 #include <stdio.h>
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28 #include <vms/pdscdef.h>
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29 #include <vms/libicb.h>
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30 #include <vms/chfctxdef.h>
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31 #include <vms/chfdef.h>
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32
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33 #define MD_FALLBACK_FRAME_STATE_FOR alpha_vms_fallback_frame_state
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34
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35 typedef void * ADDR;
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36 typedef unsigned long long REG;
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37 typedef PDSCDEF * PV;
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38
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39 #define REG_AT(addr) (*(REG *)(addr))
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40 #define ADDR_AT(addr) (*(ADDR *)(addr))
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41
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42 /* Compute pointer to procedure descriptor (Procedure Value) from Frame
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43 Pointer FP, according to the rules in [ABI-3.5.1 Current Procedure]. */
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44 #define PV_FOR(FP) \
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45 (((FP) != 0) \
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46 ? (((REG_AT (FP) & 0x7) == 0) ? *(PDSCDEF **)(FP) : (PDSCDEF *)(FP)) : 0)
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47
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48 extern int SYS$GL_CALL_HANDL;
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49 /* This is actually defined as a "long", but in system code where longs
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50 are always 4bytes while GCC longs might be 8bytes. */
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51
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52 #define UPDATE_FS_FOR_CFA_GR(FS, GRN, LOC, CFA) \
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53 do { \
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54 (FS)->regs.reg[GRN].how = REG_SAVED_OFFSET; \
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55 (FS)->regs.reg[GRN].loc.offset = (_Unwind_Sword) ((REG) (LOC) - (REG) (CFA)); \
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56 } while (0);
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57
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58 #define GIVEUP_ON_FAILURE(STATUS) \
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59 { if ((((STATUS) & 1) != 1)) return _URC_END_OF_STACK; }
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60 #define DENOTES_EXC_DISPATCHER(PV) ((PV) == (ADDR) (REG) SYS$GL_CALL_HANDL)
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61
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62 #define RA_COLUMN (DWARF_ALT_FRAME_RETURN_COLUMN)
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63
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64 static int
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65 alpha_vms_fallback_frame_state (struct _Unwind_Context *context,
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66 _Unwind_FrameState *fs)
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67 {
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68 static int eh_debug = -1;
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69
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70 /* Our goal is to update FS to reflect the state one step up CONTEXT, that
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71 is: the CFA, return address and *saved* registers locations associated
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72 with the function designated by CONTEXT->ra. We are called when the
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73 libgcc unwinder has not found any dwarf FDE for this address, which
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74 typically happens when trying to propagate a language exception through a
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75 signal global vector or frame based handler.
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76
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77 The CONTEXT->reg[] entries reflect the state/location of register saves
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78 so designate values live at the CONTEXT->ra point. Of precious value to
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79 us here is the frame pointer (r29), which gets us a procedure value. */
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80
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81 PV pv = (context->reg[29] != 0) ? PV_FOR (ADDR_AT (context->reg[29])) : 0;
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82
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83 int pkind = pv ? pv->pdsc$w_flags & 0xf : 0;
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84 /* VMS procedure kind, as indicated by the procedure descriptor. We only
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85 know how to deal with FP_STACK or FP_REGISTER here. */
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86
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87 ADDR new_cfa = 0;
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88 /* CFA we will establish for the caller, computed in different ways,
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89 e.g. depending whether we cross an exception dispatcher frame. */
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90
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91 CHFCTX *chfctx = 0;
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92 /* Pointer to the VMS CHF context associated with an exception dispatcher
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93 frame, if we happen to come across one. */
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94
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95 int i,j;
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96
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97 if (eh_debug == -1)
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98 {
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99 char * eh_debug_env = getenv ("EH_DEBUG");
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100 eh_debug = eh_debug_env ? atoi (eh_debug_env) : 0;
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101 }
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102
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103 if (eh_debug)
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104 printf ("MD_FALLBACK running ...\n");
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105
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106 /* We only know how to deal with stack or reg frame procedures, so give
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107 up if we're handed anything else. */
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108 if (pkind != PDSC$K_KIND_FP_STACK && pkind != PDSC$K_KIND_FP_REGISTER)
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109 return _URC_END_OF_STACK;
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110
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111 if (eh_debug)
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112 printf ("FALLBACK: CTX FP = 0x%p, PV = 0x%p, EN = 0x%llx, RA = 0x%p\n",
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113 ADDR_AT (context->reg[29]), pv, pv->pdsc$q_entry, context->ra);
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114
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115 fs->retaddr_column = RA_COLUMN;
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116
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117 /* If PV designates a VMS exception vector or condition handler, we need to
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118 do as if the caller was the signaling point and estabish the state of the
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119 intermediate VMS code (CFA, RA and saved register locations) as if it was
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120 a single regular function. This requires special processing.
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121
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122 The datastructures available from an condition dispatcher frame (signal
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123 context) do not contain the values of most callee-saved registers, so
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124 whathever PV designates, we need to account for the registers it saves.
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125
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126 Besides, we need to express all the locations with respect to a
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127 consistent CFA value, so we compute this first. */
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128
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129 if (DENOTES_EXC_DISPATCHER (pv))
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130 {
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131 /* The CFA to establish is the signaling point's stack pointer. We
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132 compute it using the system invocation context unwinding services and
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133 save the CHF context data pointer along the way for later uses. */
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134
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135 INVO_CONTEXT_BLK icb;
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136 int status, invo_handle;
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137
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138 if (eh_debug)
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139 printf ("FALLBACK: SYS$HANDLER\n");
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140
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141 icb.libicb$q_ireg [29] = REG_AT (context->reg[29]);
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142 icb.libicb$q_ireg [30] = 0;
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143 invo_handle = LIB$GET_INVO_HANDLE (&icb);
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144
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145 status = LIB$GET_INVO_CONTEXT (invo_handle, &icb);
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146 GIVEUP_ON_FAILURE (status);
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147
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148 chfctx = (CHFCTX *) icb.libicb$ph_chfctx_addr;
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149
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150 status = LIB$GET_PREV_INVO_CONTEXT (&icb);
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151 GIVEUP_ON_FAILURE (status);
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152
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153 new_cfa = (ADDR) icb.libicb$q_ireg[30];
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154 }
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155 else
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156 {
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157 /* The CFA to establish is the SP value on entry of the procedure
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158 designated by PV, which we compute as the corresponding frame base
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159 register value + frame size. Note that the frame base may differ
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160 from CONTEXT->cfa, typically if the caller has performed dynamic
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161 stack allocations. */
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162
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163 int base_reg = pv->pdsc$w_flags & PDSC$M_BASE_REG_IS_FP ? 29 : 30;
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164 ADDR base_addr = ADDR_AT (context->reg[base_reg]);
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165
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166 new_cfa = base_addr + pv->pdsc$l_size;
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167 }
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168
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169 /* State to compute the caller's CFA by adding an offset to the current
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170 one in CONTEXT. */
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171 fs->regs.cfa_how = CFA_REG_OFFSET;
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172 fs->regs.cfa_reg = __builtin_dwarf_sp_column ();
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173 fs->regs.cfa_offset = new_cfa - context->cfa;
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174
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175 /* Regular unwind first, accounting for the register saves performed by
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176 the procedure designated by PV. */
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177
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178 switch (pkind)
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179 {
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180 case PDSC$K_KIND_FP_STACK:
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181 {
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182 /* The saved registers are all located in the Register Save Area,
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183 except for the procedure value register (R27) found at the frame
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184 base address. */
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185
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186 int base_reg = pv->pdsc$w_flags & PDSC$M_BASE_REG_IS_FP ? 29 : 30;
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187 ADDR base_addr = ADDR_AT (context->reg[base_reg]);
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188 ADDR rsa_addr = base_addr + pv->pdsc$w_rsa_offset;
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189
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190 if (eh_debug)
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191 printf ("FALLBACK: STACK frame procedure\n");
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192
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193 UPDATE_FS_FOR_CFA_GR (fs, 27, base_addr, new_cfa);
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194
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195 /* The first RSA entry is for the return address register, R26. */
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196
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197 UPDATE_FS_FOR_CFA_GR (fs, 26, rsa_addr, new_cfa);
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198 UPDATE_FS_FOR_CFA_GR (fs, RA_COLUMN, rsa_addr, new_cfa);
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199
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200 /* The following entries are for registers marked as saved according
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201 to ireg_mask. */
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202 for (i = 0, j = 0; i < 32; i++)
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203 if ((1 << i) & pv->pdsc$l_ireg_mask)
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204 UPDATE_FS_FOR_CFA_GR (fs, i, rsa_addr + 8 * ++j, new_cfa);
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205
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206 /* ??? floating point registers ? */
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207
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208 break;
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209 }
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210
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211 case PDSC$K_KIND_FP_REGISTER:
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212 {
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213 if (eh_debug)
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214 printf ("FALLBACK: REGISTER frame procedure\n");
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215
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216 fs->regs.reg[RA_COLUMN].how = REG_SAVED_REG;
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217 fs->regs.reg[RA_COLUMN].loc.reg = pv->pdsc$b_save_ra;
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218
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219 fs->regs.reg[29].how = REG_SAVED_REG;
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220 fs->regs.reg[29].loc.reg = pv->pdsc$b_save_fp;
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diff changeset
221
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222 break;
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223 }
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224
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225 default:
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226 /* Should never reach here. */
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227 return _URC_END_OF_STACK;
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228 }
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diff changeset
229
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230 /* If PV designates an exception dispatcher, we have to adjust the return
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231 address column to get at the signal occurrence point, and account for
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232 for what the CHF context contains. */
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233
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234 if (DENOTES_EXC_DISPATCHER (pv))
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235 {
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236 /* The PC of the instruction causing the condition is available from the
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237 signal argument vector. Extra saved register values are available
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238 from the mechargs array. */
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ryoma <e075725@ie.u-ryukyu.ac.jp>
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239
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240 CHF$SIGNAL_ARRAY *sigargs
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241 = (CHF$SIGNAL_ARRAY *) chfctx->chfctx$q_sigarglst;
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242
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243 CHF$MECH_ARRAY *mechargs
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244 = (CHF$MECH_ARRAY *) chfctx->chfctx$q_mcharglst;
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245
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ryoma <e075725@ie.u-ryukyu.ac.jp>
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246 ADDR condpc_addr
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247 = &((int *)(&sigargs->chf$l_sig_name)) [sigargs->chf$is_sig_args-2];
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248
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249 ADDR rei_frame_addr = (void *) mechargs->chf$q_mch_esf_addr;
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diff changeset
250
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251 /* Adjust the return address location. */
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252
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253 UPDATE_FS_FOR_CFA_GR (fs, RA_COLUMN, condpc_addr, new_cfa);
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254
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255 /* The frame pointer at the condition point is available from the
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ryoma <e075725@ie.u-ryukyu.ac.jp>
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256 chf context directly. */
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257
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258 UPDATE_FS_FOR_CFA_GR (fs, 29, &chfctx->chfctx$q_expt_fp, new_cfa);
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259
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260 /* Registers available from the mechargs array. */
0
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261
55
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262 UPDATE_FS_FOR_CFA_GR (fs, 0, &mechargs->chf$q_mch_savr0, new_cfa);
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263 UPDATE_FS_FOR_CFA_GR (fs, 1, &mechargs->chf$q_mch_savr1, new_cfa);
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264
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265 UPDATE_FS_FOR_CFA_GR (fs, 16, &mechargs->chf$q_mch_savr16, new_cfa);
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266 UPDATE_FS_FOR_CFA_GR (fs, 17, &mechargs->chf$q_mch_savr17, new_cfa);
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267 UPDATE_FS_FOR_CFA_GR (fs, 18, &mechargs->chf$q_mch_savr18, new_cfa);
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268 UPDATE_FS_FOR_CFA_GR (fs, 19, &mechargs->chf$q_mch_savr19, new_cfa);
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269 UPDATE_FS_FOR_CFA_GR (fs, 20, &mechargs->chf$q_mch_savr20, new_cfa);
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270 UPDATE_FS_FOR_CFA_GR (fs, 21, &mechargs->chf$q_mch_savr21, new_cfa);
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ryoma <e075725@ie.u-ryukyu.ac.jp>
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271 UPDATE_FS_FOR_CFA_GR (fs, 22, &mechargs->chf$q_mch_savr22, new_cfa);
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272 UPDATE_FS_FOR_CFA_GR (fs, 23, &mechargs->chf$q_mch_savr23, new_cfa);
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ryoma <e075725@ie.u-ryukyu.ac.jp>
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273 UPDATE_FS_FOR_CFA_GR (fs, 24, &mechargs->chf$q_mch_savr24, new_cfa);
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ryoma <e075725@ie.u-ryukyu.ac.jp>
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274 UPDATE_FS_FOR_CFA_GR (fs, 25, &mechargs->chf$q_mch_savr25, new_cfa);
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ryoma <e075725@ie.u-ryukyu.ac.jp>
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275 UPDATE_FS_FOR_CFA_GR (fs, 26, &mechargs->chf$q_mch_savr26, new_cfa);
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ryoma <e075725@ie.u-ryukyu.ac.jp>
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276 UPDATE_FS_FOR_CFA_GR (fs, 27, &mechargs->chf$q_mch_savr27, new_cfa);
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ryoma <e075725@ie.u-ryukyu.ac.jp>
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277 UPDATE_FS_FOR_CFA_GR (fs, 28, &mechargs->chf$q_mch_savr28, new_cfa);
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ryoma <e075725@ie.u-ryukyu.ac.jp>
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diff changeset
278
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ryoma <e075725@ie.u-ryukyu.ac.jp>
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279 /* Registers R2 to R7 are available from the rei frame pointer. */
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ryoma <e075725@ie.u-ryukyu.ac.jp>
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diff changeset
280
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ryoma <e075725@ie.u-ryukyu.ac.jp>
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281 for (i = 2; i <= 7; i ++)
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ryoma <e075725@ie.u-ryukyu.ac.jp>
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282 UPDATE_FS_FOR_CFA_GR (fs, i, rei_frame_addr+(i - 2)*8, new_cfa);
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ryoma <e075725@ie.u-ryukyu.ac.jp>
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diff changeset
283
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ryoma <e075725@ie.u-ryukyu.ac.jp>
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284 /* ??? floating point registers ? */
0
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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285 }
55
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ryoma <e075725@ie.u-ryukyu.ac.jp>
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286
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287 return _URC_NO_REASON;
0
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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288 }
55
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289
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290
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ryoma <e075725@ie.u-ryukyu.ac.jp>
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291