Mercurial > hg > CbC > CbC_gcc
annotate gcc/config/arm/lib1funcs.asm @ 55:77e2b8dfacca gcc-4.4.5
update it from 4.4.3 to 4.5.0
| author | ryoma <e075725@ie.u-ryukyu.ac.jp> |
|---|---|
| date | Fri, 12 Feb 2010 23:39:51 +0900 |
| parents | a06113de4d67 |
| children | b7f97abdc517 |
| rev | line source |
|---|---|
| 0 | 1 @ libgcc routines for ARM cpu. |
| 2 @ Division routines, written by Richard Earnshaw, (rearnsha@armltd.co.uk) | |
| 3 | |
| 4 /* Copyright 1995, 1996, 1998, 1999, 2000, 2003, 2004, 2005, 2007, 2008, | |
| 5 2009 Free Software Foundation, Inc. | |
| 6 | |
| 7 This file is free software; you can redistribute it and/or modify it | |
| 8 under the terms of the GNU General Public License as published by the | |
| 9 Free Software Foundation; either version 3, or (at your option) any | |
| 10 later version. | |
| 11 | |
| 12 This file is distributed in the hope that it will be useful, but | |
| 13 WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
| 15 General Public License for more details. | |
| 16 | |
| 17 Under Section 7 of GPL version 3, you are granted additional | |
| 18 permissions described in the GCC Runtime Library Exception, version | |
| 19 3.1, as published by the Free Software Foundation. | |
| 20 | |
| 21 You should have received a copy of the GNU General Public License and | |
| 22 a copy of the GCC Runtime Library Exception along with this program; | |
| 23 see the files COPYING3 and COPYING.RUNTIME respectively. If not, see | |
| 24 <http://www.gnu.org/licenses/>. */ | |
| 25 | |
| 26 /* An executable stack is *not* required for these functions. */ | |
| 27 #if defined(__ELF__) && defined(__linux__) | |
| 28 .section .note.GNU-stack,"",%progbits | |
| 29 .previous | |
|
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30 #endif /* __ELF__ and __linux__ */ |
| 0 | 31 |
|
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32 #ifdef __ARM_EABI__ |
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33 /* Some attributes that are common to all routines in this file. */ |
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34 /* Tag_ABI_align8_needed: This code does not require 8-byte |
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35 alignment from the caller. */ |
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36 /* .eabi_attribute 24, 0 -- default setting. */ |
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37 /* Tag_ABI_align8_preserved: This code preserves 8-byte |
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38 alignment in any callee. */ |
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39 .eabi_attribute 25, 1 |
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40 #endif /* __ARM_EABI__ */ |
| 0 | 41 /* ------------------------------------------------------------------------ */ |
| 42 | |
| 43 /* We need to know what prefix to add to function names. */ | |
| 44 | |
| 45 #ifndef __USER_LABEL_PREFIX__ | |
| 46 #error __USER_LABEL_PREFIX__ not defined | |
| 47 #endif | |
| 48 | |
| 49 /* ANSI concatenation macros. */ | |
| 50 | |
| 51 #define CONCAT1(a, b) CONCAT2(a, b) | |
| 52 #define CONCAT2(a, b) a ## b | |
| 53 | |
| 54 /* Use the right prefix for global labels. */ | |
| 55 | |
| 56 #define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) | |
| 57 | |
| 58 #ifdef __ELF__ | |
| 59 #ifdef __thumb__ | |
| 60 #define __PLT__ /* Not supported in Thumb assembler (for now). */ | |
| 61 #elif defined __vxworks && !defined __PIC__ | |
| 62 #define __PLT__ /* Not supported by the kernel loader. */ | |
| 63 #else | |
| 64 #define __PLT__ (PLT) | |
| 65 #endif | |
| 66 #define TYPE(x) .type SYM(x),function | |
| 67 #define SIZE(x) .size SYM(x), . - SYM(x) | |
| 68 #define LSYM(x) .x | |
| 69 #else | |
| 70 #define __PLT__ | |
| 71 #define TYPE(x) | |
| 72 #define SIZE(x) | |
| 73 #define LSYM(x) x | |
| 74 #endif | |
| 75 | |
| 76 /* Function end macros. Variants for interworking. */ | |
| 77 | |
| 78 #if defined(__ARM_ARCH_2__) | |
| 79 # define __ARM_ARCH__ 2 | |
| 80 #endif | |
| 81 | |
| 82 #if defined(__ARM_ARCH_3__) | |
| 83 # define __ARM_ARCH__ 3 | |
| 84 #endif | |
| 85 | |
| 86 #if defined(__ARM_ARCH_3M__) || defined(__ARM_ARCH_4__) \ | |
| 87 || defined(__ARM_ARCH_4T__) | |
| 88 /* We use __ARM_ARCH__ set to 4 here, but in reality it's any processor with | |
| 89 long multiply instructions. That includes v3M. */ | |
| 90 # define __ARM_ARCH__ 4 | |
| 91 #endif | |
| 92 | |
| 93 #if defined(__ARM_ARCH_5__) || defined(__ARM_ARCH_5T__) \ | |
| 94 || defined(__ARM_ARCH_5E__) || defined(__ARM_ARCH_5TE__) \ | |
| 95 || defined(__ARM_ARCH_5TEJ__) | |
| 96 # define __ARM_ARCH__ 5 | |
| 97 #endif | |
| 98 | |
| 99 #if defined(__ARM_ARCH_6__) || defined(__ARM_ARCH_6J__) \ | |
| 100 || defined(__ARM_ARCH_6K__) || defined(__ARM_ARCH_6Z__) \ | |
| 101 || defined(__ARM_ARCH_6ZK__) || defined(__ARM_ARCH_6T2__) \ | |
| 102 || defined(__ARM_ARCH_6M__) | |
| 103 # define __ARM_ARCH__ 6 | |
| 104 #endif | |
| 105 | |
| 106 #if defined(__ARM_ARCH_7__) || defined(__ARM_ARCH_7A__) \ | |
| 107 || defined(__ARM_ARCH_7R__) || defined(__ARM_ARCH_7M__) | |
| 108 # define __ARM_ARCH__ 7 | |
| 109 #endif | |
| 110 | |
| 111 #ifndef __ARM_ARCH__ | |
| 112 #error Unable to determine architecture. | |
| 113 #endif | |
| 114 | |
| 115 /* How to return from a function call depends on the architecture variant. */ | |
| 116 | |
| 117 #if (__ARM_ARCH__ > 4) || defined(__ARM_ARCH_4T__) | |
| 118 | |
| 119 # define RET bx lr | |
| 120 # define RETc(x) bx##x lr | |
| 121 | |
| 122 /* Special precautions for interworking on armv4t. */ | |
| 123 # if (__ARM_ARCH__ == 4) | |
| 124 | |
| 125 /* Always use bx, not ldr pc. */ | |
| 126 # if (defined(__thumb__) || defined(__THUMB_INTERWORK__)) | |
| 127 # define __INTERWORKING__ | |
| 128 # endif /* __THUMB__ || __THUMB_INTERWORK__ */ | |
| 129 | |
| 130 /* Include thumb stub before arm mode code. */ | |
| 131 # if defined(__thumb__) && !defined(__THUMB_INTERWORK__) | |
| 132 # define __INTERWORKING_STUBS__ | |
| 133 # endif /* __thumb__ && !__THUMB_INTERWORK__ */ | |
| 134 | |
| 135 #endif /* __ARM_ARCH == 4 */ | |
| 136 | |
| 137 #else | |
| 138 | |
| 139 # define RET mov pc, lr | |
| 140 # define RETc(x) mov##x pc, lr | |
| 141 | |
| 142 #endif | |
| 143 | |
| 144 .macro cfi_pop advance, reg, cfa_offset | |
| 145 #ifdef __ELF__ | |
| 146 .pushsection .debug_frame | |
| 147 .byte 0x4 /* DW_CFA_advance_loc4 */ | |
| 148 .4byte \advance | |
| 149 .byte (0xc0 | \reg) /* DW_CFA_restore */ | |
| 150 .byte 0xe /* DW_CFA_def_cfa_offset */ | |
| 151 .uleb128 \cfa_offset | |
| 152 .popsection | |
| 153 #endif | |
| 154 .endm | |
| 155 .macro cfi_push advance, reg, offset, cfa_offset | |
| 156 #ifdef __ELF__ | |
| 157 .pushsection .debug_frame | |
| 158 .byte 0x4 /* DW_CFA_advance_loc4 */ | |
| 159 .4byte \advance | |
| 160 .byte (0x80 | \reg) /* DW_CFA_offset */ | |
| 161 .uleb128 (\offset / -4) | |
| 162 .byte 0xe /* DW_CFA_def_cfa_offset */ | |
| 163 .uleb128 \cfa_offset | |
| 164 .popsection | |
| 165 #endif | |
| 166 .endm | |
| 167 .macro cfi_start start_label, end_label | |
| 168 #ifdef __ELF__ | |
| 169 .pushsection .debug_frame | |
| 170 LSYM(Lstart_frame): | |
| 171 .4byte LSYM(Lend_cie) - LSYM(Lstart_cie) @ Length of CIE | |
| 172 LSYM(Lstart_cie): | |
| 173 .4byte 0xffffffff @ CIE Identifier Tag | |
| 174 .byte 0x1 @ CIE Version | |
| 175 .ascii "\0" @ CIE Augmentation | |
| 176 .uleb128 0x1 @ CIE Code Alignment Factor | |
| 177 .sleb128 -4 @ CIE Data Alignment Factor | |
| 178 .byte 0xe @ CIE RA Column | |
| 179 .byte 0xc @ DW_CFA_def_cfa | |
| 180 .uleb128 0xd | |
| 181 .uleb128 0x0 | |
| 182 | |
| 183 .align 2 | |
| 184 LSYM(Lend_cie): | |
| 185 .4byte LSYM(Lend_fde)-LSYM(Lstart_fde) @ FDE Length | |
| 186 LSYM(Lstart_fde): | |
| 187 .4byte LSYM(Lstart_frame) @ FDE CIE offset | |
| 188 .4byte \start_label @ FDE initial location | |
| 189 .4byte \end_label-\start_label @ FDE address range | |
| 190 .popsection | |
| 191 #endif | |
| 192 .endm | |
| 193 .macro cfi_end end_label | |
| 194 #ifdef __ELF__ | |
| 195 .pushsection .debug_frame | |
| 196 .align 2 | |
| 197 LSYM(Lend_fde): | |
| 198 .popsection | |
| 199 \end_label: | |
| 200 #endif | |
| 201 .endm | |
| 202 | |
| 203 /* Don't pass dirn, it's there just to get token pasting right. */ | |
| 204 | |
| 205 .macro RETLDM regs=, cond=, unwind=, dirn=ia | |
| 206 #if defined (__INTERWORKING__) | |
| 207 .ifc "\regs","" | |
| 208 ldr\cond lr, [sp], #8 | |
| 209 .else | |
| 210 # if defined(__thumb2__) | |
| 211 pop\cond {\regs, lr} | |
| 212 # else | |
| 213 ldm\cond\dirn sp!, {\regs, lr} | |
| 214 # endif | |
| 215 .endif | |
| 216 .ifnc "\unwind", "" | |
| 217 /* Mark LR as restored. */ | |
| 218 97: cfi_pop 97b - \unwind, 0xe, 0x0 | |
| 219 .endif | |
| 220 bx\cond lr | |
| 221 #else | |
| 222 /* Caller is responsible for providing IT instruction. */ | |
| 223 .ifc "\regs","" | |
| 224 ldr\cond pc, [sp], #8 | |
| 225 .else | |
| 226 # if defined(__thumb2__) | |
| 227 pop\cond {\regs, pc} | |
| 228 # else | |
| 229 ldm\cond\dirn sp!, {\regs, pc} | |
| 230 # endif | |
| 231 .endif | |
| 232 #endif | |
| 233 .endm | |
| 234 | |
| 235 /* The Unified assembly syntax allows the same code to be assembled for both | |
| 236 ARM and Thumb-2. However this is only supported by recent gas, so define | |
| 237 a set of macros to allow ARM code on older assemblers. */ | |
| 238 #if defined(__thumb2__) | |
| 239 .macro do_it cond, suffix="" | |
| 240 it\suffix \cond | |
| 241 .endm | |
| 242 .macro shift1 op, arg0, arg1, arg2 | |
| 243 \op \arg0, \arg1, \arg2 | |
| 244 .endm | |
| 245 #define do_push push | |
| 246 #define do_pop pop | |
| 247 #define COND(op1, op2, cond) op1 ## op2 ## cond | |
| 248 /* Perform an arithmetic operation with a variable shift operand. This | |
| 249 requires two instructions and a scratch register on Thumb-2. */ | |
| 250 .macro shiftop name, dest, src1, src2, shiftop, shiftreg, tmp | |
| 251 \shiftop \tmp, \src2, \shiftreg | |
| 252 \name \dest, \src1, \tmp | |
| 253 .endm | |
| 254 #else | |
| 255 .macro do_it cond, suffix="" | |
| 256 .endm | |
| 257 .macro shift1 op, arg0, arg1, arg2 | |
| 258 mov \arg0, \arg1, \op \arg2 | |
| 259 .endm | |
| 260 #define do_push stmfd sp!, | |
| 261 #define do_pop ldmfd sp!, | |
| 262 #define COND(op1, op2, cond) op1 ## cond ## op2 | |
| 263 .macro shiftop name, dest, src1, src2, shiftop, shiftreg, tmp | |
| 264 \name \dest, \src1, \src2, \shiftop \shiftreg | |
| 265 .endm | |
| 266 #endif | |
| 267 | |
|
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268 #ifdef __ARM_EABI__ |
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269 .macro ARM_LDIV0 name signed |
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270 cmp r0, #0 |
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271 .ifc \signed, unsigned |
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272 movne r0, #0xffffffff |
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273 .else |
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274 movgt r0, #0x7fffffff |
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275 movlt r0, #0x80000000 |
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276 .endif |
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277 b SYM (__aeabi_idiv0) __PLT__ |
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278 .endm |
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279 #else |
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280 .macro ARM_LDIV0 name signed |
| 0 | 281 str lr, [sp, #-8]! |
| 282 98: cfi_push 98b - __\name, 0xe, -0x8, 0x8 | |
| 283 bl SYM (__div0) __PLT__ | |
| 284 mov r0, #0 @ About as wrong as it could be. | |
| 285 RETLDM unwind=98b | |
| 286 .endm | |
|
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287 #endif |
| 0 | 288 |
| 289 | |
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290 #ifdef __ARM_EABI__ |
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291 .macro THUMB_LDIV0 name signed |
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292 #if defined(__ARM_ARCH_6M__) |
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293 .ifc \signed, unsigned |
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294 cmp r0, #0 |
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295 beq 1f |
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296 mov r0, #0 |
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297 mvn r0, r0 @ 0xffffffff |
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298 1: |
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299 .else |
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300 cmp r0, #0 |
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301 beq 2f |
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302 blt 3f |
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303 mov r0, #0 |
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304 mvn r0, r0 |
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305 lsr r0, r0, #1 @ 0x7fffffff |
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306 b 2f |
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307 3: mov r0, #0x80 |
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308 lsl r0, r0, #24 @ 0x80000000 |
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309 2: |
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310 .endif |
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311 push {r0, r1, r2} |
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312 ldr r0, 4f |
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313 adr r1, 4f |
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314 add r0, r1 |
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315 str r0, [sp, #8] |
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316 @ We know we are not on armv4t, so pop pc is safe. |
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317 pop {r0, r1, pc} |
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318 .align 2 |
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319 4: |
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320 .word __aeabi_idiv0 - 4b |
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321 #elif defined(__thumb2__) |
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322 .syntax unified |
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323 .ifc \signed, unsigned |
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324 cbz r0, 1f |
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325 mov r0, #0xffffffff |
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326 1: |
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327 .else |
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328 cmp r0, #0 |
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329 do_it gt |
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330 movgt r0, #0x7fffffff |
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331 do_it lt |
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332 movlt r0, #0x80000000 |
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333 .endif |
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334 b.w SYM(__aeabi_idiv0) __PLT__ |
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335 #else |
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336 .align 2 |
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337 bx pc |
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338 nop |
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339 .arm |
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340 cmp r0, #0 |
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341 .ifc \signed, unsigned |
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342 movne r0, #0xffffffff |
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343 .else |
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344 movgt r0, #0x7fffffff |
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345 movlt r0, #0x80000000 |
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346 .endif |
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347 b SYM(__aeabi_idiv0) __PLT__ |
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348 .thumb |
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349 #endif |
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350 .endm |
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351 #else |
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352 .macro THUMB_LDIV0 name signed |
| 0 | 353 push { r1, lr } |
| 354 98: cfi_push 98b - __\name, 0xe, -0x4, 0x8 | |
| 355 bl SYM (__div0) | |
| 356 mov r0, #0 @ About as wrong as it could be. | |
| 357 #if defined (__INTERWORKING__) | |
| 358 pop { r1, r2 } | |
| 359 bx r2 | |
| 360 #else | |
| 361 pop { r1, pc } | |
| 362 #endif | |
| 363 .endm | |
|
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364 #endif |
| 0 | 365 |
| 366 .macro FUNC_END name | |
| 367 SIZE (__\name) | |
| 368 .endm | |
| 369 | |
|
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370 .macro DIV_FUNC_END name signed |
| 0 | 371 cfi_start __\name, LSYM(Lend_div0) |
| 372 LSYM(Ldiv0): | |
| 373 #ifdef __thumb__ | |
|
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374 THUMB_LDIV0 \name \signed |
| 0 | 375 #else |
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376 ARM_LDIV0 \name \signed |
| 0 | 377 #endif |
| 378 cfi_end LSYM(Lend_div0) | |
| 379 FUNC_END \name | |
| 380 .endm | |
| 381 | |
| 382 .macro THUMB_FUNC_START name | |
| 383 .globl SYM (\name) | |
| 384 TYPE (\name) | |
| 385 .thumb_func | |
| 386 SYM (\name): | |
| 387 .endm | |
| 388 | |
| 389 /* Function start macros. Variants for ARM and Thumb. */ | |
| 390 | |
| 391 #ifdef __thumb__ | |
| 392 #define THUMB_FUNC .thumb_func | |
| 393 #define THUMB_CODE .force_thumb | |
| 394 # if defined(__thumb2__) | |
| 395 #define THUMB_SYNTAX .syntax divided | |
| 396 # else | |
| 397 #define THUMB_SYNTAX | |
| 398 # endif | |
| 399 #else | |
| 400 #define THUMB_FUNC | |
| 401 #define THUMB_CODE | |
| 402 #define THUMB_SYNTAX | |
| 403 #endif | |
| 404 | |
| 405 .macro FUNC_START name | |
| 406 .text | |
| 407 .globl SYM (__\name) | |
| 408 TYPE (__\name) | |
| 409 .align 0 | |
| 410 THUMB_CODE | |
| 411 THUMB_FUNC | |
| 412 THUMB_SYNTAX | |
| 413 SYM (__\name): | |
| 414 .endm | |
| 415 | |
| 416 /* Special function that will always be coded in ARM assembly, even if | |
| 417 in Thumb-only compilation. */ | |
| 418 | |
| 419 #if defined(__thumb2__) | |
| 420 | |
| 421 /* For Thumb-2 we build everything in thumb mode. */ | |
| 422 .macro ARM_FUNC_START name | |
| 423 FUNC_START \name | |
| 424 .syntax unified | |
| 425 .endm | |
| 426 #define EQUIV .thumb_set | |
| 427 .macro ARM_CALL name | |
| 428 bl __\name | |
| 429 .endm | |
| 430 | |
| 431 #elif defined(__INTERWORKING_STUBS__) | |
| 432 | |
| 433 .macro ARM_FUNC_START name | |
| 434 FUNC_START \name | |
| 435 bx pc | |
| 436 nop | |
| 437 .arm | |
| 438 /* A hook to tell gdb that we've switched to ARM mode. Also used to call | |
| 439 directly from other local arm routines. */ | |
| 440 _L__\name: | |
| 441 .endm | |
| 442 #define EQUIV .thumb_set | |
| 443 /* Branch directly to a function declared with ARM_FUNC_START. | |
| 444 Must be called in arm mode. */ | |
| 445 .macro ARM_CALL name | |
| 446 bl _L__\name | |
| 447 .endm | |
| 448 | |
| 449 #else /* !(__INTERWORKING_STUBS__ || __thumb2__) */ | |
| 450 | |
| 451 #ifdef __ARM_ARCH_6M__ | |
| 452 #define EQUIV .thumb_set | |
| 453 #else | |
| 454 .macro ARM_FUNC_START name | |
| 455 .text | |
| 456 .globl SYM (__\name) | |
| 457 TYPE (__\name) | |
| 458 .align 0 | |
| 459 .arm | |
| 460 SYM (__\name): | |
| 461 .endm | |
| 462 #define EQUIV .set | |
| 463 .macro ARM_CALL name | |
| 464 bl __\name | |
| 465 .endm | |
| 466 #endif | |
| 467 | |
| 468 #endif | |
| 469 | |
| 470 .macro FUNC_ALIAS new old | |
| 471 .globl SYM (__\new) | |
| 472 #if defined (__thumb__) | |
| 473 .thumb_set SYM (__\new), SYM (__\old) | |
| 474 #else | |
| 475 .set SYM (__\new), SYM (__\old) | |
| 476 #endif | |
| 477 .endm | |
| 478 | |
| 479 #ifndef __ARM_ARCH_6M__ | |
| 480 .macro ARM_FUNC_ALIAS new old | |
| 481 .globl SYM (__\new) | |
| 482 EQUIV SYM (__\new), SYM (__\old) | |
| 483 #if defined(__INTERWORKING_STUBS__) | |
| 484 .set SYM (_L__\new), SYM (_L__\old) | |
| 485 #endif | |
| 486 .endm | |
| 487 #endif | |
| 488 | |
| 489 #ifdef __ARMEB__ | |
| 490 #define xxh r0 | |
| 491 #define xxl r1 | |
| 492 #define yyh r2 | |
| 493 #define yyl r3 | |
| 494 #else | |
| 495 #define xxh r1 | |
| 496 #define xxl r0 | |
| 497 #define yyh r3 | |
| 498 #define yyl r2 | |
| 499 #endif | |
| 500 | |
|
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501 #ifdef __ARM_EABI__ |
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502 .macro WEAK name |
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503 .weak SYM (__\name) |
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504 .endm |
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505 #endif |
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506 |
| 0 | 507 #ifdef __thumb__ |
| 508 /* Register aliases. */ | |
| 509 | |
| 510 work .req r4 @ XXXX is this safe ? | |
| 511 dividend .req r0 | |
| 512 divisor .req r1 | |
| 513 overdone .req r2 | |
| 514 result .req r2 | |
| 515 curbit .req r3 | |
| 516 #endif | |
| 517 #if 0 | |
| 518 ip .req r12 | |
| 519 sp .req r13 | |
| 520 lr .req r14 | |
| 521 pc .req r15 | |
| 522 #endif | |
| 523 | |
| 524 /* ------------------------------------------------------------------------ */ | |
| 525 /* Bodies of the division and modulo routines. */ | |
| 526 /* ------------------------------------------------------------------------ */ | |
| 527 .macro ARM_DIV_BODY dividend, divisor, result, curbit | |
| 528 | |
| 529 #if __ARM_ARCH__ >= 5 && ! defined (__OPTIMIZE_SIZE__) | |
| 530 | |
|
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531 #if defined (__thumb2__) |
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532 clz \curbit, \dividend |
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533 clz \result, \divisor |
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534 sub \curbit, \result, \curbit |
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535 rsb \curbit, \curbit, #31 |
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536 adr \result, 1f |
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537 add \curbit, \result, \curbit, lsl #4 |
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538 mov \result, #0 |
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539 mov pc, \curbit |
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540 .p2align 3 |
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541 1: |
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542 .set shift, 32 |
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543 .rept 32 |
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544 .set shift, shift - 1 |
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545 cmp.w \dividend, \divisor, lsl #shift |
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546 nop.n |
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547 adc.w \result, \result, \result |
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548 it cs |
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549 subcs.w \dividend, \dividend, \divisor, lsl #shift |
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550 .endr |
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551 #else |
| 0 | 552 clz \curbit, \dividend |
| 553 clz \result, \divisor | |
| 554 sub \curbit, \result, \curbit | |
| 555 rsbs \curbit, \curbit, #31 | |
| 556 addne \curbit, \curbit, \curbit, lsl #1 | |
| 557 mov \result, #0 | |
| 558 addne pc, pc, \curbit, lsl #2 | |
| 559 nop | |
| 560 .set shift, 32 | |
| 561 .rept 32 | |
| 562 .set shift, shift - 1 | |
| 563 cmp \dividend, \divisor, lsl #shift | |
| 564 adc \result, \result, \result | |
| 565 subcs \dividend, \dividend, \divisor, lsl #shift | |
| 566 .endr | |
|
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567 #endif |
| 0 | 568 |
| 569 #else /* __ARM_ARCH__ < 5 || defined (__OPTIMIZE_SIZE__) */ | |
| 570 #if __ARM_ARCH__ >= 5 | |
| 571 | |
| 572 clz \curbit, \divisor | |
| 573 clz \result, \dividend | |
| 574 sub \result, \curbit, \result | |
| 575 mov \curbit, #1 | |
| 576 mov \divisor, \divisor, lsl \result | |
| 577 mov \curbit, \curbit, lsl \result | |
| 578 mov \result, #0 | |
| 579 | |
| 580 #else /* __ARM_ARCH__ < 5 */ | |
| 581 | |
| 582 @ Initially shift the divisor left 3 bits if possible, | |
| 583 @ set curbit accordingly. This allows for curbit to be located | |
| 584 @ at the left end of each 4-bit nibbles in the division loop | |
| 585 @ to save one loop in most cases. | |
| 586 tst \divisor, #0xe0000000 | |
| 587 moveq \divisor, \divisor, lsl #3 | |
| 588 moveq \curbit, #8 | |
| 589 movne \curbit, #1 | |
| 590 | |
| 591 @ Unless the divisor is very big, shift it up in multiples of | |
| 592 @ four bits, since this is the amount of unwinding in the main | |
| 593 @ division loop. Continue shifting until the divisor is | |
| 594 @ larger than the dividend. | |
| 595 1: cmp \divisor, #0x10000000 | |
| 596 cmplo \divisor, \dividend | |
| 597 movlo \divisor, \divisor, lsl #4 | |
| 598 movlo \curbit, \curbit, lsl #4 | |
| 599 blo 1b | |
| 600 | |
| 601 @ For very big divisors, we must shift it a bit at a time, or | |
| 602 @ we will be in danger of overflowing. | |
| 603 1: cmp \divisor, #0x80000000 | |
| 604 cmplo \divisor, \dividend | |
| 605 movlo \divisor, \divisor, lsl #1 | |
| 606 movlo \curbit, \curbit, lsl #1 | |
| 607 blo 1b | |
| 608 | |
| 609 mov \result, #0 | |
| 610 | |
| 611 #endif /* __ARM_ARCH__ < 5 */ | |
| 612 | |
| 613 @ Division loop | |
| 614 1: cmp \dividend, \divisor | |
|
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615 do_it hs, t |
| 0 | 616 subhs \dividend, \dividend, \divisor |
| 617 orrhs \result, \result, \curbit | |
| 618 cmp \dividend, \divisor, lsr #1 | |
|
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619 do_it hs, t |
| 0 | 620 subhs \dividend, \dividend, \divisor, lsr #1 |
| 621 orrhs \result, \result, \curbit, lsr #1 | |
| 622 cmp \dividend, \divisor, lsr #2 | |
|
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623 do_it hs, t |
| 0 | 624 subhs \dividend, \dividend, \divisor, lsr #2 |
| 625 orrhs \result, \result, \curbit, lsr #2 | |
| 626 cmp \dividend, \divisor, lsr #3 | |
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627 do_it hs, t |
| 0 | 628 subhs \dividend, \dividend, \divisor, lsr #3 |
| 629 orrhs \result, \result, \curbit, lsr #3 | |
| 630 cmp \dividend, #0 @ Early termination? | |
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631 do_it hs, t |
| 0 | 632 movnes \curbit, \curbit, lsr #4 @ No, any more bits to do? |
| 633 movne \divisor, \divisor, lsr #4 | |
| 634 bne 1b | |
| 635 | |
| 636 #endif /* __ARM_ARCH__ < 5 || defined (__OPTIMIZE_SIZE__) */ | |
| 637 | |
| 638 .endm | |
| 639 /* ------------------------------------------------------------------------ */ | |
| 640 .macro ARM_DIV2_ORDER divisor, order | |
| 641 | |
| 642 #if __ARM_ARCH__ >= 5 | |
| 643 | |
| 644 clz \order, \divisor | |
| 645 rsb \order, \order, #31 | |
| 646 | |
| 647 #else | |
| 648 | |
| 649 cmp \divisor, #(1 << 16) | |
| 650 movhs \divisor, \divisor, lsr #16 | |
| 651 movhs \order, #16 | |
| 652 movlo \order, #0 | |
| 653 | |
| 654 cmp \divisor, #(1 << 8) | |
| 655 movhs \divisor, \divisor, lsr #8 | |
| 656 addhs \order, \order, #8 | |
| 657 | |
| 658 cmp \divisor, #(1 << 4) | |
| 659 movhs \divisor, \divisor, lsr #4 | |
| 660 addhs \order, \order, #4 | |
| 661 | |
| 662 cmp \divisor, #(1 << 2) | |
| 663 addhi \order, \order, #3 | |
| 664 addls \order, \order, \divisor, lsr #1 | |
| 665 | |
| 666 #endif | |
| 667 | |
| 668 .endm | |
| 669 /* ------------------------------------------------------------------------ */ | |
| 670 .macro ARM_MOD_BODY dividend, divisor, order, spare | |
| 671 | |
| 672 #if __ARM_ARCH__ >= 5 && ! defined (__OPTIMIZE_SIZE__) | |
| 673 | |
| 674 clz \order, \divisor | |
| 675 clz \spare, \dividend | |
| 676 sub \order, \order, \spare | |
| 677 rsbs \order, \order, #31 | |
| 678 addne pc, pc, \order, lsl #3 | |
| 679 nop | |
| 680 .set shift, 32 | |
| 681 .rept 32 | |
| 682 .set shift, shift - 1 | |
| 683 cmp \dividend, \divisor, lsl #shift | |
| 684 subcs \dividend, \dividend, \divisor, lsl #shift | |
| 685 .endr | |
| 686 | |
| 687 #else /* __ARM_ARCH__ < 5 || defined (__OPTIMIZE_SIZE__) */ | |
| 688 #if __ARM_ARCH__ >= 5 | |
| 689 | |
| 690 clz \order, \divisor | |
| 691 clz \spare, \dividend | |
| 692 sub \order, \order, \spare | |
| 693 mov \divisor, \divisor, lsl \order | |
| 694 | |
| 695 #else /* __ARM_ARCH__ < 5 */ | |
| 696 | |
| 697 mov \order, #0 | |
| 698 | |
| 699 @ Unless the divisor is very big, shift it up in multiples of | |
| 700 @ four bits, since this is the amount of unwinding in the main | |
| 701 @ division loop. Continue shifting until the divisor is | |
| 702 @ larger than the dividend. | |
| 703 1: cmp \divisor, #0x10000000 | |
| 704 cmplo \divisor, \dividend | |
| 705 movlo \divisor, \divisor, lsl #4 | |
| 706 addlo \order, \order, #4 | |
| 707 blo 1b | |
| 708 | |
| 709 @ For very big divisors, we must shift it a bit at a time, or | |
| 710 @ we will be in danger of overflowing. | |
| 711 1: cmp \divisor, #0x80000000 | |
| 712 cmplo \divisor, \dividend | |
| 713 movlo \divisor, \divisor, lsl #1 | |
| 714 addlo \order, \order, #1 | |
| 715 blo 1b | |
| 716 | |
| 717 #endif /* __ARM_ARCH__ < 5 */ | |
| 718 | |
| 719 @ Perform all needed substractions to keep only the reminder. | |
| 720 @ Do comparisons in batch of 4 first. | |
| 721 subs \order, \order, #3 @ yes, 3 is intended here | |
| 722 blt 2f | |
| 723 | |
| 724 1: cmp \dividend, \divisor | |
| 725 subhs \dividend, \dividend, \divisor | |
| 726 cmp \dividend, \divisor, lsr #1 | |
| 727 subhs \dividend, \dividend, \divisor, lsr #1 | |
| 728 cmp \dividend, \divisor, lsr #2 | |
| 729 subhs \dividend, \dividend, \divisor, lsr #2 | |
| 730 cmp \dividend, \divisor, lsr #3 | |
| 731 subhs \dividend, \dividend, \divisor, lsr #3 | |
| 732 cmp \dividend, #1 | |
| 733 mov \divisor, \divisor, lsr #4 | |
| 734 subges \order, \order, #4 | |
| 735 bge 1b | |
| 736 | |
| 737 tst \order, #3 | |
| 738 teqne \dividend, #0 | |
| 739 beq 5f | |
| 740 | |
| 741 @ Either 1, 2 or 3 comparison/substractions are left. | |
| 742 2: cmn \order, #2 | |
| 743 blt 4f | |
| 744 beq 3f | |
| 745 cmp \dividend, \divisor | |
| 746 subhs \dividend, \dividend, \divisor | |
| 747 mov \divisor, \divisor, lsr #1 | |
| 748 3: cmp \dividend, \divisor | |
| 749 subhs \dividend, \dividend, \divisor | |
| 750 mov \divisor, \divisor, lsr #1 | |
| 751 4: cmp \dividend, \divisor | |
| 752 subhs \dividend, \dividend, \divisor | |
| 753 5: | |
| 754 | |
| 755 #endif /* __ARM_ARCH__ < 5 || defined (__OPTIMIZE_SIZE__) */ | |
| 756 | |
| 757 .endm | |
| 758 /* ------------------------------------------------------------------------ */ | |
| 759 .macro THUMB_DIV_MOD_BODY modulo | |
| 760 @ Load the constant 0x10000000 into our work register. | |
| 761 mov work, #1 | |
| 762 lsl work, #28 | |
| 763 LSYM(Loop1): | |
| 764 @ Unless the divisor is very big, shift it up in multiples of | |
| 765 @ four bits, since this is the amount of unwinding in the main | |
| 766 @ division loop. Continue shifting until the divisor is | |
| 767 @ larger than the dividend. | |
| 768 cmp divisor, work | |
| 769 bhs LSYM(Lbignum) | |
| 770 cmp divisor, dividend | |
| 771 bhs LSYM(Lbignum) | |
| 772 lsl divisor, #4 | |
| 773 lsl curbit, #4 | |
| 774 b LSYM(Loop1) | |
| 775 LSYM(Lbignum): | |
| 776 @ Set work to 0x80000000 | |
| 777 lsl work, #3 | |
| 778 LSYM(Loop2): | |
| 779 @ For very big divisors, we must shift it a bit at a time, or | |
| 780 @ we will be in danger of overflowing. | |
| 781 cmp divisor, work | |
| 782 bhs LSYM(Loop3) | |
| 783 cmp divisor, dividend | |
| 784 bhs LSYM(Loop3) | |
| 785 lsl divisor, #1 | |
| 786 lsl curbit, #1 | |
| 787 b LSYM(Loop2) | |
| 788 LSYM(Loop3): | |
| 789 @ Test for possible subtractions ... | |
| 790 .if \modulo | |
| 791 @ ... On the final pass, this may subtract too much from the dividend, | |
| 792 @ so keep track of which subtractions are done, we can fix them up | |
| 793 @ afterwards. | |
| 794 mov overdone, #0 | |
| 795 cmp dividend, divisor | |
| 796 blo LSYM(Lover1) | |
| 797 sub dividend, dividend, divisor | |
| 798 LSYM(Lover1): | |
| 799 lsr work, divisor, #1 | |
| 800 cmp dividend, work | |
| 801 blo LSYM(Lover2) | |
| 802 sub dividend, dividend, work | |
| 803 mov ip, curbit | |
| 804 mov work, #1 | |
| 805 ror curbit, work | |
| 806 orr overdone, curbit | |
| 807 mov curbit, ip | |
| 808 LSYM(Lover2): | |
| 809 lsr work, divisor, #2 | |
| 810 cmp dividend, work | |
| 811 blo LSYM(Lover3) | |
| 812 sub dividend, dividend, work | |
| 813 mov ip, curbit | |
| 814 mov work, #2 | |
| 815 ror curbit, work | |
| 816 orr overdone, curbit | |
| 817 mov curbit, ip | |
| 818 LSYM(Lover3): | |
| 819 lsr work, divisor, #3 | |
| 820 cmp dividend, work | |
| 821 blo LSYM(Lover4) | |
| 822 sub dividend, dividend, work | |
| 823 mov ip, curbit | |
| 824 mov work, #3 | |
| 825 ror curbit, work | |
| 826 orr overdone, curbit | |
| 827 mov curbit, ip | |
| 828 LSYM(Lover4): | |
| 829 mov ip, curbit | |
| 830 .else | |
| 831 @ ... and note which bits are done in the result. On the final pass, | |
| 832 @ this may subtract too much from the dividend, but the result will be ok, | |
| 833 @ since the "bit" will have been shifted out at the bottom. | |
| 834 cmp dividend, divisor | |
| 835 blo LSYM(Lover1) | |
| 836 sub dividend, dividend, divisor | |
| 837 orr result, result, curbit | |
| 838 LSYM(Lover1): | |
| 839 lsr work, divisor, #1 | |
| 840 cmp dividend, work | |
| 841 blo LSYM(Lover2) | |
| 842 sub dividend, dividend, work | |
| 843 lsr work, curbit, #1 | |
| 844 orr result, work | |
| 845 LSYM(Lover2): | |
| 846 lsr work, divisor, #2 | |
| 847 cmp dividend, work | |
| 848 blo LSYM(Lover3) | |
| 849 sub dividend, dividend, work | |
| 850 lsr work, curbit, #2 | |
| 851 orr result, work | |
| 852 LSYM(Lover3): | |
| 853 lsr work, divisor, #3 | |
| 854 cmp dividend, work | |
| 855 blo LSYM(Lover4) | |
| 856 sub dividend, dividend, work | |
| 857 lsr work, curbit, #3 | |
| 858 orr result, work | |
| 859 LSYM(Lover4): | |
| 860 .endif | |
| 861 | |
| 862 cmp dividend, #0 @ Early termination? | |
| 863 beq LSYM(Lover5) | |
| 864 lsr curbit, #4 @ No, any more bits to do? | |
| 865 beq LSYM(Lover5) | |
| 866 lsr divisor, #4 | |
| 867 b LSYM(Loop3) | |
| 868 LSYM(Lover5): | |
| 869 .if \modulo | |
| 870 @ Any subtractions that we should not have done will be recorded in | |
| 871 @ the top three bits of "overdone". Exactly which were not needed | |
| 872 @ are governed by the position of the bit, stored in ip. | |
| 873 mov work, #0xe | |
| 874 lsl work, #28 | |
| 875 and overdone, work | |
| 876 beq LSYM(Lgot_result) | |
| 877 | |
| 878 @ If we terminated early, because dividend became zero, then the | |
| 879 @ bit in ip will not be in the bottom nibble, and we should not | |
| 880 @ perform the additions below. We must test for this though | |
| 881 @ (rather relying upon the TSTs to prevent the additions) since | |
| 882 @ the bit in ip could be in the top two bits which might then match | |
| 883 @ with one of the smaller RORs. | |
| 884 mov curbit, ip | |
| 885 mov work, #0x7 | |
| 886 tst curbit, work | |
| 887 beq LSYM(Lgot_result) | |
| 888 | |
| 889 mov curbit, ip | |
| 890 mov work, #3 | |
| 891 ror curbit, work | |
| 892 tst overdone, curbit | |
| 893 beq LSYM(Lover6) | |
| 894 lsr work, divisor, #3 | |
| 895 add dividend, work | |
| 896 LSYM(Lover6): | |
| 897 mov curbit, ip | |
| 898 mov work, #2 | |
| 899 ror curbit, work | |
| 900 tst overdone, curbit | |
| 901 beq LSYM(Lover7) | |
| 902 lsr work, divisor, #2 | |
| 903 add dividend, work | |
| 904 LSYM(Lover7): | |
| 905 mov curbit, ip | |
| 906 mov work, #1 | |
| 907 ror curbit, work | |
| 908 tst overdone, curbit | |
| 909 beq LSYM(Lgot_result) | |
| 910 lsr work, divisor, #1 | |
| 911 add dividend, work | |
| 912 .endif | |
| 913 LSYM(Lgot_result): | |
| 914 .endm | |
| 915 /* ------------------------------------------------------------------------ */ | |
| 916 /* Start of the Real Functions */ | |
| 917 /* ------------------------------------------------------------------------ */ | |
| 918 #ifdef L_udivsi3 | |
| 919 | |
|
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920 #if defined(__ARM_ARCH_6M__) |
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921 |
| 0 | 922 FUNC_START udivsi3 |
| 923 FUNC_ALIAS aeabi_uidiv udivsi3 | |
| 924 | |
| 925 cmp divisor, #0 | |
| 926 beq LSYM(Ldiv0) | |
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927 LSYM(udivsi3_skip_div0_test): |
| 0 | 928 mov curbit, #1 |
| 929 mov result, #0 | |
| 930 | |
| 931 push { work } | |
| 932 cmp dividend, divisor | |
| 933 blo LSYM(Lgot_result) | |
| 934 | |
| 935 THUMB_DIV_MOD_BODY 0 | |
| 936 | |
| 937 mov r0, result | |
| 938 pop { work } | |
| 939 RET | |
| 940 | |
|
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941 #else /* ARM version/Thumb-2. */ |
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942 |
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943 ARM_FUNC_START udivsi3 |
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944 ARM_FUNC_ALIAS aeabi_uidiv udivsi3 |
| 0 | 945 |
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946 /* Note: if called via udivsi3_skip_div0_test, this will unnecessarily |
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947 check for division-by-zero a second time. */ |
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948 LSYM(udivsi3_skip_div0_test): |
| 0 | 949 subs r2, r1, #1 |
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950 do_it eq |
| 0 | 951 RETc(eq) |
| 952 bcc LSYM(Ldiv0) | |
| 953 cmp r0, r1 | |
| 954 bls 11f | |
| 955 tst r1, r2 | |
| 956 beq 12f | |
| 957 | |
| 958 ARM_DIV_BODY r0, r1, r2, r3 | |
| 959 | |
| 960 mov r0, r2 | |
| 961 RET | |
| 962 | |
|
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963 11: do_it eq, e |
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964 moveq r0, #1 |
| 0 | 965 movne r0, #0 |
| 966 RET | |
| 967 | |
| 968 12: ARM_DIV2_ORDER r1, r2 | |
| 969 | |
| 970 mov r0, r0, lsr r2 | |
| 971 RET | |
| 972 | |
| 973 #endif /* ARM version */ | |
| 974 | |
|
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975 DIV_FUNC_END udivsi3 unsigned |
| 0 | 976 |
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977 #if defined(__ARM_ARCH_6M__) |
| 0 | 978 FUNC_START aeabi_uidivmod |
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979 cmp r1, #0 |
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980 beq LSYM(Ldiv0) |
| 0 | 981 push {r0, r1, lr} |
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982 bl LSYM(udivsi3_skip_div0_test) |
| 0 | 983 POP {r1, r2, r3} |
| 984 mul r2, r0 | |
| 985 sub r1, r1, r2 | |
| 986 bx r3 | |
| 987 #else | |
|
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988 ARM_FUNC_START aeabi_uidivmod |
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989 cmp r1, #0 |
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990 beq LSYM(Ldiv0) |
| 0 | 991 stmfd sp!, { r0, r1, lr } |
|
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992 bl LSYM(udivsi3_skip_div0_test) |
| 0 | 993 ldmfd sp!, { r1, r2, lr } |
| 994 mul r3, r2, r0 | |
| 995 sub r1, r1, r3 | |
| 996 RET | |
| 997 #endif | |
| 998 FUNC_END aeabi_uidivmod | |
| 999 | |
| 1000 #endif /* L_udivsi3 */ | |
| 1001 /* ------------------------------------------------------------------------ */ | |
| 1002 #ifdef L_umodsi3 | |
| 1003 | |
| 1004 FUNC_START umodsi3 | |
| 1005 | |
| 1006 #ifdef __thumb__ | |
| 1007 | |
| 1008 cmp divisor, #0 | |
| 1009 beq LSYM(Ldiv0) | |
| 1010 mov curbit, #1 | |
| 1011 cmp dividend, divisor | |
| 1012 bhs LSYM(Lover10) | |
| 1013 RET | |
| 1014 | |
| 1015 LSYM(Lover10): | |
| 1016 push { work } | |
| 1017 | |
| 1018 THUMB_DIV_MOD_BODY 1 | |
| 1019 | |
| 1020 pop { work } | |
| 1021 RET | |
| 1022 | |
| 1023 #else /* ARM version. */ | |
| 1024 | |
| 1025 subs r2, r1, #1 @ compare divisor with 1 | |
| 1026 bcc LSYM(Ldiv0) | |
| 1027 cmpne r0, r1 @ compare dividend with divisor | |
| 1028 moveq r0, #0 | |
| 1029 tsthi r1, r2 @ see if divisor is power of 2 | |
| 1030 andeq r0, r0, r2 | |
| 1031 RETc(ls) | |
| 1032 | |
| 1033 ARM_MOD_BODY r0, r1, r2, r3 | |
| 1034 | |
| 1035 RET | |
| 1036 | |
| 1037 #endif /* ARM version. */ | |
| 1038 | |
|
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1039 DIV_FUNC_END umodsi3 unsigned |
| 0 | 1040 |
| 1041 #endif /* L_umodsi3 */ | |
| 1042 /* ------------------------------------------------------------------------ */ | |
| 1043 #ifdef L_divsi3 | |
| 1044 | |
|
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1045 #if defined(__ARM_ARCH_6M__) |
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1046 |
| 0 | 1047 FUNC_START divsi3 |
| 1048 FUNC_ALIAS aeabi_idiv divsi3 | |
| 1049 | |
| 1050 cmp divisor, #0 | |
| 1051 beq LSYM(Ldiv0) | |
|
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1052 LSYM(divsi3_skip_div0_test): |
| 0 | 1053 push { work } |
| 1054 mov work, dividend | |
| 1055 eor work, divisor @ Save the sign of the result. | |
| 1056 mov ip, work | |
| 1057 mov curbit, #1 | |
| 1058 mov result, #0 | |
| 1059 cmp divisor, #0 | |
| 1060 bpl LSYM(Lover10) | |
| 1061 neg divisor, divisor @ Loops below use unsigned. | |
| 1062 LSYM(Lover10): | |
| 1063 cmp dividend, #0 | |
| 1064 bpl LSYM(Lover11) | |
| 1065 neg dividend, dividend | |
| 1066 LSYM(Lover11): | |
| 1067 cmp dividend, divisor | |
| 1068 blo LSYM(Lgot_result) | |
| 1069 | |
| 1070 THUMB_DIV_MOD_BODY 0 | |
| 1071 | |
| 1072 mov r0, result | |
| 1073 mov work, ip | |
| 1074 cmp work, #0 | |
| 1075 bpl LSYM(Lover12) | |
| 1076 neg r0, r0 | |
| 1077 LSYM(Lover12): | |
| 1078 pop { work } | |
| 1079 RET | |
| 1080 | |
|
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1081 #else /* ARM/Thumb-2 version. */ |
| 0 | 1082 |
|
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1083 ARM_FUNC_START divsi3 |
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1084 ARM_FUNC_ALIAS aeabi_idiv divsi3 |
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1085 |
| 0 | 1086 cmp r1, #0 |
|
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1087 beq LSYM(Ldiv0) |
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1088 LSYM(divsi3_skip_div0_test): |
| 0 | 1089 eor ip, r0, r1 @ save the sign of the result. |
|
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1090 do_it mi |
| 0 | 1091 rsbmi r1, r1, #0 @ loops below use unsigned. |
| 1092 subs r2, r1, #1 @ division by 1 or -1 ? | |
| 1093 beq 10f | |
| 1094 movs r3, r0 | |
|
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1095 do_it mi |
| 0 | 1096 rsbmi r3, r0, #0 @ positive dividend value |
| 1097 cmp r3, r1 | |
| 1098 bls 11f | |
| 1099 tst r1, r2 @ divisor is power of 2 ? | |
| 1100 beq 12f | |
| 1101 | |
| 1102 ARM_DIV_BODY r3, r1, r0, r2 | |
| 1103 | |
| 1104 cmp ip, #0 | |
|
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1105 do_it mi |
| 0 | 1106 rsbmi r0, r0, #0 |
| 1107 RET | |
| 1108 | |
| 1109 10: teq ip, r0 @ same sign ? | |
|
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1110 do_it mi |
| 0 | 1111 rsbmi r0, r0, #0 |
| 1112 RET | |
| 1113 | |
|
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1114 11: do_it lo |
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1115 movlo r0, #0 |
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1116 do_it eq,t |
| 0 | 1117 moveq r0, ip, asr #31 |
| 1118 orreq r0, r0, #1 | |
| 1119 RET | |
| 1120 | |
| 1121 12: ARM_DIV2_ORDER r1, r2 | |
| 1122 | |
| 1123 cmp ip, #0 | |
| 1124 mov r0, r3, lsr r2 | |
|
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1125 do_it mi |
| 0 | 1126 rsbmi r0, r0, #0 |
| 1127 RET | |
| 1128 | |
| 1129 #endif /* ARM version */ | |
| 1130 | |
|
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1131 DIV_FUNC_END divsi3 signed |
| 0 | 1132 |
|
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1133 #if defined(__ARM_ARCH_6M__) |
| 0 | 1134 FUNC_START aeabi_idivmod |
|
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1135 cmp r1, #0 |
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1136 beq LSYM(Ldiv0) |
| 0 | 1137 push {r0, r1, lr} |
|
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1138 bl LSYM(divsi3_skip_div0_test) |
| 0 | 1139 POP {r1, r2, r3} |
| 1140 mul r2, r0 | |
| 1141 sub r1, r1, r2 | |
| 1142 bx r3 | |
| 1143 #else | |
|
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1144 ARM_FUNC_START aeabi_idivmod |
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1145 cmp r1, #0 |
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1146 beq LSYM(Ldiv0) |
| 0 | 1147 stmfd sp!, { r0, r1, lr } |
|
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1148 bl LSYM(divsi3_skip_div0_test) |
| 0 | 1149 ldmfd sp!, { r1, r2, lr } |
| 1150 mul r3, r2, r0 | |
| 1151 sub r1, r1, r3 | |
| 1152 RET | |
| 1153 #endif | |
| 1154 FUNC_END aeabi_idivmod | |
| 1155 | |
| 1156 #endif /* L_divsi3 */ | |
| 1157 /* ------------------------------------------------------------------------ */ | |
| 1158 #ifdef L_modsi3 | |
| 1159 | |
| 1160 FUNC_START modsi3 | |
| 1161 | |
| 1162 #ifdef __thumb__ | |
| 1163 | |
| 1164 mov curbit, #1 | |
| 1165 cmp divisor, #0 | |
| 1166 beq LSYM(Ldiv0) | |
| 1167 bpl LSYM(Lover10) | |
| 1168 neg divisor, divisor @ Loops below use unsigned. | |
| 1169 LSYM(Lover10): | |
| 1170 push { work } | |
| 1171 @ Need to save the sign of the dividend, unfortunately, we need | |
| 1172 @ work later on. Must do this after saving the original value of | |
| 1173 @ the work register, because we will pop this value off first. | |
| 1174 push { dividend } | |
| 1175 cmp dividend, #0 | |
| 1176 bpl LSYM(Lover11) | |
| 1177 neg dividend, dividend | |
| 1178 LSYM(Lover11): | |
| 1179 cmp dividend, divisor | |
| 1180 blo LSYM(Lgot_result) | |
| 1181 | |
| 1182 THUMB_DIV_MOD_BODY 1 | |
| 1183 | |
| 1184 pop { work } | |
| 1185 cmp work, #0 | |
| 1186 bpl LSYM(Lover12) | |
| 1187 neg dividend, dividend | |
| 1188 LSYM(Lover12): | |
| 1189 pop { work } | |
| 1190 RET | |
| 1191 | |
| 1192 #else /* ARM version. */ | |
| 1193 | |
| 1194 cmp r1, #0 | |
| 1195 beq LSYM(Ldiv0) | |
| 1196 rsbmi r1, r1, #0 @ loops below use unsigned. | |
| 1197 movs ip, r0 @ preserve sign of dividend | |
| 1198 rsbmi r0, r0, #0 @ if negative make positive | |
| 1199 subs r2, r1, #1 @ compare divisor with 1 | |
| 1200 cmpne r0, r1 @ compare dividend with divisor | |
| 1201 moveq r0, #0 | |
| 1202 tsthi r1, r2 @ see if divisor is power of 2 | |
| 1203 andeq r0, r0, r2 | |
| 1204 bls 10f | |
| 1205 | |
| 1206 ARM_MOD_BODY r0, r1, r2, r3 | |
| 1207 | |
| 1208 10: cmp ip, #0 | |
| 1209 rsbmi r0, r0, #0 | |
| 1210 RET | |
| 1211 | |
| 1212 #endif /* ARM version */ | |
| 1213 | |
|
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|
1214 DIV_FUNC_END modsi3 signed |
| 0 | 1215 |
| 1216 #endif /* L_modsi3 */ | |
| 1217 /* ------------------------------------------------------------------------ */ | |
| 1218 #ifdef L_dvmd_tls | |
| 1219 | |
|
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|
1220 #ifdef __ARM_EABI__ |
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1221 WEAK aeabi_idiv0 |
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1222 WEAK aeabi_ldiv0 |
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1223 FUNC_START aeabi_idiv0 |
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1224 FUNC_START aeabi_ldiv0 |
| 0 | 1225 RET |
| 1226 FUNC_END aeabi_ldiv0 | |
| 1227 FUNC_END aeabi_idiv0 | |
|
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|
1228 #else |
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|
1229 FUNC_START div0 |
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1230 RET |
| 0 | 1231 FUNC_END div0 |
|
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|
1232 #endif |
| 0 | 1233 |
| 1234 #endif /* L_divmodsi_tools */ | |
| 1235 /* ------------------------------------------------------------------------ */ | |
| 1236 #ifdef L_dvmd_lnx | |
| 1237 @ GNU/Linux division-by zero handler. Used in place of L_dvmd_tls | |
| 1238 | |
| 1239 /* Constant taken from <asm/signal.h>. */ | |
| 1240 #define SIGFPE 8 | |
| 1241 | |
|
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|
1242 #ifdef __ARM_EABI__ |
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|
1243 WEAK aeabi_idiv0 |
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|
1244 WEAK aeabi_ldiv0 |
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|
1245 ARM_FUNC_START aeabi_idiv0 |
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|
1246 ARM_FUNC_START aeabi_ldiv0 |
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|
1247 #else |
| 0 | 1248 ARM_FUNC_START div0 |
|
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|
1249 #endif |
| 0 | 1250 |
| 1251 do_push {r1, lr} | |
| 1252 mov r0, #SIGFPE | |
| 1253 bl SYM(raise) __PLT__ | |
| 1254 RETLDM r1 | |
| 1255 | |
|
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|
1256 #ifdef __ARM_EABI__ |
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1257 FUNC_END aeabi_ldiv0 |
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|
1258 FUNC_END aeabi_idiv0 |
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1259 #else |
| 0 | 1260 FUNC_END div0 |
|
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|
1261 #endif |
| 0 | 1262 |
| 1263 #endif /* L_dvmd_lnx */ | |
|
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1264 #ifdef L_clear_cache |
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1265 #if defined __ARM_EABI__ && defined __linux__ |
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1266 @ EABI GNU/Linux call to cacheflush syscall. |
|
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1267 ARM_FUNC_START clear_cache |
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1268 do_push {r7} |
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1269 #if __ARM_ARCH__ >= 7 || defined(__ARM_ARCH_6T2__) |
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1270 movw r7, #2 |
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1271 movt r7, #0xf |
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1272 #else |
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1273 mov r7, #0xf0000 |
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1274 add r7, r7, #2 |
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1275 #endif |
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1276 mov r2, #0 |
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|
1277 swi 0 |
|
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1278 do_pop {r7} |
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1279 RET |
|
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1280 FUNC_END clear_cache |
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1281 #else |
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1282 #error "This is only for ARM EABI GNU/Linux" |
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1283 #endif |
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|
1284 #endif /* L_clear_cache */ |
| 0 | 1285 /* ------------------------------------------------------------------------ */ |
| 1286 /* Dword shift operations. */ | |
| 1287 /* All the following Dword shift variants rely on the fact that | |
| 1288 shft xxx, Reg | |
| 1289 is in fact done as | |
| 1290 shft xxx, (Reg & 255) | |
| 1291 so for Reg value in (32...63) and (-1...-31) we will get zero (in the | |
| 1292 case of logical shifts) or the sign (for asr). */ | |
| 1293 | |
| 1294 #ifdef __ARMEB__ | |
| 1295 #define al r1 | |
| 1296 #define ah r0 | |
| 1297 #else | |
| 1298 #define al r0 | |
| 1299 #define ah r1 | |
| 1300 #endif | |
| 1301 | |
| 1302 /* Prevent __aeabi double-word shifts from being produced on SymbianOS. */ | |
| 1303 #ifndef __symbian__ | |
| 1304 | |
| 1305 #ifdef L_lshrdi3 | |
| 1306 | |
| 1307 FUNC_START lshrdi3 | |
| 1308 FUNC_ALIAS aeabi_llsr lshrdi3 | |
| 1309 | |
| 1310 #ifdef __thumb__ | |
| 1311 lsr al, r2 | |
| 1312 mov r3, ah | |
| 1313 lsr ah, r2 | |
| 1314 mov ip, r3 | |
| 1315 sub r2, #32 | |
| 1316 lsr r3, r2 | |
| 1317 orr al, r3 | |
| 1318 neg r2, r2 | |
| 1319 mov r3, ip | |
| 1320 lsl r3, r2 | |
| 1321 orr al, r3 | |
| 1322 RET | |
| 1323 #else | |
| 1324 subs r3, r2, #32 | |
| 1325 rsb ip, r2, #32 | |
| 1326 movmi al, al, lsr r2 | |
| 1327 movpl al, ah, lsr r3 | |
| 1328 orrmi al, al, ah, lsl ip | |
| 1329 mov ah, ah, lsr r2 | |
| 1330 RET | |
| 1331 #endif | |
| 1332 FUNC_END aeabi_llsr | |
| 1333 FUNC_END lshrdi3 | |
| 1334 | |
| 1335 #endif | |
| 1336 | |
| 1337 #ifdef L_ashrdi3 | |
| 1338 | |
| 1339 FUNC_START ashrdi3 | |
| 1340 FUNC_ALIAS aeabi_lasr ashrdi3 | |
| 1341 | |
| 1342 #ifdef __thumb__ | |
| 1343 lsr al, r2 | |
| 1344 mov r3, ah | |
| 1345 asr ah, r2 | |
| 1346 sub r2, #32 | |
| 1347 @ If r2 is negative at this point the following step would OR | |
| 1348 @ the sign bit into all of AL. That's not what we want... | |
| 1349 bmi 1f | |
| 1350 mov ip, r3 | |
| 1351 asr r3, r2 | |
| 1352 orr al, r3 | |
| 1353 mov r3, ip | |
| 1354 1: | |
| 1355 neg r2, r2 | |
| 1356 lsl r3, r2 | |
| 1357 orr al, r3 | |
| 1358 RET | |
| 1359 #else | |
| 1360 subs r3, r2, #32 | |
| 1361 rsb ip, r2, #32 | |
| 1362 movmi al, al, lsr r2 | |
| 1363 movpl al, ah, asr r3 | |
| 1364 orrmi al, al, ah, lsl ip | |
| 1365 mov ah, ah, asr r2 | |
| 1366 RET | |
| 1367 #endif | |
| 1368 | |
| 1369 FUNC_END aeabi_lasr | |
| 1370 FUNC_END ashrdi3 | |
| 1371 | |
| 1372 #endif | |
| 1373 | |
| 1374 #ifdef L_ashldi3 | |
| 1375 | |
| 1376 FUNC_START ashldi3 | |
| 1377 FUNC_ALIAS aeabi_llsl ashldi3 | |
| 1378 | |
| 1379 #ifdef __thumb__ | |
| 1380 lsl ah, r2 | |
| 1381 mov r3, al | |
| 1382 lsl al, r2 | |
| 1383 mov ip, r3 | |
| 1384 sub r2, #32 | |
| 1385 lsl r3, r2 | |
| 1386 orr ah, r3 | |
| 1387 neg r2, r2 | |
| 1388 mov r3, ip | |
| 1389 lsr r3, r2 | |
| 1390 orr ah, r3 | |
| 1391 RET | |
| 1392 #else | |
| 1393 subs r3, r2, #32 | |
| 1394 rsb ip, r2, #32 | |
| 1395 movmi ah, ah, lsl r2 | |
| 1396 movpl ah, al, lsl r3 | |
| 1397 orrmi ah, ah, al, lsr ip | |
| 1398 mov al, al, lsl r2 | |
| 1399 RET | |
| 1400 #endif | |
| 1401 FUNC_END aeabi_llsl | |
| 1402 FUNC_END ashldi3 | |
| 1403 | |
| 1404 #endif | |
| 1405 | |
| 1406 #endif /* __symbian__ */ | |
| 1407 | |
| 1408 #if ((__ARM_ARCH__ > 5) && !defined(__ARM_ARCH_6M__)) \ | |
| 1409 || defined(__ARM_ARCH_5E__) || defined(__ARM_ARCH_5TE__) \ | |
| 1410 || defined(__ARM_ARCH_5TEJ__) | |
| 1411 #define HAVE_ARM_CLZ 1 | |
| 1412 #endif | |
| 1413 | |
| 1414 #ifdef L_clzsi2 | |
| 1415 #if defined(__ARM_ARCH_6M__) | |
| 1416 FUNC_START clzsi2 | |
| 1417 mov r1, #28 | |
| 1418 mov r3, #1 | |
| 1419 lsl r3, r3, #16 | |
| 1420 cmp r0, r3 /* 0x10000 */ | |
| 1421 bcc 2f | |
| 1422 lsr r0, r0, #16 | |
| 1423 sub r1, r1, #16 | |
| 1424 2: lsr r3, r3, #8 | |
| 1425 cmp r0, r3 /* #0x100 */ | |
| 1426 bcc 2f | |
| 1427 lsr r0, r0, #8 | |
| 1428 sub r1, r1, #8 | |
| 1429 2: lsr r3, r3, #4 | |
| 1430 cmp r0, r3 /* #0x10 */ | |
| 1431 bcc 2f | |
| 1432 lsr r0, r0, #4 | |
| 1433 sub r1, r1, #4 | |
| 1434 2: adr r2, 1f | |
| 1435 ldrb r0, [r2, r0] | |
| 1436 add r0, r0, r1 | |
| 1437 bx lr | |
| 1438 .align 2 | |
| 1439 1: | |
| 1440 .byte 4, 3, 2, 2, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 | |
| 1441 FUNC_END clzsi2 | |
| 1442 #else | |
| 1443 ARM_FUNC_START clzsi2 | |
| 1444 # if defined(HAVE_ARM_CLZ) | |
| 1445 clz r0, r0 | |
| 1446 RET | |
| 1447 # else | |
| 1448 mov r1, #28 | |
| 1449 cmp r0, #0x10000 | |
| 1450 do_it cs, t | |
| 1451 movcs r0, r0, lsr #16 | |
| 1452 subcs r1, r1, #16 | |
| 1453 cmp r0, #0x100 | |
| 1454 do_it cs, t | |
| 1455 movcs r0, r0, lsr #8 | |
| 1456 subcs r1, r1, #8 | |
| 1457 cmp r0, #0x10 | |
| 1458 do_it cs, t | |
| 1459 movcs r0, r0, lsr #4 | |
| 1460 subcs r1, r1, #4 | |
| 1461 adr r2, 1f | |
| 1462 ldrb r0, [r2, r0] | |
| 1463 add r0, r0, r1 | |
| 1464 RET | |
| 1465 .align 2 | |
| 1466 1: | |
| 1467 .byte 4, 3, 2, 2, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 | |
| 1468 # endif /* !HAVE_ARM_CLZ */ | |
| 1469 FUNC_END clzsi2 | |
| 1470 #endif | |
| 1471 #endif /* L_clzsi2 */ | |
| 1472 | |
| 1473 #ifdef L_clzdi2 | |
| 1474 #if !defined(HAVE_ARM_CLZ) | |
| 1475 | |
| 1476 # if defined(__ARM_ARCH_6M__) | |
| 1477 FUNC_START clzdi2 | |
| 1478 push {r4, lr} | |
| 1479 # else | |
| 1480 ARM_FUNC_START clzdi2 | |
| 1481 do_push {r4, lr} | |
| 1482 # endif | |
| 1483 cmp xxh, #0 | |
| 1484 bne 1f | |
| 1485 # ifdef __ARMEB__ | |
| 1486 mov r0, xxl | |
| 1487 bl __clzsi2 | |
| 1488 add r0, r0, #32 | |
| 1489 b 2f | |
| 1490 1: | |
| 1491 bl __clzsi2 | |
| 1492 # else | |
| 1493 bl __clzsi2 | |
| 1494 add r0, r0, #32 | |
| 1495 b 2f | |
| 1496 1: | |
| 1497 mov r0, xxh | |
| 1498 bl __clzsi2 | |
| 1499 # endif | |
| 1500 2: | |
| 1501 # if defined(__ARM_ARCH_6M__) | |
| 1502 pop {r4, pc} | |
| 1503 # else | |
| 1504 RETLDM r4 | |
| 1505 # endif | |
| 1506 FUNC_END clzdi2 | |
| 1507 | |
| 1508 #else /* HAVE_ARM_CLZ */ | |
| 1509 | |
| 1510 ARM_FUNC_START clzdi2 | |
| 1511 cmp xxh, #0 | |
| 1512 do_it eq, et | |
| 1513 clzeq r0, xxl | |
| 1514 clzne r0, xxh | |
| 1515 addeq r0, r0, #32 | |
| 1516 RET | |
| 1517 FUNC_END clzdi2 | |
| 1518 | |
| 1519 #endif | |
| 1520 #endif /* L_clzdi2 */ | |
| 1521 | |
| 1522 /* ------------------------------------------------------------------------ */ | |
| 1523 /* These next two sections are here despite the fact that they contain Thumb | |
| 1524 assembler because their presence allows interworked code to be linked even | |
| 1525 when the GCC library is this one. */ | |
| 1526 | |
| 1527 /* Do not build the interworking functions when the target architecture does | |
| 1528 not support Thumb instructions. (This can be a multilib option). */ | |
| 1529 #if defined __ARM_ARCH_4T__ || defined __ARM_ARCH_5T__\ | |
| 1530 || defined __ARM_ARCH_5TE__ || defined __ARM_ARCH_5TEJ__ \ | |
| 1531 || __ARM_ARCH__ >= 6 | |
| 1532 | |
| 1533 #if defined L_call_via_rX | |
| 1534 | |
| 1535 /* These labels & instructions are used by the Arm/Thumb interworking code. | |
| 1536 The address of function to be called is loaded into a register and then | |
| 1537 one of these labels is called via a BL instruction. This puts the | |
| 1538 return address into the link register with the bottom bit set, and the | |
| 1539 code here switches to the correct mode before executing the function. */ | |
| 1540 | |
| 1541 .text | |
| 1542 .align 0 | |
| 1543 .force_thumb | |
| 1544 | |
| 1545 .macro call_via register | |
| 1546 THUMB_FUNC_START _call_via_\register | |
| 1547 | |
| 1548 bx \register | |
| 1549 nop | |
| 1550 | |
| 1551 SIZE (_call_via_\register) | |
| 1552 .endm | |
| 1553 | |
| 1554 call_via r0 | |
| 1555 call_via r1 | |
| 1556 call_via r2 | |
| 1557 call_via r3 | |
| 1558 call_via r4 | |
| 1559 call_via r5 | |
| 1560 call_via r6 | |
| 1561 call_via r7 | |
| 1562 call_via r8 | |
| 1563 call_via r9 | |
| 1564 call_via sl | |
| 1565 call_via fp | |
| 1566 call_via ip | |
| 1567 call_via sp | |
| 1568 call_via lr | |
| 1569 | |
| 1570 #endif /* L_call_via_rX */ | |
| 1571 | |
| 1572 /* Don't bother with the old interworking routines for Thumb-2. */ | |
| 1573 /* ??? Maybe only omit these on "m" variants. */ | |
| 1574 #if !defined(__thumb2__) && !defined(__ARM_ARCH_6M__) | |
| 1575 | |
| 1576 #if defined L_interwork_call_via_rX | |
| 1577 | |
| 1578 /* These labels & instructions are used by the Arm/Thumb interworking code, | |
| 1579 when the target address is in an unknown instruction set. The address | |
| 1580 of function to be called is loaded into a register and then one of these | |
| 1581 labels is called via a BL instruction. This puts the return address | |
| 1582 into the link register with the bottom bit set, and the code here | |
| 1583 switches to the correct mode before executing the function. Unfortunately | |
| 1584 the target code cannot be relied upon to return via a BX instruction, so | |
| 1585 instead we have to store the resturn address on the stack and allow the | |
| 1586 called function to return here instead. Upon return we recover the real | |
| 1587 return address and use a BX to get back to Thumb mode. | |
| 1588 | |
| 1589 There are three variations of this code. The first, | |
| 1590 _interwork_call_via_rN(), will push the return address onto the | |
| 1591 stack and pop it in _arm_return(). It should only be used if all | |
| 1592 arguments are passed in registers. | |
| 1593 | |
| 1594 The second, _interwork_r7_call_via_rN(), instead stores the return | |
| 1595 address at [r7, #-4]. It is the caller's responsibility to ensure | |
| 1596 that this address is valid and contains no useful data. | |
| 1597 | |
| 1598 The third, _interwork_r11_call_via_rN(), works in the same way but | |
| 1599 uses r11 instead of r7. It is useful if the caller does not really | |
| 1600 need a frame pointer. */ | |
| 1601 | |
| 1602 .text | |
| 1603 .align 0 | |
| 1604 | |
| 1605 .code 32 | |
| 1606 .globl _arm_return | |
| 1607 LSYM(Lstart_arm_return): | |
| 1608 cfi_start LSYM(Lstart_arm_return) LSYM(Lend_arm_return) | |
| 1609 cfi_push 0, 0xe, -0x8, 0x8 | |
| 1610 nop @ This nop is for the benefit of debuggers, so that | |
| 1611 @ backtraces will use the correct unwind information. | |
| 1612 _arm_return: | |
| 1613 RETLDM unwind=LSYM(Lstart_arm_return) | |
| 1614 cfi_end LSYM(Lend_arm_return) | |
| 1615 | |
| 1616 .globl _arm_return_r7 | |
| 1617 _arm_return_r7: | |
| 1618 ldr lr, [r7, #-4] | |
| 1619 bx lr | |
| 1620 | |
| 1621 .globl _arm_return_r11 | |
| 1622 _arm_return_r11: | |
| 1623 ldr lr, [r11, #-4] | |
| 1624 bx lr | |
| 1625 | |
| 1626 .macro interwork_with_frame frame, register, name, return | |
| 1627 .code 16 | |
| 1628 | |
| 1629 THUMB_FUNC_START \name | |
| 1630 | |
| 1631 bx pc | |
| 1632 nop | |
| 1633 | |
| 1634 .code 32 | |
| 1635 tst \register, #1 | |
| 1636 streq lr, [\frame, #-4] | |
| 1637 adreq lr, _arm_return_\frame | |
| 1638 bx \register | |
| 1639 | |
| 1640 SIZE (\name) | |
| 1641 .endm | |
| 1642 | |
| 1643 .macro interwork register | |
| 1644 .code 16 | |
| 1645 | |
| 1646 THUMB_FUNC_START _interwork_call_via_\register | |
| 1647 | |
| 1648 bx pc | |
| 1649 nop | |
| 1650 | |
| 1651 .code 32 | |
| 1652 .globl LSYM(Lchange_\register) | |
| 1653 LSYM(Lchange_\register): | |
| 1654 tst \register, #1 | |
| 1655 streq lr, [sp, #-8]! | |
| 1656 adreq lr, _arm_return | |
| 1657 bx \register | |
| 1658 | |
| 1659 SIZE (_interwork_call_via_\register) | |
| 1660 | |
| 1661 interwork_with_frame r7,\register,_interwork_r7_call_via_\register | |
| 1662 interwork_with_frame r11,\register,_interwork_r11_call_via_\register | |
| 1663 .endm | |
| 1664 | |
| 1665 interwork r0 | |
| 1666 interwork r1 | |
| 1667 interwork r2 | |
| 1668 interwork r3 | |
| 1669 interwork r4 | |
| 1670 interwork r5 | |
| 1671 interwork r6 | |
| 1672 interwork r7 | |
| 1673 interwork r8 | |
| 1674 interwork r9 | |
| 1675 interwork sl | |
| 1676 interwork fp | |
| 1677 interwork ip | |
| 1678 interwork sp | |
| 1679 | |
| 1680 /* The LR case has to be handled a little differently... */ | |
| 1681 .code 16 | |
| 1682 | |
| 1683 THUMB_FUNC_START _interwork_call_via_lr | |
| 1684 | |
| 1685 bx pc | |
| 1686 nop | |
| 1687 | |
| 1688 .code 32 | |
| 1689 .globl .Lchange_lr | |
| 1690 .Lchange_lr: | |
| 1691 tst lr, #1 | |
| 1692 stmeqdb r13!, {lr, pc} | |
| 1693 mov ip, lr | |
| 1694 adreq lr, _arm_return | |
| 1695 bx ip | |
| 1696 | |
| 1697 SIZE (_interwork_call_via_lr) | |
| 1698 | |
| 1699 #endif /* L_interwork_call_via_rX */ | |
| 1700 #endif /* !__thumb2__ */ | |
|
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1701 |
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1702 /* Functions to support compact pic switch tables in thumb1 state. |
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1703 All these routines take an index into the table in r0. The |
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1704 table is at LR & ~1 (but this must be rounded up in the case |
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1705 of 32-bit entires). They are only permitted to clobber r12 |
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1706 and r14 and r0 must be preserved on exit. */ |
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1707 #ifdef L_thumb1_case_sqi |
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1708 |
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1709 .text |
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1710 .align 0 |
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1711 .force_thumb |
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1712 .syntax unified |
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1713 THUMB_FUNC_START __gnu_thumb1_case_sqi |
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1714 push {r1} |
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1715 mov r1, lr |
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1716 lsrs r1, r1, #1 |
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1717 lsls r1, r1, #1 |
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1718 ldrsb r1, [r1, r0] |
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1719 lsls r1, r1, #1 |
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1720 add lr, lr, r1 |
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1721 pop {r1} |
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1722 bx lr |
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1723 SIZE (__gnu_thumb1_case_sqi) |
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1724 #endif |
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1725 |
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1726 #ifdef L_thumb1_case_uqi |
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1727 |
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1728 .text |
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1729 .align 0 |
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1730 .force_thumb |
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1731 .syntax unified |
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1732 THUMB_FUNC_START __gnu_thumb1_case_uqi |
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|
1733 push {r1} |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1734 mov r1, lr |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1735 lsrs r1, r1, #1 |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1736 lsls r1, r1, #1 |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1737 ldrb r1, [r1, r0] |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1738 lsls r1, r1, #1 |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1739 add lr, lr, r1 |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1740 pop {r1} |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1741 bx lr |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1742 SIZE (__gnu_thumb1_case_uqi) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1743 #endif |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1744 |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1745 #ifdef L_thumb1_case_shi |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1746 |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1747 .text |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1748 .align 0 |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1749 .force_thumb |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1750 .syntax unified |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1751 THUMB_FUNC_START __gnu_thumb1_case_shi |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1752 push {r0, r1} |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1753 mov r1, lr |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1754 lsrs r1, r1, #1 |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1755 lsls r0, r0, #1 |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1756 lsls r1, r1, #1 |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1757 ldrsh r1, [r1, r0] |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1758 lsls r1, r1, #1 |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1759 add lr, lr, r1 |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1760 pop {r0, r1} |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1761 bx lr |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1762 SIZE (__gnu_thumb1_case_shi) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1763 #endif |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1764 |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1765 #ifdef L_thumb1_case_uhi |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1766 |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1767 .text |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1768 .align 0 |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1769 .force_thumb |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1770 .syntax unified |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1771 THUMB_FUNC_START __gnu_thumb1_case_uhi |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1772 push {r0, r1} |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1773 mov r1, lr |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1774 lsrs r1, r1, #1 |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1775 lsls r0, r0, #1 |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1776 lsls r1, r1, #1 |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1777 ldrh r1, [r1, r0] |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1778 lsls r1, r1, #1 |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1779 add lr, lr, r1 |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1780 pop {r0, r1} |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1781 bx lr |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1782 SIZE (__gnu_thumb1_case_uhi) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1783 #endif |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1784 |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1785 #ifdef L_thumb1_case_si |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1786 |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1787 .text |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1788 .align 0 |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1789 .force_thumb |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1790 .syntax unified |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1791 THUMB_FUNC_START __gnu_thumb1_case_si |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1792 push {r0, r1} |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1793 mov r1, lr |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1794 adds.n r1, r1, #2 /* Align to word. */ |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1795 lsrs r1, r1, #2 |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1796 lsls r0, r0, #2 |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1797 lsls r1, r1, #2 |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1798 ldr r0, [r1, r0] |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1799 adds r0, r0, r1 |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1800 mov lr, r0 |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1801 pop {r0, r1} |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1802 mov pc, lr /* We know we were called from thumb code. */ |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1803 SIZE (__gnu_thumb1_case_si) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1804 #endif |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
1805 |
| 0 | 1806 #endif /* Arch supports thumb. */ |
| 1807 | |
| 1808 #ifndef __symbian__ | |
| 1809 #ifndef __ARM_ARCH_6M__ | |
| 1810 #include "ieee754-df.S" | |
| 1811 #include "ieee754-sf.S" | |
| 1812 #include "bpabi.S" | |
| 1813 #else /* __ARM_ARCH_6M__ */ | |
| 1814 #include "bpabi-v6m.S" | |
| 1815 #endif /* __ARM_ARCH_6M__ */ | |
| 1816 #endif /* !__symbian__ */ |