Mercurial > hg > CbC > CbC_gcc
annotate gcc/config/iq2000/iq2000.md @ 55:77e2b8dfacca gcc-4.4.5
update it from 4.4.3 to 4.5.0
| author | ryoma <e075725@ie.u-ryukyu.ac.jp> |
|---|---|
| date | Fri, 12 Feb 2010 23:39:51 +0900 |
| parents | a06113de4d67 |
| children | f6334be47118 |
| rev | line source |
|---|---|
| 0 | 1 ;; iq2000.md Machine Description for Vitesse IQ2000 processors |
| 2 ;; Copyright (C) 2003, 2004, 2005, 2007 Free Software Foundation, Inc. | |
| 3 | |
| 4 ;; This file is part of GCC. | |
| 5 | |
| 6 ;; GCC is free software; you can redistribute it and/or modify | |
| 7 ;; it under the terms of the GNU General Public License as published by | |
| 8 ;; the Free Software Foundation; either version 3, or (at your option) | |
| 9 ;; any later version. | |
| 10 | |
| 11 ;; GCC is distributed in the hope that it will be useful, | |
| 12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 14 ;; GNU General Public License for more details. | |
| 15 | |
| 16 ;; You should have received a copy of the GNU General Public License | |
| 17 ;; along with GCC; see the file COPYING3. If not see | |
| 18 ;; <http://www.gnu.org/licenses/>. | |
| 19 | |
| 20 (define_constants | |
| 21 [(UNSPEC_ADO16 0) | |
| 22 (UNSPEC_RAM 1) | |
| 23 (UNSPEC_CHKHDR 2) | |
| 24 (UNSPEC_PKRL 3) | |
| 25 (UNSPEC_CFC0 4) | |
| 26 (UNSPEC_CFC1 5) | |
| 27 (UNSPEC_CFC2 6) | |
| 28 (UNSPEC_CFC3 7) | |
| 29 (UNSPEC_CTC0 8) | |
| 30 (UNSPEC_CTC1 9) | |
| 31 (UNSPEC_CTC2 10) | |
| 32 (UNSPEC_CTC3 11) | |
| 33 (UNSPEC_MFC0 12) | |
| 34 (UNSPEC_MFC1 13) | |
| 35 (UNSPEC_MFC2 14) | |
| 36 (UNSPEC_MFC3 15) | |
| 37 (UNSPEC_MTC0 16) | |
| 38 (UNSPEC_MTC1 17) | |
| 39 (UNSPEC_MTC2 18) | |
| 40 (UNSPEC_MTC3 19) | |
| 41 (UNSPEC_LUR 20) | |
| 42 (UNSPEC_RB 21) | |
| 43 (UNSPEC_RX 22) | |
| 44 (UNSPEC_SRRD 23) | |
| 45 (UNSPEC_SRWR 24) | |
| 46 (UNSPEC_WB 25) | |
| 47 (UNSPEC_WX 26) | |
| 48 (UNSPEC_LUC32 49) | |
| 49 (UNSPEC_LUC32L 27) | |
| 50 (UNSPEC_LUC64 28) | |
| 51 (UNSPEC_LUC64L 29) | |
| 52 (UNSPEC_LUK 30) | |
| 53 (UNSPEC_LULCK 31) | |
| 54 (UNSPEC_LUM32 32) | |
| 55 (UNSPEC_LUM32L 33) | |
| 56 (UNSPEC_LUM64 34) | |
| 57 (UNSPEC_LUM64L 35) | |
| 58 (UNSPEC_LURL 36) | |
| 59 (UNSPEC_MRGB 37) | |
| 60 (UNSPEC_SRRDL 38) | |
| 61 (UNSPEC_SRULCK 39) | |
| 62 (UNSPEC_SRWRU 40) | |
| 63 (UNSPEC_TRAPQFL 41) | |
| 64 (UNSPEC_TRAPQNE 42) | |
| 65 (UNSPEC_TRAPREL 43) | |
| 66 (UNSPEC_WBU 44) | |
| 67 (UNSPEC_SYSCALL 45)] | |
| 68 ) | |
| 69 ;; UNSPEC values used in iq2000.md | |
| 70 ;; Number USE | |
| 71 ;; 0 movsi_ul | |
| 72 ;; 1 movsi_us, get_fnaddr | |
| 73 ;; 3 eh_set_return | |
| 74 ;; 20 builtin_setjmp_setup | |
| 75 ;; | |
| 76 ;; UNSPEC_VOLATILE values | |
| 77 ;; 0 blockage | |
| 78 ;; 2 loadgp | |
| 79 ;; 3 builtin_longjmp | |
| 80 ;; 4 exception_receiver | |
| 81 ;; 10 consttable_qi | |
| 82 ;; 11 consttable_hi | |
| 83 ;; 12 consttable_si | |
| 84 ;; 13 consttable_di | |
| 85 ;; 14 consttable_sf | |
| 86 ;; 15 consttable_df | |
| 87 ;; 16 align_2 | |
| 88 ;; 17 align_4 | |
| 89 ;; 18 align_8 | |
| 90 | |
| 91 | |
| 92 ;; .................... | |
| 93 ;; | |
| 94 ;; Attributes | |
| 95 ;; | |
| 96 ;; .................... | |
| 97 | |
| 98 ;; Classification of each insn. | |
| 99 ;; branch conditional branch | |
| 100 ;; jump unconditional jump | |
| 101 ;; call unconditional call | |
| 102 ;; load load instruction(s) | |
| 103 ;; store store instruction(s) | |
| 104 ;; move data movement within same register set | |
| 105 ;; xfer transfer to/from coprocessor | |
| 106 ;; arith integer arithmetic instruction | |
| 107 ;; darith double precision integer arithmetic instructions | |
| 108 ;; imul integer multiply | |
| 109 ;; idiv integer divide | |
| 110 ;; icmp integer compare | |
| 111 ;; fadd floating point add/subtract | |
| 112 ;; fmul floating point multiply | |
| 113 ;; fmadd floating point multiply-add | |
| 114 ;; fdiv floating point divide | |
| 115 ;; fabs floating point absolute value | |
| 116 ;; fneg floating point negation | |
| 117 ;; fcmp floating point compare | |
| 118 ;; fcvt floating point convert | |
| 119 ;; fsqrt floating point square root | |
| 120 ;; multi multiword sequence (or user asm statements) | |
| 121 ;; nop no operation | |
| 122 | |
| 123 (define_attr "type" | |
| 124 "unknown,branch,jump,call,load,store,move,xfer,arith,darith,imul,idiv,icmp,fadd,fmul,fmadd,fdiv,fabs,fneg,fcmp,fcvt,fsqrt,multi,nop" | |
| 125 (const_string "unknown")) | |
| 126 | |
| 127 ;; Main data type used by the insn | |
| 128 (define_attr "mode" "unknown,none,QI,HI,SI,DI,SF,DF,FPSW" (const_string "unknown")) | |
| 129 | |
| 130 ;; Length (in # of bytes). A conditional branch is allowed only to a | |
| 131 ;; location within a signed 18-bit offset of the delay slot. If that | |
| 132 ;; provides too small a range, we use the `j' instruction. This | |
| 133 ;; instruction takes a 28-bit value, but that value is not an offset. | |
| 134 ;; Instead, it's bitwise-ored with the high-order four bits of the | |
| 135 ;; instruction in the delay slot, which means it cannot be used to | |
| 136 ;; cross a 256MB boundary. We could fall back back on the jr, | |
| 137 ;; instruction which allows full access to the entire address space, | |
| 138 ;; but we do not do so at present. | |
| 139 | |
| 140 (define_attr "length" "" | |
| 141 (cond [(eq_attr "type" "branch") | |
| 142 (cond [(lt (abs (minus (match_dup 1) (plus (pc) (const_int 4)))) | |
| 143 (const_int 131072)) | |
| 144 (const_int 4)] | |
| 145 (const_int 12))] | |
| 146 (const_int 4))) | |
| 147 | |
| 148 (define_attr "cpu" | |
| 149 "default,iq2000" | |
| 150 (const (symbol_ref "iq2000_cpu_attr"))) | |
| 151 | |
| 152 ;; Does the instruction have a mandatory delay slot? has_dslot | |
| 153 ;; Can the instruction be in a delay slot? ok_in_dslot | |
| 154 ;; Can the instruction not be in a delay slot? not_in_dslot | |
| 155 (define_attr "dslot" "has_dslot,ok_in_dslot,not_in_dslot" | |
| 156 (if_then_else (eq_attr "type" "branch,jump,call,xfer,fcmp") | |
| 157 (const_string "has_dslot") | |
| 158 (const_string "ok_in_dslot"))) | |
| 159 | |
| 160 ;; Attribute defining whether or not we can use the branch-likely instructions | |
| 161 | |
| 162 (define_attr "branch_likely" "no,yes" | |
| 163 (const | |
| 164 (if_then_else (ne (symbol_ref "GENERATE_BRANCHLIKELY") (const_int 0)) | |
| 165 (const_string "yes") | |
| 166 (const_string "no")))) | |
| 167 | |
| 168 | |
| 169 ;; Describe a user's asm statement. | |
| 170 (define_asm_attributes | |
| 171 [(set_attr "type" "multi")]) | |
| 172 | |
| 173 | |
| 174 | |
| 175 ;; ......................... | |
| 176 ;; | |
| 177 ;; Delay slots, can't describe load/fcmp/xfer delay slots here | |
| 178 ;; | |
| 179 ;; ......................... | |
| 180 | |
| 181 (define_delay (eq_attr "type" "jump") | |
| 182 [(and (eq_attr "dslot" "ok_in_dslot") (eq_attr "length" "4")) | |
| 183 (nil) | |
| 184 (nil)]) | |
| 185 | |
| 186 (define_delay (eq_attr "type" "branch") | |
| 187 [(and (eq_attr "dslot" "ok_in_dslot") (eq_attr "length" "4")) | |
| 188 (nil) | |
| 189 (and (eq_attr "branch_likely" "yes") (and (eq_attr "dslot" "ok_in_dslot") (eq_attr "length" "4")))]) | |
| 190 | |
| 191 (define_delay (eq_attr "type" "call") | |
| 192 [(and (eq_attr "dslot" "ok_in_dslot") (eq_attr "length" "4")) | |
| 193 (nil) | |
| 194 (nil)]) | |
| 195 | |
| 196 (include "predicates.md") | |
| 197 | |
| 198 | |
| 199 ;; ......................... | |
| 200 ;; | |
| 201 ;; Pipeline model | |
| 202 ;; | |
| 203 ;; ......................... | |
| 204 | |
| 205 (define_automaton "iq2000") | |
| 206 (define_cpu_unit "core,memory" "iq2000") | |
| 207 | |
| 208 (define_insn_reservation "nonmemory" 1 | |
| 209 (eq_attr "type" "!load,move,store,xfer") | |
| 210 "core") | |
| 211 | |
| 212 (define_insn_reservation "iq2000_load_move" 3 | |
| 213 (and (eq_attr "type" "load,move") | |
| 214 (eq_attr "cpu" "iq2000")) | |
| 215 "memory") | |
| 216 | |
| 217 (define_insn_reservation "other_load_move" 1 | |
| 218 (and (eq_attr "type" "load,move") | |
| 219 (eq_attr "cpu" "!iq2000")) | |
| 220 "memory") | |
| 221 | |
| 222 (define_insn_reservation "store" 1 | |
| 223 (eq_attr "type" "store") | |
| 224 "memory") | |
| 225 | |
| 226 (define_insn_reservation "xfer" 2 | |
| 227 (eq_attr "type" "xfer") | |
| 228 "memory") | |
| 229 | |
| 230 ;; | |
| 231 ;; .................... | |
| 232 ;; | |
| 233 ;; CONDITIONAL TRAPS | |
| 234 ;; | |
| 235 ;; .................... | |
| 236 ;; | |
| 237 | |
| 238 (define_insn "trap" | |
| 239 [(trap_if (const_int 1) (const_int 0))] | |
| 240 "" | |
| 241 "* | |
| 242 { | |
| 243 return \"break\"; | |
| 244 }") | |
| 245 | |
| 246 ;; | |
| 247 ;; .................... | |
| 248 ;; | |
| 249 ;; ADDITION | |
| 250 ;; | |
| 251 ;; .................... | |
| 252 ;; | |
| 253 | |
| 254 (define_expand "addsi3" | |
| 255 [(set (match_operand:SI 0 "register_operand" "=d") | |
| 256 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ") | |
| 257 (match_operand:SI 2 "arith_operand" "dI")))] | |
| 258 "" | |
| 259 "") | |
| 260 | |
| 261 (define_insn "addsi3_internal" | |
| 262 [(set (match_operand:SI 0 "register_operand" "=d,=d") | |
| 263 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ,dJ") | |
| 264 (match_operand:SI 2 "arith_operand" "d,I")))] | |
| 265 "" | |
| 266 "@ | |
| 267 addu\\t%0,%z1,%2 | |
| 268 addiu\\t%0,%z1,%2" | |
| 269 [(set_attr "type" "arith") | |
| 270 (set_attr "mode" "SI")]) | |
| 271 | |
| 272 ;; | |
| 273 ;; .................... | |
| 274 ;; | |
| 275 ;; SUBTRACTION | |
| 276 ;; | |
| 277 ;; .................... | |
| 278 ;; | |
| 279 | |
| 280 (define_expand "subsi3" | |
| 281 [(set (match_operand:SI 0 "register_operand" "=d") | |
| 282 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ") | |
| 283 (match_operand:SI 2 "arith_operand" "dI")))] | |
| 284 "" | |
| 285 "") | |
| 286 | |
| 287 (define_insn "subsi3_internal" | |
| 288 [(set (match_operand:SI 0 "register_operand" "=d,=d") | |
| 289 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ,dJ") | |
| 290 (match_operand:SI 2 "arith_operand" "d,I")))] | |
| 291 "" | |
| 292 "@ | |
| 293 subu\\t%0,%z1,%2 | |
| 294 addiu\\t%0,%z1,%n2" | |
| 295 [(set_attr "type" "arith") | |
| 296 (set_attr "mode" "SI")]) | |
| 297 | |
| 298 ;; | |
| 299 ;; .................... | |
| 300 ;; | |
| 301 ;; NEGATION and ONE'S COMPLEMENT | |
| 302 ;; | |
| 303 ;; .................... | |
| 304 | |
| 305 (define_insn "negsi2" | |
| 306 [(set (match_operand:SI 0 "register_operand" "=d") | |
| 307 (neg:SI (match_operand:SI 1 "register_operand" "d")))] | |
| 308 "" | |
| 309 "* | |
| 310 { | |
| 311 operands[2] = const0_rtx; | |
| 312 return \"subu\\t%0,%z2,%1\"; | |
| 313 }" | |
| 314 [(set_attr "type" "arith") | |
| 315 (set_attr "mode" "SI")]) | |
| 316 | |
| 317 (define_insn "one_cmplsi2" | |
| 318 [(set (match_operand:SI 0 "register_operand" "=d") | |
| 319 (not:SI (match_operand:SI 1 "register_operand" "d")))] | |
| 320 "" | |
| 321 "* | |
| 322 { | |
| 323 operands[2] = const0_rtx; | |
| 324 return \"nor\\t%0,%z2,%1\"; | |
| 325 }" | |
| 326 [(set_attr "type" "arith") | |
| 327 (set_attr "mode" "SI")]) | |
| 328 | |
| 329 ;; | |
| 330 ;; .................... | |
| 331 ;; | |
| 332 ;; LOGICAL | |
| 333 ;; | |
| 334 ;; .................... | |
| 335 ;; | |
| 336 | |
| 337 (define_expand "andsi3" | |
| 338 [(set (match_operand:SI 0 "register_operand" "=d,d,d") | |
| 339 (and:SI (match_operand:SI 1 "uns_arith_operand" "%d,d,d") | |
| 340 (match_operand:SI 2 "nonmemory_operand" "d,K,N")))] | |
| 341 "" | |
| 342 "") | |
| 343 | |
| 344 (define_insn "" | |
| 345 [(set (match_operand:SI 0 "register_operand" "=d,d,d") | |
| 346 (and:SI (match_operand:SI 1 "uns_arith_operand" "%d,d,d") | |
| 347 (match_operand:SI 2 "nonmemory_operand" "d,K,N")))] | |
| 348 "" | |
| 349 "* | |
| 350 { | |
| 351 if (which_alternative == 0) | |
| 352 return \"and\\t%0,%1,%2\"; | |
| 353 else if (which_alternative == 1) | |
| 354 return \"andi\\t%0,%1,%x2\"; | |
| 355 else if (which_alternative == 2) | |
| 356 { | |
| 357 if ((INTVAL (operands[2]) & 0xffff) == 0xffff) | |
| 358 { | |
| 359 operands[2] = GEN_INT (INTVAL (operands[2]) >> 16); | |
| 360 return \"andoui\\t%0,%1,%x2\"; | |
| 361 } | |
| 362 else | |
| 363 { | |
| 364 operands[2] = GEN_INT (INTVAL (operands[2]) & 0xffff); | |
| 365 return \"andoi\\t%0,%1,%x2\"; | |
| 366 } | |
| 367 } | |
| 368 }" | |
| 369 [(set_attr "type" "arith") | |
| 370 (set_attr "mode" "SI")]) | |
| 371 | |
| 372 (define_expand "iorsi3" | |
| 373 [(set (match_operand:SI 0 "register_operand" "=d,d") | |
| 374 (ior:SI (match_operand:SI 1 "uns_arith_operand" "%d,d") | |
| 375 (match_operand:SI 2 "uns_arith_operand" "d,K")))] | |
| 376 "" | |
| 377 "") | |
| 378 | |
| 379 (define_insn "" | |
| 380 [(set (match_operand:SI 0 "register_operand" "=d,d") | |
| 381 (ior:SI (match_operand:SI 1 "uns_arith_operand" "%d,d") | |
| 382 (match_operand:SI 2 "uns_arith_operand" "d,K")))] | |
| 383 "" | |
| 384 "@ | |
| 385 or\\t%0,%1,%2 | |
| 386 ori\\t%0,%1,%x2" | |
| 387 [(set_attr "type" "arith") | |
| 388 (set_attr "mode" "SI")]) | |
| 389 | |
| 390 (define_expand "xorsi3" | |
| 391 [(set (match_operand:SI 0 "register_operand" "=d,d") | |
| 392 (xor:SI (match_operand:SI 1 "uns_arith_operand" "%d,d") | |
| 393 (match_operand:SI 2 "uns_arith_operand" "d,K")))] | |
| 394 "" | |
| 395 "") | |
| 396 | |
| 397 (define_insn "" | |
| 398 [(set (match_operand:SI 0 "register_operand" "=d,d") | |
| 399 (xor:SI (match_operand:SI 1 "uns_arith_operand" "%d,d") | |
| 400 (match_operand:SI 2 "uns_arith_operand" "d,K")))] | |
| 401 "" | |
| 402 "@ | |
| 403 xor\\t%0,%1,%2 | |
| 404 xori\\t%0,%1,%x2" | |
| 405 [(set_attr "type" "arith") | |
| 406 (set_attr "mode" "SI")]) | |
| 407 | |
| 408 (define_insn "*norsi3" | |
| 409 [(set (match_operand:SI 0 "register_operand" "=d") | |
| 410 (and:SI (not:SI (match_operand:SI 1 "register_operand" "d")) | |
| 411 (not:SI (match_operand:SI 2 "register_operand" "d"))))] | |
| 412 "" | |
| 413 "nor\\t%0,%z1,%z2" | |
| 414 [(set_attr "type" "arith") | |
| 415 (set_attr "mode" "SI")]) | |
| 416 | |
| 417 ;; | |
| 418 ;; .................... | |
| 419 ;; | |
| 420 ;; ZERO EXTENSION | |
| 421 ;; | |
| 422 ;; .................... | |
| 423 | |
| 424 ;; Extension insns. | |
| 425 ;; Those for integer source operand are ordered widest source type first. | |
| 426 | |
| 427 (define_expand "zero_extendhisi2" | |
| 428 [(set (match_operand:SI 0 "register_operand" "") | |
| 429 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))] | |
| 430 "" | |
| 431 "") | |
| 432 | |
| 433 (define_insn "" | |
| 434 [(set (match_operand:SI 0 "register_operand" "=d,d,d") | |
| 435 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d,R,m")))] | |
| 436 "" | |
| 437 "* | |
| 438 { | |
| 439 if (which_alternative == 0) | |
| 440 return \"andi\\t%0,%1,0xffff\"; | |
| 441 else | |
| 442 return iq2000_move_1word (operands, insn, TRUE); | |
| 443 }" | |
| 444 [(set_attr "type" "arith,load,load") | |
| 445 (set_attr "mode" "SI") | |
| 446 (set_attr "length" "4,4,8")]) | |
| 447 | |
| 448 (define_expand "zero_extendqihi2" | |
| 449 [(set (match_operand:HI 0 "register_operand" "") | |
| 450 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))] | |
| 451 "" | |
| 452 "") | |
| 453 | |
| 454 (define_insn "" | |
| 455 [(set (match_operand:HI 0 "register_operand" "=d,d,d") | |
| 456 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "d,R,m")))] | |
| 457 "" | |
| 458 "* | |
| 459 { | |
| 460 if (which_alternative == 0) | |
| 461 return \"andi\\t%0,%1,0x00ff\"; | |
| 462 else | |
| 463 return iq2000_move_1word (operands, insn, TRUE); | |
| 464 }" | |
| 465 [(set_attr "type" "arith,load,load") | |
| 466 (set_attr "mode" "HI") | |
| 467 (set_attr "length" "4,4,8")]) | |
| 468 | |
| 469 (define_expand "zero_extendqisi2" | |
| 470 [(set (match_operand:SI 0 "register_operand" "") | |
| 471 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))] | |
| 472 "" | |
| 473 "") | |
| 474 | |
| 475 (define_insn "" | |
| 476 [(set (match_operand:SI 0 "register_operand" "=d,d,d") | |
| 477 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "d,R,m")))] | |
| 478 "" | |
| 479 "* | |
| 480 { | |
| 481 if (which_alternative == 0) | |
| 482 return \"andi\\t%0,%1,0x00ff\"; | |
| 483 else | |
| 484 return iq2000_move_1word (operands, insn, TRUE); | |
| 485 }" | |
| 486 [(set_attr "type" "arith,load,load") | |
| 487 (set_attr "mode" "SI") | |
| 488 (set_attr "length" "4,4,8")]) | |
| 489 | |
| 490 ;; | |
| 491 ;; .................... | |
| 492 ;; | |
| 493 ;; SIGN EXTENSION | |
| 494 ;; | |
| 495 ;; .................... | |
| 496 | |
| 497 ;; Extension insns. | |
| 498 ;; Those for integer source operand are ordered widest source type first. | |
| 499 | |
| 500 ;; These patterns originally accepted general_operands, however, slightly | |
| 501 ;; better code is generated by only accepting register_operands, and then | |
| 502 ;; letting combine generate the lh and lb insns. | |
| 503 | |
| 504 (define_expand "extendhisi2" | |
| 505 [(set (match_operand:SI 0 "register_operand" "") | |
| 506 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))] | |
| 507 "" | |
| 508 " | |
| 509 { | |
| 510 if (optimize && GET_CODE (operands[1]) == MEM) | |
| 511 operands[1] = force_not_mem (operands[1]); | |
| 512 | |
| 513 if (GET_CODE (operands[1]) != MEM) | |
| 514 { | |
| 515 rtx op1 = gen_lowpart (SImode, operands[1]); | |
| 516 rtx temp = gen_reg_rtx (SImode); | |
| 517 rtx shift = GEN_INT (16); | |
| 518 | |
| 519 emit_insn (gen_ashlsi3 (temp, op1, shift)); | |
| 520 emit_insn (gen_ashrsi3 (operands[0], temp, shift)); | |
| 521 DONE; | |
| 522 } | |
| 523 }") | |
| 524 | |
| 525 (define_insn "extendhisi2_internal" | |
| 526 [(set (match_operand:SI 0 "register_operand" "=d,d") | |
| 527 (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,m")))] | |
| 528 "" | |
| 529 "* return iq2000_move_1word (operands, insn, FALSE);" | |
| 530 [(set_attr "type" "load") | |
| 531 (set_attr "mode" "SI") | |
| 532 (set_attr "length" "4,8")]) | |
| 533 | |
| 534 (define_expand "extendqihi2" | |
| 535 [(set (match_operand:HI 0 "register_operand" "") | |
| 536 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))] | |
| 537 "" | |
| 538 " | |
| 539 { | |
| 540 if (optimize && GET_CODE (operands[1]) == MEM) | |
| 541 operands[1] = force_not_mem (operands[1]); | |
| 542 | |
| 543 if (GET_CODE (operands[1]) != MEM) | |
| 544 { | |
| 545 rtx op0 = gen_lowpart (SImode, operands[0]); | |
| 546 rtx op1 = gen_lowpart (SImode, operands[1]); | |
| 547 rtx temp = gen_reg_rtx (SImode); | |
| 548 rtx shift = GEN_INT (24); | |
| 549 | |
| 550 emit_insn (gen_ashlsi3 (temp, op1, shift)); | |
| 551 emit_insn (gen_ashrsi3 (op0, temp, shift)); | |
| 552 DONE; | |
| 553 } | |
| 554 }") | |
| 555 | |
| 556 (define_insn "extendqihi2_internal" | |
| 557 [(set (match_operand:HI 0 "register_operand" "=d,d") | |
| 558 (sign_extend:HI (match_operand:QI 1 "memory_operand" "R,m")))] | |
| 559 "" | |
| 560 "* return iq2000_move_1word (operands, insn, FALSE);" | |
| 561 [(set_attr "type" "load") | |
| 562 (set_attr "mode" "SI") | |
| 563 (set_attr "length" "4,8")]) | |
| 564 | |
| 565 | |
| 566 (define_expand "extendqisi2" | |
| 567 [(set (match_operand:SI 0 "register_operand" "") | |
| 568 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))] | |
| 569 "" | |
| 570 " | |
| 571 { | |
| 572 if (optimize && GET_CODE (operands[1]) == MEM) | |
| 573 operands[1] = force_not_mem (operands[1]); | |
| 574 | |
| 575 if (GET_CODE (operands[1]) != MEM) | |
| 576 { | |
| 577 rtx op1 = gen_lowpart (SImode, operands[1]); | |
| 578 rtx temp = gen_reg_rtx (SImode); | |
| 579 rtx shift = GEN_INT (24); | |
| 580 | |
| 581 emit_insn (gen_ashlsi3 (temp, op1, shift)); | |
| 582 emit_insn (gen_ashrsi3 (operands[0], temp, shift)); | |
| 583 DONE; | |
| 584 } | |
| 585 }") | |
| 586 | |
| 587 (define_insn "extendqisi2_insn" | |
| 588 [(set (match_operand:SI 0 "register_operand" "=d,d") | |
| 589 (sign_extend:SI (match_operand:QI 1 "memory_operand" "R,m")))] | |
| 590 "" | |
| 591 "* return iq2000_move_1word (operands, insn, FALSE);" | |
| 592 [(set_attr "type" "load") | |
| 593 (set_attr "mode" "SI") | |
| 594 (set_attr "length" "4,8")]) | |
| 595 | |
| 596 ;; | |
| 597 ;; ........................ | |
| 598 ;; | |
| 599 ;; BIT FIELD EXTRACTION | |
| 600 ;; | |
| 601 ;; ........................ | |
| 602 | |
| 603 (define_insn "extzv" | |
| 604 [(set (match_operand:SI 0 "register_operand" "=r") | |
| 605 (zero_extract:SI (match_operand:SI 1 "register_operand" "r") | |
| 606 (match_operand:SI 2 "const_int_operand" "O") | |
| 607 (match_operand:SI 3 "const_int_operand" "O")))] | |
| 608 "" | |
| 609 "* | |
| 610 { | |
| 611 int value[4]; | |
| 612 value[2] = INTVAL (operands[2]); | |
| 613 value[3] = INTVAL (operands[3]); | |
| 614 operands[2] = GEN_INT ((value[3])); | |
| 615 operands[3] = GEN_INT ((32 - value[2])); | |
| 616 return \"ram\\t%0,%1,%2,%3,0x0\"; | |
| 617 }" | |
| 618 [(set_attr "type" "arith")]) | |
| 619 | |
| 620 ;; | |
| 621 ;; .................... | |
| 622 ;; | |
| 623 ;; DATA MOVEMENT | |
| 624 ;; | |
| 625 ;; .................... | |
| 626 | |
| 627 /* Take care of constants that don't fit in single instruction */ | |
| 628 (define_split | |
| 629 [(set (match_operand:SI 0 "register_operand" "") | |
| 630 (match_operand:SI 1 "general_operand" ""))] | |
| 631 "(reload_in_progress || reload_completed) | |
| 632 && large_int (operands[1], SImode)" | |
| 633 | |
| 634 [(set (match_dup 0 ) | |
| 635 (high:SI (match_dup 1))) | |
| 636 (set (match_dup 0 ) | |
| 637 (lo_sum:SI (match_dup 0) | |
| 638 (match_dup 1)))] | |
| 639 ) | |
| 640 | |
| 641 ;; ??? iq2000_move_1word has support for HIGH, so this pattern may be | |
| 642 ;; unnecessary. | |
| 643 | |
| 644 (define_insn "high" | |
| 645 [(set (match_operand:SI 0 "register_operand" "=r") | |
| 646 (high:SI (match_operand:SI 1 "immediate_operand" "")))] | |
| 647 "" | |
| 648 "lui\\t%0,%%hi(%1) # high" | |
| 649 [(set_attr "type" "move")]) | |
| 650 | |
| 651 (define_insn "low" | |
| 652 [(set (match_operand:SI 0 "register_operand" "=r") | |
| 653 (lo_sum:SI (match_operand:SI 1 "register_operand" "r") | |
| 654 (match_operand:SI 2 "immediate_operand" "")))] | |
| 655 "" | |
| 656 "addiu\\t%0,%1,%%lo(%2) # low" | |
| 657 [(set_attr "type" "arith") | |
| 658 (set_attr "mode" "SI")]) | |
| 659 | |
| 660 ;; 32-bit Integer moves | |
| 661 | |
| 662 (define_split | |
| 663 [(set (match_operand:SI 0 "register_operand" "") | |
| 664 (match_operand:SI 1 "large_int" ""))] | |
| 665 "reload_in_progress | reload_completed" | |
| 666 [(set (match_dup 0) | |
| 667 (match_dup 2)) | |
| 668 (set (match_dup 0) | |
| 669 (ior:SI (match_dup 0) | |
| 670 (match_dup 3)))] | |
| 671 " | |
| 672 { | |
| 673 operands[2] = GEN_INT (trunc_int_for_mode (INTVAL (operands[1]) | |
| 674 & BITMASK_UPPER16, | |
| 675 SImode)); | |
| 676 operands[3] = GEN_INT (INTVAL (operands[1]) & BITMASK_LOWER16); | |
| 677 }") | |
| 678 | |
| 679 ;; Unlike most other insns, the move insns can't be split with | |
| 680 ;; different predicates, because register spilling and other parts of | |
| 681 ;; the compiler, have memoized the insn number already. | |
| 682 | |
| 683 (define_expand "movsi" | |
| 684 [(set (match_operand:SI 0 "nonimmediate_operand" "") | |
| 685 (match_operand:SI 1 "general_operand" ""))] | |
| 686 "" | |
| 687 " | |
| 688 { | |
| 689 if (iq2000_check_split (operands[1], SImode)) | |
| 690 { | |
| 691 enum machine_mode mode = GET_MODE (operands[0]); | |
| 692 rtx tem = ((reload_in_progress | reload_completed) | |
| 693 ? operands[0] : gen_reg_rtx (mode)); | |
| 694 | |
| 695 emit_insn (gen_rtx_SET (VOIDmode, tem, | |
| 696 gen_rtx_HIGH (mode, operands[1]))); | |
| 697 | |
| 698 operands[1] = gen_rtx_LO_SUM (mode, tem, operands[1]); | |
| 699 } | |
| 700 | |
| 701 if ((reload_in_progress | reload_completed) == 0 | |
| 702 && !register_operand (operands[0], SImode) | |
| 703 && !register_operand (operands[1], SImode) | |
| 704 && (GET_CODE (operands[1]) != CONST_INT | |
| 705 || INTVAL (operands[1]) != 0)) | |
| 706 { | |
| 707 rtx temp = force_reg (SImode, operands[1]); | |
| 708 emit_move_insn (operands[0], temp); | |
| 709 DONE; | |
| 710 } | |
| 711 | |
| 712 /* Take care of constants that don't fit in single instruction */ | |
| 713 if ((reload_in_progress || reload_completed) | |
| 714 && CONSTANT_P (operands[1]) | |
| 715 && GET_CODE (operands[1]) != HIGH | |
| 716 && GET_CODE (operands[1]) != LO_SUM | |
| 717 && ! SMALL_INT_UNSIGNED (operands[1])) | |
| 718 { | |
| 719 rtx tem = ((reload_in_progress | reload_completed) | |
| 720 ? operands[0] : gen_reg_rtx (SImode)); | |
| 721 | |
| 722 emit_insn (gen_rtx_SET (VOIDmode, tem, | |
| 723 gen_rtx_HIGH (SImode, operands[1]))); | |
| 724 operands[1] = gen_rtx_LO_SUM (SImode, tem, operands[1]); | |
| 725 } | |
| 726 }") | |
| 727 | |
| 728 ;; The difference between these two is whether or not ints are allowed | |
| 729 ;; in FP registers (off by default, use -mdebugh to enable). | |
| 730 | |
| 731 (define_insn "movsi_internal2" | |
| 732 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,R,m,*d,*z,*x,*d,*x,*d") | |
| 733 (match_operand:SI 1 "move_operand" "d,S,IKL,Mnis,R,m,dJ,dJ,*z,*d,J,*x,*d,*a"))] | |
| 734 "(register_operand (operands[0], SImode) | |
| 735 || register_operand (operands[1], SImode) | |
| 736 || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))" | |
| 737 "* return iq2000_move_1word (operands, insn, FALSE);" | |
| 738 [(set_attr "type" "move,load,arith,arith,load,load,store,store,xfer,xfer,move,move,move,move") | |
| 739 (set_attr "mode" "SI") | |
|
55
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
740 (set_attr "length" "4,8,4,8,8,8,4,8,4,4,4,4,4,4")]) |
| 0 | 741 |
| 742 ;; 16-bit Integer moves | |
| 743 | |
| 744 ;; Unlike most other insns, the move insns can't be split with | |
| 745 ;; different predicates, because register spilling and other parts of | |
| 746 ;; the compiler, have memoized the insn number already. | |
| 747 ;; Unsigned loads are used because BYTE_LOADS_ZERO_EXTEND is defined | |
| 748 | |
| 749 (define_expand "movhi" | |
| 750 [(set (match_operand:HI 0 "nonimmediate_operand" "") | |
| 751 (match_operand:HI 1 "general_operand" ""))] | |
| 752 "" | |
| 753 " | |
| 754 { | |
| 755 if ((reload_in_progress | reload_completed) == 0 | |
| 756 && !register_operand (operands[0], HImode) | |
| 757 && !register_operand (operands[1], HImode) | |
| 758 && ((GET_CODE (operands[1]) != CONST_INT | |
| 759 || INTVAL (operands[1]) != 0))) | |
| 760 { | |
| 761 rtx temp = force_reg (HImode, operands[1]); | |
| 762 emit_move_insn (operands[0], temp); | |
| 763 DONE; | |
| 764 } | |
| 765 }") | |
| 766 | |
| 767 ;; The difference between these two is whether or not ints are allowed | |
| 768 ;; in FP registers (off by default, use -mdebugh to enable). | |
| 769 | |
| 770 (define_insn "movhi_internal2" | |
| 771 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,R,m,*d,*z,*x,*d") | |
| 772 (match_operand:HI 1 "general_operand" "d,IK,R,m,dJ,dJ,*z,*d,*d,*x"))] | |
| 773 "(register_operand (operands[0], HImode) | |
| 774 || register_operand (operands[1], HImode) | |
| 775 || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))" | |
| 776 "* return iq2000_move_1word (operands, insn, TRUE);" | |
| 777 [(set_attr "type" "move,arith,load,load,store,store,xfer,xfer,move,move") | |
| 778 (set_attr "mode" "HI") | |
| 779 (set_attr "length" "4,4,4,8,4,8,4,4,4,4")]) | |
| 780 | |
| 781 ;; 8-bit Integer moves | |
| 782 | |
| 783 ;; Unlike most other insns, the move insns can't be split with | |
| 784 ;; different predicates, because register spilling and other parts of | |
| 785 ;; the compiler, have memoized the insn number already. | |
| 786 ;; Unsigned loads are used because BYTE_LOADS_ZERO_EXTEND is defined | |
| 787 | |
| 788 (define_expand "movqi" | |
| 789 [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
| 790 (match_operand:QI 1 "general_operand" ""))] | |
| 791 "" | |
| 792 " | |
| 793 { | |
| 794 if ((reload_in_progress | reload_completed) == 0 | |
| 795 && !register_operand (operands[0], QImode) | |
| 796 && !register_operand (operands[1], QImode) | |
| 797 && (GET_CODE (operands[1]) != CONST_INT | |
| 798 || INTVAL (operands[1]) != 0)) | |
| 799 { | |
| 800 rtx temp = force_reg (QImode, operands[1]); | |
| 801 emit_move_insn (operands[0], temp); | |
| 802 DONE; | |
| 803 } | |
| 804 }") | |
| 805 | |
| 806 ;; The difference between these two is whether or not ints are allowed | |
| 807 ;; in FP registers (off by default, use -mdebugh to enable). | |
| 808 | |
| 809 (define_insn "movqi_internal2" | |
| 810 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,m,*d,*z,*x,*d") | |
| 811 (match_operand:QI 1 "general_operand" "d,IK,R,m,dJ,dJ,*z,*d,*d,*x"))] | |
| 812 "(register_operand (operands[0], QImode) | |
| 813 || register_operand (operands[1], QImode) | |
| 814 || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))" | |
| 815 "* return iq2000_move_1word (operands, insn, TRUE);" | |
| 816 [(set_attr "type" "move,arith,load,load,store,store,xfer,xfer,move,move") | |
| 817 (set_attr "mode" "QI") | |
| 818 (set_attr "length" "4,4,4,8,4,8,4,4,4,4")]) | |
| 819 | |
| 820 ;; 32-bit floating point moves | |
| 821 | |
| 822 (define_expand "movsf" | |
| 823 [(set (match_operand:SF 0 "general_operand" "") | |
| 824 (match_operand:SF 1 "general_operand" ""))] | |
| 825 "" | |
| 826 " | |
| 827 { | |
| 828 if (!reload_in_progress | |
| 829 && !reload_completed | |
| 830 && GET_CODE (operands[0]) == MEM | |
| 831 && (GET_CODE (operands[1]) == MEM | |
| 832 || GET_CODE (operands[1]) == CONST_DOUBLE)) | |
| 833 operands[1] = copy_to_mode_reg (SFmode, operands[1]); | |
| 834 | |
| 835 /* Take care of reg <- SF constant */ | |
| 836 if ( const_double_operand (operands[1], GET_MODE (operands[1]) ) ) | |
| 837 { | |
| 838 emit_insn (gen_movsf_high (operands[0], operands[1])); | |
| 839 emit_insn (gen_movsf_lo_sum (operands[0], operands[0], operands[1])); | |
| 840 DONE; | |
| 841 } | |
| 842 }") | |
| 843 | |
| 844 (define_insn "movsf_lo_sum" | |
| 845 [(set (match_operand:SF 0 "register_operand" "=r") | |
| 846 (lo_sum:SF (match_operand:SF 1 "register_operand" "r") | |
| 847 (match_operand:SF 2 "const_double_operand" "")))] | |
| 848 "" | |
| 849 "* | |
| 850 { | |
| 851 REAL_VALUE_TYPE r; | |
| 852 long i; | |
| 853 | |
| 854 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[2]); | |
| 855 REAL_VALUE_TO_TARGET_SINGLE (r, i); | |
| 856 operands[2] = GEN_INT (i); | |
| 857 return \"addiu\\t%0,%1,%%lo(%2) # low\"; | |
| 858 }" | |
| 859 [(set_attr "length" "4") | |
| 860 (set_attr "type" "arith")]) | |
| 861 | |
| 862 (define_insn "movsf_high" | |
| 863 [(set (match_operand:SF 0 "register_operand" "=r") | |
| 864 (high:SF (match_operand:SF 1 "const_double_operand" "")))] | |
| 865 "" | |
| 866 "* | |
| 867 { | |
| 868 REAL_VALUE_TYPE r; | |
| 869 long i; | |
| 870 | |
| 871 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]); | |
| 872 REAL_VALUE_TO_TARGET_SINGLE (r, i); | |
| 873 operands[1] = GEN_INT (i); | |
| 874 return \"lui\\t%0,%%hi(%1) # high\"; | |
| 875 }" | |
| 876 [(set_attr "length" "4") | |
| 877 (set_attr "type" "arith")]) | |
| 878 | |
| 879 (define_insn "*movsf_internal" | |
| 880 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m") | |
| 881 (match_operand:SF 1 "nonimmediate_operand" "r,m,r"))] | |
| 882 "!memory_operand (operands[0], SFmode) || !memory_operand (operands[1], SFmode)" | |
| 883 "* | |
| 884 { | |
| 885 iq2000_fill_delay_slot (\"\", DELAY_LOAD, operands, insn); | |
| 886 if (which_alternative == 0) | |
| 887 return \"or\\t%0,%1,%1\"; | |
| 888 else if (which_alternative == 1) | |
| 889 return \"lw\\t%0,%1\"; | |
| 890 else if (which_alternative == 2) | |
| 891 return \"sw\\t%1,%0\"; | |
| 892 }" | |
| 893 [(set_attr "length" "4,4,4") | |
| 894 (set_attr "type" "arith,load,store")] | |
| 895 ) | |
| 896 | |
| 897 ;; | |
| 898 ;; .................... | |
| 899 ;; | |
| 900 ;; SHIFTS | |
| 901 ;; | |
| 902 ;; .................... | |
| 903 | |
| 904 (define_expand "ashlsi3" | |
| 905 [(set (match_operand:SI 0 "register_operand" "=d") | |
| 906 (ashift:SI (match_operand:SI 1 "register_operand" "d") | |
| 907 (match_operand:SI 2 "arith_operand" "dI")))] | |
| 908 "" | |
| 909 "") | |
| 910 | |
| 911 (define_insn "ashlsi3_internal1" | |
| 912 [(set (match_operand:SI 0 "register_operand" "=d") | |
| 913 (ashift:SI (match_operand:SI 1 "register_operand" "d") | |
| 914 (match_operand:SI 2 "arith_operand" "dI")))] | |
| 915 "" | |
| 916 "* | |
| 917 { | |
| 918 if (GET_CODE (operands[2]) == CONST_INT) | |
| 919 { | |
| 920 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); | |
| 921 return \"sll\\t%0,%1,%2\"; | |
| 922 } | |
| 923 else | |
| 924 return \"sllv\\t%0,%1,%2\"; | |
| 925 }" | |
| 926 [(set_attr "type" "arith") | |
| 927 (set_attr "mode" "SI")]) | |
| 928 | |
| 929 (define_expand "ashrsi3" | |
| 930 [(set (match_operand:SI 0 "register_operand" "=d") | |
| 931 (ashiftrt:SI (match_operand:SI 1 "register_operand" "d") | |
| 932 (match_operand:SI 2 "arith_operand" "dI")))] | |
| 933 "" | |
| 934 "") | |
| 935 | |
| 936 (define_insn "ashrsi3_internal1" | |
| 937 [(set (match_operand:SI 0 "register_operand" "=d") | |
| 938 (ashiftrt:SI (match_operand:SI 1 "register_operand" "d") | |
| 939 (match_operand:SI 2 "arith_operand" "dI")))] | |
| 940 "" | |
| 941 "* | |
| 942 { | |
| 943 if (GET_CODE (operands[2]) == CONST_INT) | |
| 944 { | |
| 945 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); | |
| 946 return \"sra\\t%0,%1,%2\"; | |
| 947 } | |
| 948 else | |
| 949 return \"srav\\t%0,%1,%2\"; | |
| 950 }" | |
| 951 [(set_attr "type" "arith") | |
| 952 (set_attr "mode" "SI")]) | |
| 953 | |
| 954 (define_expand "lshrsi3" | |
| 955 [(set (match_operand:SI 0 "register_operand" "=d") | |
| 956 (lshiftrt:SI (match_operand:SI 1 "register_operand" "d") | |
| 957 (match_operand:SI 2 "arith_operand" "dI")))] | |
| 958 "" | |
| 959 "") | |
| 960 | |
| 961 (define_insn "lshrsi3_internal1" | |
| 962 [(set (match_operand:SI 0 "register_operand" "=d") | |
| 963 (lshiftrt:SI (match_operand:SI 1 "register_operand" "d") | |
| 964 (match_operand:SI 2 "arith_operand" "dI")))] | |
| 965 "" | |
| 966 "* | |
| 967 { | |
| 968 if (GET_CODE (operands[2]) == CONST_INT) | |
| 969 { | |
| 970 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); | |
| 971 return \"srl\\t%0,%1,%2\"; | |
| 972 } | |
| 973 else | |
| 974 return \"srlv\\t%0,%1,%2\"; | |
| 975 }" | |
| 976 [(set_attr "type" "arith") | |
| 977 (set_attr "mode" "SI")]) | |
| 978 | |
| 979 ;; Rotate Right | |
| 980 (define_insn "rotrsi3" | |
| 981 [(set (match_operand:SI 0 "register_operand" "=r") | |
| 982 (rotatert:SI (match_operand:SI 1 "register_operand" "r") | |
| 983 (match_operand:SI 2 "uns_arith_operand" "O")))] | |
| 984 "" | |
| 985 "ram %0,%1,%2,0x0,0x0" | |
| 986 [(set_attr "type" "arith")]) | |
| 987 | |
| 988 | |
| 989 ;; | |
| 990 ;; .................... | |
| 991 ;; | |
|
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update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
992 ;; CONDITIONAL BRANCHES |
| 0 | 993 ;; |
| 994 ;; .................... | |
| 995 | |
|
55
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
996 (define_expand "cbranchsi4" |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
997 [(set (pc) |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
998 (if_then_else |
|
77e2b8dfacca
update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
0
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999 (match_operator:SI 0 "ordered_comparison_operator" |
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1000 [(match_operand:SI 1 "register_operand") |
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1001 (match_operand:SI 2 "reg_or_const_operand")]) |
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1002 (label_ref (match_operand:SI 3 "")) |
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1003 (pc)))] |
| 0 | 1004 "" |
| 1005 " | |
| 1006 { | |
|
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1007 gen_conditional_branch (operands, SImode); |
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1008 DONE; |
| 0 | 1009 }") |
| 1010 | |
| 1011 | |
| 1012 ;; Conditional branches on comparisons with zero. | |
| 1013 | |
| 1014 (define_insn "branch_zero" | |
| 1015 [(set (pc) | |
| 1016 (if_then_else | |
| 1017 (match_operator:SI 0 "cmp_op" | |
| 1018 [(match_operand:SI 2 "register_operand" "d") | |
| 1019 (const_int 0)]) | |
| 1020 (label_ref (match_operand 1 "" "")) | |
| 1021 (pc)))] | |
| 1022 "" | |
| 1023 "* | |
| 1024 { | |
| 1025 return iq2000_output_conditional_branch (insn, | |
| 1026 operands, | |
| 1027 /*two_operands_p=*/0, | |
| 1028 /*float_p=*/0, | |
| 1029 /*inverted_p=*/0, | |
| 1030 get_attr_length (insn)); | |
| 1031 }" | |
| 1032 [(set_attr "type" "branch") | |
| 1033 (set_attr "mode" "none")]) | |
| 1034 | |
| 1035 (define_insn "branch_zero_inverted" | |
| 1036 [(set (pc) | |
| 1037 (if_then_else | |
| 1038 (match_operator:SI 0 "cmp_op" | |
| 1039 [(match_operand:SI 2 "register_operand" "d") | |
| 1040 (const_int 0)]) | |
| 1041 (pc) | |
| 1042 (label_ref (match_operand 1 "" ""))))] | |
| 1043 "" | |
| 1044 "* | |
| 1045 { | |
| 1046 return iq2000_output_conditional_branch (insn, | |
| 1047 operands, | |
| 1048 /*two_operands_p=*/0, | |
| 1049 /*float_p=*/0, | |
| 1050 /*inverted_p=*/1, | |
| 1051 get_attr_length (insn)); | |
| 1052 }" | |
| 1053 [(set_attr "type" "branch") | |
| 1054 (set_attr "mode" "none")]) | |
| 1055 | |
| 1056 ;; Conditional branch on equality comparison. | |
| 1057 | |
| 1058 (define_insn "branch_equality" | |
| 1059 [(set (pc) | |
| 1060 (if_then_else | |
| 1061 (match_operator:SI 0 "equality_op" | |
| 1062 [(match_operand:SI 2 "register_operand" "d") | |
| 1063 (match_operand:SI 3 "register_operand" "d")]) | |
| 1064 (label_ref (match_operand 1 "" "")) | |
| 1065 (pc)))] | |
| 1066 "" | |
| 1067 "* | |
| 1068 { | |
| 1069 return iq2000_output_conditional_branch (insn, | |
| 1070 operands, | |
| 1071 /*two_operands_p=*/1, | |
| 1072 /*float_p=*/0, | |
| 1073 /*inverted_p=*/0, | |
| 1074 get_attr_length (insn)); | |
| 1075 }" | |
| 1076 [(set_attr "type" "branch") | |
| 1077 (set_attr "mode" "none")]) | |
| 1078 | |
| 1079 (define_insn "branch_equality_inverted" | |
| 1080 [(set (pc) | |
| 1081 (if_then_else | |
| 1082 (match_operator:SI 0 "equality_op" | |
| 1083 [(match_operand:SI 2 "register_operand" "d") | |
| 1084 (match_operand:SI 3 "register_operand" "d")]) | |
| 1085 (pc) | |
| 1086 (label_ref (match_operand 1 "" ""))))] | |
| 1087 "" | |
| 1088 "* | |
| 1089 { | |
| 1090 return iq2000_output_conditional_branch (insn, | |
| 1091 operands, | |
| 1092 /*two_operands_p=*/1, | |
| 1093 /*float_p=*/0, | |
| 1094 /*inverted_p=*/1, | |
| 1095 get_attr_length (insn)); | |
| 1096 }" | |
| 1097 [(set_attr "type" "branch") | |
| 1098 (set_attr "mode" "none")]) | |
| 1099 | |
| 1100 | |
| 1101 ;; Recognize bbi and bbin instructions. These use two unusual template | |
| 1102 ;; patterns, %Ax and %Px. %Ax outputs an 'i' if operand `x' is a LABEL_REF | |
| 1103 ;; otherwise it outputs an 'in'. %Px does nothing if `x' is PC | |
| 1104 ;; and outputs the operand if `x' is a LABEL_REF. | |
| 1105 | |
| 1106 (define_insn "" | |
| 1107 [(set (pc) | |
| 1108 (if_then_else | |
| 1109 (ne (sign_extract:SI (match_operand:SI 0 "register_operand" "r") | |
| 1110 (const_int 1) | |
| 1111 (match_operand:SI 1 "arith_operand" "I")) | |
| 1112 (const_int 0)) | |
| 1113 (match_operand 2 "pc_or_label_operand" "") | |
| 1114 (match_operand 3 "pc_or_label_operand" "")))] | |
| 1115 "" | |
| 1116 "bb%A2\\t%0(31-%1),%P2%P3" | |
| 1117 [(set_attr "length" "4") | |
| 1118 (set_attr "type" "branch")]) | |
| 1119 | |
| 1120 (define_insn "" | |
| 1121 [(set (pc) | |
| 1122 (if_then_else | |
| 1123 (eq (sign_extract:SI (match_operand:SI 0 "register_operand" "r") | |
| 1124 (const_int 1) | |
| 1125 (match_operand:SI 1 "arith_operand" "I")) | |
| 1126 (const_int 0)) | |
| 1127 (match_operand 2 "pc_or_label_operand" "") | |
| 1128 (match_operand 3 "pc_or_label_operand" "")))] | |
| 1129 "" | |
| 1130 "bb%A3\\t%0(31-%1),%P2%P3" | |
| 1131 [(set_attr "length" "4") | |
| 1132 (set_attr "type" "branch")]) | |
| 1133 | |
| 1134 (define_insn "" | |
| 1135 [(set (pc) | |
| 1136 (if_then_else | |
| 1137 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r") | |
| 1138 (const_int 1) | |
| 1139 (match_operand:SI 1 "arith_operand" "I")) | |
| 1140 (const_int 0)) | |
| 1141 (match_operand 2 "pc_or_label_operand" "") | |
| 1142 (match_operand 3 "pc_or_label_operand" "")))] | |
| 1143 "" | |
| 1144 "bb%A2\\t%0(31-%1),%P2%P3" | |
| 1145 [(set_attr "length" "4") | |
| 1146 (set_attr "type" "branch")]) | |
| 1147 | |
| 1148 (define_insn "" | |
| 1149 [(set (pc) | |
| 1150 (if_then_else | |
| 1151 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r") | |
| 1152 (const_int 1) | |
| 1153 (match_operand:SI 1 "arith_operand" "I")) | |
| 1154 (const_int 0)) | |
| 1155 (match_operand 2 "pc_or_label_operand" "") | |
| 1156 (match_operand 3 "pc_or_label_operand" "")))] | |
| 1157 "" | |
| 1158 "bb%A3\\t%0(31-%1),%P2%P3" | |
| 1159 [(set_attr "length" "4") | |
| 1160 (set_attr "type" "branch")]) | |
| 1161 | |
| 1162 (define_insn "" | |
| 1163 [(set (pc) | |
| 1164 (if_then_else | |
| 1165 (eq (and:SI (match_operand:SI 0 "register_operand" "r") | |
| 1166 (match_operand:SI 1 "power_of_2_operand" "I")) | |
| 1167 (const_int 0)) | |
| 1168 (match_operand 2 "pc_or_label_operand" "") | |
| 1169 (match_operand 3 "pc_or_label_operand" "")))] | |
| 1170 "" | |
| 1171 "bb%A3\\t%0(%p1),%P2%P3" | |
| 1172 [(set_attr "length" "4") | |
| 1173 (set_attr "type" "branch")]) | |
| 1174 | |
| 1175 (define_insn "" | |
| 1176 [(set (pc) | |
| 1177 (if_then_else | |
| 1178 (ne (and:SI (match_operand:SI 0 "register_operand" "r") | |
| 1179 (match_operand:SI 1 "power_of_2_operand" "I")) | |
| 1180 (const_int 0)) | |
| 1181 (match_operand 2 "pc_or_label_operand" "") | |
| 1182 (match_operand 3 "pc_or_label_operand" "")))] | |
| 1183 "" | |
| 1184 "bb%A2\\t%0(%p1),%P2%P3" | |
| 1185 [(set_attr "length" "4") | |
| 1186 (set_attr "type" "branch")]) | |
| 1187 | |
| 1188 ;; | |
| 1189 ;; .................... | |
| 1190 ;; | |
| 1191 ;; SETTING A REGISTER FROM A COMPARISON | |
| 1192 ;; | |
| 1193 ;; .................... | |
| 1194 | |
|
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1195 (define_expand "cstoresi4" |
| 0 | 1196 [(set (match_operand:SI 0 "register_operand" "=d") |
|
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1197 (match_operator:SI 1 "ordered_comparison_operator" |
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1198 [(match_operand:SI 2 "register_operand") |
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1199 (match_operand:SI 3 "reg_or_const_operand")]))] |
| 0 | 1200 "" |
| 1201 " | |
| 1202 { | |
|
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1203 gen_int_relational (GET_CODE (operands[1]), operands[0], |
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1204 operands[2], operands[3], (int *)0); |
| 0 | 1205 DONE; |
| 1206 }") | |
| 1207 | |
| 1208 (define_insn "seq_si_zero" | |
| 1209 [(set (match_operand:SI 0 "register_operand" "=d") | |
| 1210 (eq:SI (match_operand:SI 1 "register_operand" "d") | |
| 1211 (const_int 0)))] | |
| 1212 "" | |
| 1213 "sltiu\\t%0,%1,1" | |
| 1214 [(set_attr "type" "arith") | |
| 1215 (set_attr "mode" "SI")]) | |
| 1216 | |
| 1217 (define_insn "sne_si_zero" | |
| 1218 [(set (match_operand:SI 0 "register_operand" "=d") | |
| 1219 (ne:SI (match_operand:SI 1 "register_operand" "d") | |
| 1220 (const_int 0)))] | |
| 1221 "" | |
| 1222 "sltu\\t%0,%.,%1" | |
| 1223 [(set_attr "type" "arith") | |
| 1224 (set_attr "mode" "SI")]) | |
| 1225 | |
| 1226 (define_insn "sgt_si" | |
| 1227 [(set (match_operand:SI 0 "register_operand" "=d,=d") | |
| 1228 (gt:SI (match_operand:SI 1 "register_operand" "d,d") | |
| 1229 (match_operand:SI 2 "reg_or_0_operand" "d,J")))] | |
| 1230 "" | |
| 1231 "@ | |
| 1232 slt\\t%0,%z2,%1 | |
| 1233 slt\\t%0,%z2,%1" | |
| 1234 [(set_attr "type" "arith,arith") | |
| 1235 (set_attr "mode" "SI,SI")]) | |
| 1236 | |
| 1237 (define_insn "slt_si" | |
| 1238 [(set (match_operand:SI 0 "register_operand" "=d,=d") | |
| 1239 (lt:SI (match_operand:SI 1 "register_operand" "d,d") | |
| 1240 (match_operand:SI 2 "arith_operand" "d,I")))] | |
| 1241 "" | |
| 1242 "@ | |
| 1243 slt\\t%0,%1,%2 | |
| 1244 slti\\t%0,%1,%2" | |
| 1245 [(set_attr "type" "arith,arith") | |
| 1246 (set_attr "mode" "SI,SI")]) | |
| 1247 | |
| 1248 (define_insn "sle_si_const" | |
| 1249 [(set (match_operand:SI 0 "register_operand" "=d") | |
| 1250 (le:SI (match_operand:SI 1 "register_operand" "d") | |
| 1251 (match_operand:SI 2 "small_int" "I")))] | |
| 1252 "INTVAL (operands[2]) < 32767" | |
| 1253 "* | |
| 1254 { | |
| 1255 operands[2] = GEN_INT (INTVAL (operands[2])+1); | |
| 1256 return \"slti\\t%0,%1,%2\"; | |
| 1257 }" | |
| 1258 [(set_attr "type" "arith") | |
| 1259 (set_attr "mode" "SI")]) | |
| 1260 | |
| 1261 (define_insn "sgtu_si" | |
| 1262 [(set (match_operand:SI 0 "register_operand" "=d") | |
| 1263 (gtu:SI (match_operand:SI 1 "register_operand" "d") | |
| 1264 (match_operand:SI 2 "reg_or_0_operand" "dJ")))] | |
| 1265 "" | |
| 1266 "sltu\\t%0,%z2,%1" | |
| 1267 [(set_attr "type" "arith") | |
| 1268 (set_attr "mode" "SI")]) | |
| 1269 | |
| 1270 (define_insn "" | |
| 1271 [(set (match_operand:SI 0 "register_operand" "=t") | |
| 1272 (gtu:SI (match_operand:SI 1 "register_operand" "d") | |
| 1273 (match_operand:SI 2 "register_operand" "d")))] | |
| 1274 "" | |
| 1275 "sltu\\t%2,%1" | |
| 1276 [(set_attr "type" "arith") | |
| 1277 (set_attr "mode" "SI")]) | |
| 1278 | |
| 1279 (define_insn "sltu_si" | |
| 1280 [(set (match_operand:SI 0 "register_operand" "=d,=d") | |
| 1281 (ltu:SI (match_operand:SI 1 "register_operand" "d,d") | |
| 1282 (match_operand:SI 2 "arith_operand" "d,I")))] | |
| 1283 "" | |
| 1284 "@ | |
| 1285 sltu\\t%0,%1,%2 | |
| 1286 sltiu\\t%0,%1,%2" | |
| 1287 [(set_attr "type" "arith,arith") | |
| 1288 (set_attr "mode" "SI,SI")]) | |
| 1289 | |
| 1290 (define_insn "sleu_si_const" | |
| 1291 [(set (match_operand:SI 0 "register_operand" "=d") | |
| 1292 (leu:SI (match_operand:SI 1 "register_operand" "d") | |
| 1293 (match_operand:SI 2 "small_int" "I")))] | |
| 1294 "INTVAL (operands[2]) < 32767" | |
| 1295 "* | |
| 1296 { | |
| 1297 operands[2] = GEN_INT (INTVAL (operands[2]) + 1); | |
| 1298 return \"sltiu\\t%0,%1,%2\"; | |
| 1299 }" | |
| 1300 [(set_attr "type" "arith") | |
| 1301 (set_attr "mode" "SI")]) | |
| 1302 | |
| 1303 | |
| 1304 ;; | |
| 1305 ;; .................... | |
| 1306 ;; | |
| 1307 ;; UNCONDITIONAL BRANCHES | |
| 1308 ;; | |
| 1309 ;; .................... | |
| 1310 | |
| 1311 ;; Unconditional branches. | |
| 1312 | |
| 1313 (define_insn "jump" | |
| 1314 [(set (pc) | |
| 1315 (label_ref (match_operand 0 "" "")))] | |
| 1316 "" | |
| 1317 "* | |
| 1318 { | |
| 1319 if (GET_CODE (operands[0]) == REG) | |
| 1320 return \"j\\t%0\"; | |
| 1321 return \"j\\t%l0\"; | |
| 1322 /* return \"b\\t%l0\";*/ | |
| 1323 }" | |
| 1324 [(set_attr "type" "jump") | |
| 1325 (set_attr "mode" "none")]) | |
| 1326 | |
| 1327 (define_expand "indirect_jump" | |
| 1328 [(set (pc) (match_operand 0 "register_operand" "d"))] | |
| 1329 "" | |
| 1330 " | |
| 1331 { | |
| 1332 rtx dest; | |
| 1333 | |
| 1334 if (operands[0]) /* eliminate unused code warnings */ | |
| 1335 { | |
| 1336 dest = operands[0]; | |
| 1337 if (GET_CODE (dest) != REG || GET_MODE (dest) != Pmode) | |
| 1338 operands[0] = copy_to_mode_reg (Pmode, dest); | |
| 1339 | |
| 1340 if (!(Pmode == DImode)) | |
| 1341 emit_jump_insn (gen_indirect_jump_internal1 (operands[0])); | |
| 1342 else | |
| 1343 emit_jump_insn (gen_indirect_jump_internal2 (operands[0])); | |
| 1344 | |
| 1345 DONE; | |
| 1346 } | |
| 1347 }") | |
| 1348 | |
| 1349 (define_insn "indirect_jump_internal1" | |
| 1350 [(set (pc) (match_operand:SI 0 "register_operand" "d"))] | |
| 1351 "!(Pmode == DImode)" | |
| 1352 "j\\t%0" | |
| 1353 [(set_attr "type" "jump") | |
| 1354 (set_attr "mode" "none")]) | |
| 1355 | |
| 1356 (define_expand "tablejump" | |
| 1357 [(set (pc) | |
| 1358 (match_operand 0 "register_operand" "d")) | |
| 1359 (use (label_ref (match_operand 1 "" "")))] | |
| 1360 "" | |
| 1361 " | |
| 1362 { | |
| 1363 if (operands[0]) /* eliminate unused code warnings */ | |
| 1364 { | |
| 1365 gcc_assert (GET_MODE (operands[0]) == Pmode); | |
| 1366 | |
| 1367 if (!(Pmode == DImode)) | |
| 1368 emit_jump_insn (gen_tablejump_internal1 (operands[0], operands[1])); | |
| 1369 else | |
| 1370 emit_jump_insn (gen_tablejump_internal2 (operands[0], operands[1])); | |
| 1371 | |
| 1372 DONE; | |
| 1373 } | |
| 1374 }") | |
| 1375 | |
| 1376 (define_insn "tablejump_internal1" | |
| 1377 [(set (pc) | |
| 1378 (match_operand:SI 0 "register_operand" "d")) | |
| 1379 (use (label_ref (match_operand 1 "" "")))] | |
| 1380 "!(Pmode == DImode)" | |
| 1381 "j\\t%0" | |
| 1382 [(set_attr "type" "jump") | |
| 1383 (set_attr "mode" "none")]) | |
| 1384 | |
| 1385 (define_expand "tablejump_internal3" | |
| 1386 [(parallel [(set (pc) | |
| 1387 (plus:SI (match_operand:SI 0 "register_operand" "d") | |
| 1388 (label_ref:SI (match_operand 1 "" "")))) | |
| 1389 (use (label_ref:SI (match_dup 1)))])] | |
| 1390 "" | |
| 1391 "") | |
| 1392 | |
| 1393 ;;; Make sure that this only matches the insn before ADDR_DIFF_VEC. Otherwise | |
| 1394 ;;; it is not valid. ??? With the USE, the condition tests may not be required | |
| 1395 ;;; any longer. | |
| 1396 | |
| 1397 ;;; ??? The length depends on the ABI. It is two for o32, and one for n32. | |
| 1398 ;;; We just use the conservative number here. | |
| 1399 | |
| 1400 (define_insn "" | |
| 1401 [(set (pc) | |
| 1402 (plus:SI (match_operand:SI 0 "register_operand" "d") | |
| 1403 (label_ref:SI (match_operand 1 "" "")))) | |
| 1404 (use (label_ref:SI (match_dup 1)))] | |
| 1405 "!(Pmode == DImode) && next_active_insn (insn) != 0 | |
| 1406 && GET_CODE (PATTERN (next_active_insn (insn))) == ADDR_DIFF_VEC | |
| 1407 && PREV_INSN (next_active_insn (insn)) == operands[1]" | |
| 1408 "* | |
| 1409 { | |
| 1410 return \"j\\t%0\"; | |
| 1411 }" | |
| 1412 [(set_attr "type" "jump") | |
| 1413 (set_attr "mode" "none") | |
| 1414 (set_attr "length" "8")]) | |
| 1415 | |
| 1416 ;; | |
| 1417 ;; .................... | |
| 1418 ;; | |
| 1419 ;; Function prologue/epilogue | |
| 1420 ;; | |
| 1421 ;; .................... | |
| 1422 ;; | |
| 1423 | |
| 1424 (define_expand "prologue" | |
| 1425 [(const_int 1)] | |
| 1426 "" | |
| 1427 " | |
| 1428 { | |
| 1429 if (iq2000_isa >= 0) /* avoid unused code warnings */ | |
| 1430 { | |
| 1431 iq2000_expand_prologue (); | |
| 1432 DONE; | |
| 1433 } | |
| 1434 }") | |
| 1435 | |
| 1436 ;; Block any insns from being moved before this point, since the | |
| 1437 ;; profiling call to mcount can use various registers that aren't | |
| 1438 ;; saved or used to pass arguments. | |
| 1439 | |
| 1440 (define_insn "blockage" | |
| 1441 [(unspec_volatile [(const_int 0)] 0)] | |
| 1442 "" | |
| 1443 "" | |
| 1444 [(set_attr "type" "unknown") | |
| 1445 (set_attr "mode" "none") | |
| 1446 (set_attr "length" "0")]) | |
| 1447 | |
| 1448 (define_expand "epilogue" | |
| 1449 [(const_int 2)] | |
| 1450 "" | |
| 1451 " | |
| 1452 { | |
| 1453 if (iq2000_isa >= 0) /* avoid unused code warnings */ | |
| 1454 { | |
| 1455 iq2000_expand_epilogue (); | |
| 1456 DONE; | |
| 1457 } | |
| 1458 }") | |
| 1459 | |
| 1460 ;; Trivial return. Make it look like a normal return insn as that | |
| 1461 ;; allows jump optimizations to work better . | |
| 1462 (define_insn "return" | |
| 1463 [(return)] | |
| 1464 "iq2000_can_use_return_insn ()" | |
| 1465 "j\\t%%31" | |
| 1466 [(set_attr "type" "jump") | |
| 1467 (set_attr "mode" "none")]) | |
| 1468 | |
| 1469 ;; Normal return. | |
| 1470 | |
| 1471 (define_insn "return_internal" | |
| 1472 [(use (match_operand 0 "pmode_register_operand" "")) | |
| 1473 (return)] | |
| 1474 "" | |
| 1475 "* | |
| 1476 { | |
| 1477 return \"j\\t%0\"; | |
| 1478 }" | |
| 1479 [(set_attr "type" "jump") | |
| 1480 (set_attr "mode" "none")]) | |
| 1481 | |
| 1482 (define_insn "eh_return_internal" | |
| 1483 [(const_int 4) | |
| 1484 (return) | |
| 1485 (use (reg:SI 26)) | |
| 1486 (use (reg:SI 31))] | |
| 1487 "" | |
| 1488 "j\\t%%26" | |
| 1489 [(set_attr "type" "jump") | |
| 1490 (set_attr "mode" "none")]) | |
| 1491 | |
| 1492 (define_expand "eh_return" | |
| 1493 [(use (match_operand:SI 0 "register_operand" "r"))] | |
| 1494 "" | |
| 1495 " | |
| 1496 { | |
| 1497 iq2000_expand_eh_return (operands[0]); | |
| 1498 DONE; | |
| 1499 }") | |
| 1500 | |
| 1501 | |
| 1502 ;; | |
| 1503 ;; .................... | |
| 1504 ;; | |
| 1505 ;; FUNCTION CALLS | |
| 1506 ;; | |
| 1507 ;; .................... | |
| 1508 | |
| 1509 ;; calls.c now passes a third argument, make saber happy | |
| 1510 | |
| 1511 (define_expand "call" | |
| 1512 [(parallel [(call (match_operand 0 "memory_operand" "m") | |
| 1513 (match_operand 1 "" "i")) | |
| 1514 (clobber (reg:SI 31)) | |
| 1515 (use (match_operand 2 "" "")) ;; next_arg_reg | |
| 1516 (use (match_operand 3 "" ""))])] ;; struct_value_size_rtx | |
| 1517 "" | |
| 1518 " | |
| 1519 { | |
| 1520 rtx addr; | |
| 1521 | |
| 1522 if (operands[0]) /* eliminate unused code warnings */ | |
| 1523 { | |
| 1524 addr = XEXP (operands[0], 0); | |
| 1525 if ((GET_CODE (addr) != REG && (!CONSTANT_ADDRESS_P (addr))) | |
| 1526 || ! call_insn_operand (addr, VOIDmode)) | |
| 1527 XEXP (operands[0], 0) = copy_to_mode_reg (Pmode, addr); | |
| 1528 | |
| 1529 /* In order to pass small structures by value in registers | |
| 1530 compatibly with the IQ2000 compiler, we need to shift the value | |
| 1531 into the high part of the register. Function_arg has encoded | |
| 1532 a PARALLEL rtx, holding a vector of adjustments to be made | |
| 1533 as the next_arg_reg variable, so we split up the insns, | |
| 1534 and emit them separately. */ | |
| 1535 | |
| 1536 if (operands[2] != (rtx)0 && GET_CODE (operands[2]) == PARALLEL) | |
| 1537 { | |
| 1538 rtvec adjust = XVEC (operands[2], 0); | |
| 1539 int num = GET_NUM_ELEM (adjust); | |
| 1540 int i; | |
| 1541 | |
| 1542 for (i = 0; i < num; i++) | |
| 1543 emit_insn (RTVEC_ELT (adjust, i)); | |
| 1544 } | |
| 1545 | |
| 1546 emit_call_insn (gen_call_internal0 (operands[0], operands[1], | |
| 1547 gen_rtx_REG (SImode, | |
| 1548 GP_REG_FIRST + 31))); | |
| 1549 DONE; | |
| 1550 } | |
| 1551 }") | |
| 1552 | |
| 1553 (define_expand "call_internal0" | |
| 1554 [(parallel [(call (match_operand 0 "" "") | |
| 1555 (match_operand 1 "" "")) | |
| 1556 (clobber (match_operand:SI 2 "" ""))])] | |
| 1557 "" | |
| 1558 "") | |
| 1559 | |
| 1560 (define_insn "call_internal1" | |
| 1561 [(call (mem (match_operand 0 "call_insn_operand" "ri")) | |
| 1562 (match_operand 1 "" "i")) | |
| 1563 (clobber (match_operand:SI 2 "register_operand" "=d"))] | |
| 1564 "" | |
| 1565 "* | |
| 1566 { | |
| 1567 register rtx target = operands[0]; | |
| 1568 | |
| 1569 if (GET_CODE (target) == CONST_INT) | |
| 1570 return \"li\\t%@,%0\\n\\tjalr\\t%2,%@\"; | |
| 1571 else if (CONSTANT_ADDRESS_P (target)) | |
| 1572 return \"jal\\t%0\"; | |
| 1573 else | |
| 1574 return \"jalr\\t%2,%0\"; | |
| 1575 }" | |
| 1576 [(set_attr "type" "call") | |
| 1577 (set_attr "mode" "none")]) | |
| 1578 | |
| 1579 ;; calls.c now passes a fourth argument, make saber happy | |
| 1580 | |
| 1581 (define_expand "call_value" | |
| 1582 [(parallel [(set (match_operand 0 "register_operand" "=df") | |
| 1583 (call (match_operand 1 "memory_operand" "m") | |
| 1584 (match_operand 2 "" "i"))) | |
| 1585 (clobber (reg:SI 31)) | |
| 1586 (use (match_operand 3 "" ""))])] ;; next_arg_reg | |
| 1587 "" | |
| 1588 " | |
| 1589 { | |
| 1590 rtx addr; | |
| 1591 | |
| 1592 if (operands[0]) /* eliminate unused code warning */ | |
| 1593 { | |
| 1594 addr = XEXP (operands[1], 0); | |
| 1595 if ((GET_CODE (addr) != REG && (!CONSTANT_ADDRESS_P (addr))) | |
| 1596 || ! call_insn_operand (addr, VOIDmode)) | |
| 1597 XEXP (operands[1], 0) = copy_to_mode_reg (Pmode, addr); | |
| 1598 | |
| 1599 /* In order to pass small structures by value in registers | |
| 1600 compatibly with the IQ2000 compiler, we need to shift the value | |
| 1601 into the high part of the register. Function_arg has encoded | |
| 1602 a PARALLEL rtx, holding a vector of adjustments to be made | |
| 1603 as the next_arg_reg variable, so we split up the insns, | |
| 1604 and emit them separately. */ | |
| 1605 | |
| 1606 if (operands[3] != (rtx)0 && GET_CODE (operands[3]) == PARALLEL) | |
| 1607 { | |
| 1608 rtvec adjust = XVEC (operands[3], 0); | |
| 1609 int num = GET_NUM_ELEM (adjust); | |
| 1610 int i; | |
| 1611 | |
| 1612 for (i = 0; i < num; i++) | |
| 1613 emit_insn (RTVEC_ELT (adjust, i)); | |
| 1614 } | |
| 1615 | |
| 1616 if (GET_CODE (operands[0]) == PARALLEL && XVECLEN (operands[0], 0) > 1) | |
| 1617 { | |
| 1618 emit_call_insn (gen_call_value_multiple_internal0 | |
| 1619 (XEXP (XVECEXP (operands[0], 0, 0), 0), | |
| 1620 operands[1], operands[2], | |
| 1621 XEXP (XVECEXP (operands[0], 0, 1), 0), | |
| 1622 gen_rtx_REG (SImode, GP_REG_FIRST + 31))); | |
| 1623 DONE; | |
| 1624 } | |
| 1625 | |
| 1626 /* We have a call returning a DImode structure in an FP reg. | |
| 1627 Strip off the now unnecessary PARALLEL. */ | |
| 1628 if (GET_CODE (operands[0]) == PARALLEL) | |
| 1629 operands[0] = XEXP (XVECEXP (operands[0], 0, 0), 0); | |
| 1630 | |
| 1631 emit_call_insn (gen_call_value_internal0 (operands[0], operands[1], operands[2], | |
| 1632 gen_rtx_REG (SImode, | |
| 1633 GP_REG_FIRST + 31))); | |
| 1634 | |
| 1635 DONE; | |
| 1636 } | |
| 1637 }") | |
| 1638 | |
| 1639 (define_expand "call_value_internal0" | |
| 1640 [(parallel [(set (match_operand 0 "" "") | |
| 1641 (call (match_operand 1 "" "") | |
| 1642 (match_operand 2 "" ""))) | |
| 1643 (clobber (match_operand:SI 3 "" ""))])] | |
| 1644 "" | |
| 1645 "") | |
| 1646 | |
| 1647 (define_insn "call_value_internal1" | |
| 1648 [(set (match_operand 0 "register_operand" "=df") | |
| 1649 (call (mem (match_operand 1 "call_insn_operand" "ri")) | |
| 1650 (match_operand 2 "" "i"))) | |
| 1651 (clobber (match_operand:SI 3 "register_operand" "=d"))] | |
| 1652 "" | |
| 1653 "* | |
| 1654 { | |
| 1655 register rtx target = operands[1]; | |
| 1656 | |
| 1657 if (GET_CODE (target) == CONST_INT) | |
| 1658 return \"li\\t%@,%1\\n\\tjalr\\t%3,%@\"; | |
| 1659 else if (CONSTANT_ADDRESS_P (target)) | |
| 1660 return \"jal\\t%1\"; | |
| 1661 else | |
| 1662 return \"jalr\\t%3,%1\"; | |
| 1663 }" | |
| 1664 [(set_attr "type" "call") | |
| 1665 (set_attr "mode" "none")]) | |
| 1666 | |
| 1667 (define_expand "call_value_multiple_internal0" | |
| 1668 [(parallel [(set (match_operand 0 "" "") | |
| 1669 (call (match_operand 1 "" "") | |
| 1670 (match_operand 2 "" ""))) | |
| 1671 (set (match_operand 3 "" "") | |
| 1672 (call (match_dup 1) | |
| 1673 (match_dup 2))) | |
| 1674 (clobber (match_operand:SI 4 "" ""))])] | |
| 1675 "" | |
| 1676 "") | |
| 1677 | |
| 1678 ;; ??? May eventually need all 6 versions of the call patterns with multiple | |
| 1679 ;; return values. | |
| 1680 | |
| 1681 (define_insn "call_value_multiple_internal1" | |
| 1682 [(set (match_operand 0 "register_operand" "=df") | |
| 1683 (call (mem (match_operand 1 "call_insn_operand" "ri")) | |
| 1684 (match_operand 2 "" "i"))) | |
| 1685 (set (match_operand 3 "register_operand" "=df") | |
| 1686 (call (mem (match_dup 1)) | |
| 1687 (match_dup 2))) | |
| 1688 (clobber (match_operand:SI 4 "register_operand" "=d"))] | |
| 1689 "" | |
| 1690 "* | |
| 1691 { | |
| 1692 register rtx target = operands[1]; | |
| 1693 | |
| 1694 if (GET_CODE (target) == CONST_INT) | |
| 1695 return \"li\\t%@,%1\\n\\tjalr\\t%4,%@\"; | |
| 1696 else if (CONSTANT_ADDRESS_P (target)) | |
| 1697 return \"jal\\t%1\"; | |
| 1698 else | |
| 1699 return \"jalr\\t%4,%1\"; | |
| 1700 }" | |
| 1701 [(set_attr "type" "call") | |
| 1702 (set_attr "mode" "none")]) | |
| 1703 | |
| 1704 ;; Call subroutine returning any type. | |
| 1705 | |
| 1706 (define_expand "untyped_call" | |
| 1707 [(parallel [(call (match_operand 0 "" "") | |
| 1708 (const_int 0)) | |
| 1709 (match_operand 1 "" "") | |
| 1710 (match_operand 2 "" "")])] | |
| 1711 "" | |
| 1712 " | |
| 1713 { | |
| 1714 if (operands[0]) /* silence statement not reached warnings */ | |
| 1715 { | |
| 1716 int i; | |
| 1717 | |
| 1718 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx)); | |
| 1719 | |
| 1720 for (i = 0; i < XVECLEN (operands[2], 0); i++) | |
| 1721 { | |
| 1722 rtx set = XVECEXP (operands[2], 0, i); | |
| 1723 emit_move_insn (SET_DEST (set), SET_SRC (set)); | |
| 1724 } | |
| 1725 | |
| 1726 emit_insn (gen_blockage ()); | |
| 1727 DONE; | |
| 1728 } | |
| 1729 }") | |
| 1730 | |
| 1731 ;; | |
| 1732 ;; .................... | |
| 1733 ;; | |
| 1734 ;; MISC. | |
| 1735 ;; | |
| 1736 ;; .................... | |
| 1737 ;; | |
| 1738 | |
| 1739 (define_insn "nop" | |
| 1740 [(const_int 0)] | |
| 1741 "" | |
| 1742 "nop" | |
| 1743 [(set_attr "type" "nop") | |
| 1744 (set_attr "mode" "none")]) | |
| 1745 | |
| 1746 | |
| 1747 ;; For the rare case where we need to load an address into a register | |
| 1748 ;; that cannot be recognized by the normal movsi/addsi instructions. | |
| 1749 ;; I have no idea how many insns this can actually generate. It should | |
| 1750 ;; be rare, so over-estimating as 10 instructions should not have any | |
| 1751 ;; real performance impact. | |
| 1752 (define_insn "leasi" | |
| 1753 [(set (match_operand:SI 0 "register_operand" "=d") | |
| 1754 (match_operand:SI 1 "address_operand" "p"))] | |
| 1755 "Pmode == SImode" | |
| 1756 "* | |
| 1757 { | |
| 1758 rtx xoperands [3]; | |
| 1759 | |
| 1760 xoperands[0] = operands[0]; | |
| 1761 xoperands[1] = XEXP (operands[1], 0); | |
| 1762 xoperands[2] = XEXP (operands[1], 1); | |
| 1763 output_asm_insn (\"addiu\\t%0,%1,%2\", xoperands); | |
| 1764 return \"\"; | |
| 1765 }" | |
| 1766 [(set_attr "type" "arith") | |
| 1767 (set_attr "mode" "SI") | |
| 1768 (set_attr "length" "40")]) | |
| 1769 | |
| 1770 (define_insn "ado16" | |
| 1771 [(set (match_operand:SI 0 "register_operand" "=r") | |
| 1772 (unspec:SI [(match_operand:SI 1 "register_operand" "r") | |
| 1773 (match_operand:SI 2 "register_operand" "r")] | |
| 1774 UNSPEC_ADO16))] | |
| 1775 "" | |
| 1776 "ado16\\t%0, %1, %2" | |
| 1777 ) | |
| 1778 | |
| 1779 (define_insn "ram" | |
| 1780 [(set (match_operand:SI 0 "register_operand" "=r") | |
| 1781 (unspec:SI [(match_operand:SI 1 "register_operand" "r") | |
| 1782 (match_operand:SI 2 "const_int_operand" "I") | |
| 1783 (match_operand:SI 3 "const_int_operand" "I") | |
| 1784 (match_operand:SI 4 "const_int_operand" "I")] | |
| 1785 UNSPEC_RAM))] | |
| 1786 "" | |
| 1787 "ram\\t%0, %1, %2, %3, %4" | |
| 1788 ) | |
| 1789 | |
| 1790 (define_insn "chkhdr" | |
| 1791 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "=r") | |
| 1792 (match_operand:SI 1 "register_operand" "r")] | |
| 1793 UNSPEC_CHKHDR)] | |
| 1794 "" | |
| 1795 "* return iq2000_fill_delay_slot (\"chkhdr\\t%0, %1\", DELAY_LOAD, operands, insn);" | |
| 1796 [(set_attr "dslot" "not_in_dslot")] | |
| 1797 ) | |
| 1798 | |
| 1799 (define_insn "pkrl" | |
| 1800 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r") | |
| 1801 (match_operand:SI 1 "register_operand" "r")] | |
| 1802 UNSPEC_PKRL)] | |
| 1803 "" | |
| 1804 "* return iq2000_fill_delay_slot (\"pkrl\\t%0, %1\", DELAY_NONE, operands, insn);" | |
| 1805 [(set_attr "dslot" "not_in_dslot")] | |
| 1806 ) | |
| 1807 | |
| 1808 (define_insn "cfc0" | |
| 1809 [(set (match_operand:SI 0 "register_operand" "=r") | |
| 1810 (unspec_volatile:SI [(match_operand:SI 1 "const_int_operand" "I")] | |
| 1811 UNSPEC_CFC0))] | |
| 1812 "" | |
| 1813 "* return iq2000_fill_delay_slot (\"cfc0\\t%0, %%%1\", DELAY_LOAD, operands, insn);" | |
| 1814 [(set_attr "dslot" "ok_in_dslot")] | |
| 1815 ) | |
| 1816 | |
| 1817 (define_insn "cfc1" | |
| 1818 [(set (match_operand:SI 0 "register_operand" "=r") | |
| 1819 (unspec_volatile:SI [(match_operand:SI 1 "const_int_operand" "I")] | |
| 1820 UNSPEC_CFC1))] | |
| 1821 "" | |
| 1822 "* return iq2000_fill_delay_slot (\"cfc1\\t%0, %%%1\", DELAY_LOAD, operands, insn);" | |
| 1823 [(set_attr "dslot" "ok_in_dslot")] | |
| 1824 ) | |
| 1825 | |
| 1826 (define_insn "cfc2" | |
| 1827 [(set (match_operand:SI 0 "register_operand" "=r") | |
| 1828 (unspec_volatile:SI [(match_operand:SI 1 "const_int_operand" "I")] | |
| 1829 UNSPEC_CFC2))] | |
| 1830 "" | |
| 1831 "* return iq2000_fill_delay_slot (\"cfc2\\t%0, %%%1\", DELAY_LOAD, operands, insn);" | |
| 1832 [(set_attr "dslot" "not_in_dslot")] | |
| 1833 ) | |
| 1834 | |
| 1835 (define_insn "cfc3" | |
| 1836 [(set (match_operand:SI 0 "register_operand" "=r") | |
| 1837 (unspec_volatile:SI [(match_operand:SI 1 "const_int_operand" "I")] | |
| 1838 UNSPEC_CFC3))] | |
| 1839 "" | |
| 1840 "* return iq2000_fill_delay_slot (\"cfc3\\t%0, %%%1\", DELAY_LOAD, operands, insn);" | |
| 1841 [(set_attr "dslot" "not_in_dslot")] | |
| 1842 ) | |
| 1843 | |
| 1844 (define_insn "ctc0" | |
| 1845 [(unspec_volatile:SI [(match_operand:SI 0 "reg_or_0_operand" "rJ") | |
| 1846 (match_operand:SI 1 "const_int_operand" "I")] | |
| 1847 UNSPEC_CTC0)] | |
| 1848 "" | |
| 1849 "* return iq2000_fill_delay_slot (\"ctc0\\t%z0, %%%1\", DELAY_NONE, operands, insn);" | |
| 1850 [(set_attr "dslot" "ok_in_dslot")] | |
| 1851 ) | |
| 1852 | |
| 1853 (define_insn "ctc1" | |
| 1854 [(unspec_volatile:SI [(match_operand:SI 0 "reg_or_0_operand" "rJ") | |
| 1855 (match_operand:SI 1 "const_int_operand" "I")] | |
| 1856 UNSPEC_CTC1)] | |
| 1857 "" | |
| 1858 "* return iq2000_fill_delay_slot (\"ctc1\\t%z0, %%%1\", DELAY_NONE, operands, insn);" | |
| 1859 [(set_attr "dslot" "ok_in_dslot")] | |
| 1860 ) | |
| 1861 | |
| 1862 (define_insn "ctc2" | |
| 1863 [(unspec_volatile:SI [(match_operand:SI 0 "reg_or_0_operand" "rJ") | |
| 1864 (match_operand:SI 1 "const_int_operand" "I")] | |
| 1865 UNSPEC_CTC2)] | |
| 1866 "" | |
| 1867 "* return iq2000_fill_delay_slot (\"ctc2\\t%z0, %%%1\", DELAY_NONE, operands, insn);" | |
| 1868 [(set_attr "dslot" "ok_in_dslot")] | |
| 1869 ) | |
| 1870 | |
| 1871 (define_insn "ctc3" | |
| 1872 [(unspec_volatile:SI [(match_operand:SI 0 "reg_or_0_operand" "rJ") | |
| 1873 (match_operand:SI 1 "const_int_operand" "I")] | |
| 1874 UNSPEC_CTC3)] | |
| 1875 "" | |
| 1876 "* return iq2000_fill_delay_slot (\"ctc3\\t%z0, %%%1\", DELAY_NONE, operands, insn);" | |
| 1877 [(set_attr "dslot" "ok_in_dslot")] | |
| 1878 ) | |
| 1879 | |
| 1880 (define_insn "mfc0" | |
| 1881 [(set (match_operand:SI 0 "register_operand" "=r") | |
| 1882 (unspec_volatile:SI [(match_operand:SI 1 "const_int_operand" "I")] | |
| 1883 UNSPEC_MFC0))] | |
| 1884 "" | |
| 1885 "* return iq2000_fill_delay_slot (\"mfc0\\t%0, %%%1\", DELAY_LOAD, operands, insn);" | |
| 1886 [(set_attr "dslot" "ok_in_dslot")] | |
| 1887 ) | |
| 1888 | |
| 1889 (define_insn "mfc1" | |
| 1890 [(set (match_operand:SI 0 "register_operand" "=r") | |
| 1891 (unspec_volatile:SI [(match_operand:SI 1 "const_int_operand" "I")] | |
| 1892 UNSPEC_MFC1))] | |
| 1893 "" | |
| 1894 "* return iq2000_fill_delay_slot (\"mfc1\\t%0, %%%1\", DELAY_LOAD, operands, insn);" | |
| 1895 [(set_attr "dslot" "ok_in_dslot")] | |
| 1896 ) | |
| 1897 | |
| 1898 (define_insn "mfc2" | |
| 1899 [(set (match_operand:SI 0 "register_operand" "=r") | |
| 1900 (unspec_volatile:SI [(match_operand:SI 1 "const_int_operand" "I")] | |
| 1901 UNSPEC_MFC2))] | |
| 1902 "" | |
| 1903 "* return iq2000_fill_delay_slot (\"mfc2\\t%0, %%%1\", DELAY_LOAD, operands, insn);" | |
| 1904 [(set_attr "dslot" "not_in_dslot")] | |
| 1905 ) | |
| 1906 | |
| 1907 (define_insn "mfc3" | |
| 1908 [(set (match_operand:SI 0 "register_operand" "=r") | |
| 1909 (unspec_volatile:SI [(match_operand:SI 1 "const_int_operand" "I")] | |
| 1910 UNSPEC_MFC3))] | |
| 1911 "" | |
| 1912 "* return iq2000_fill_delay_slot (\"mfc3\\t%0, %%%1\", DELAY_LOAD, operands, insn);" | |
| 1913 [(set_attr "dslot" "not_in_dslot")] | |
| 1914 ) | |
| 1915 | |
| 1916 (define_insn "mtc0" | |
| 1917 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r") | |
| 1918 (match_operand:SI 1 "const_int_operand" "I")] | |
| 1919 UNSPEC_MTC0)] | |
| 1920 "" | |
| 1921 "* return iq2000_fill_delay_slot (\"mtc0\\t%0, %%%1\", DELAY_NONE, operands, insn);" | |
| 1922 [(set_attr "dslot" "ok_in_dslot")] | |
| 1923 ) | |
| 1924 | |
| 1925 (define_insn "mtc1" | |
| 1926 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r") | |
| 1927 (match_operand:SI 1 "const_int_operand" "I")] | |
| 1928 UNSPEC_MTC1)] | |
| 1929 "" | |
| 1930 "* return iq2000_fill_delay_slot (\"mtc1\\t%0, %%%1\", DELAY_NONE, operands, insn);" | |
| 1931 [(set_attr "dslot" "ok_in_dslot")] | |
| 1932 ) | |
| 1933 | |
| 1934 (define_insn "mtc2" | |
| 1935 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r") | |
| 1936 (match_operand:SI 1 "const_int_operand" "I")] | |
| 1937 UNSPEC_MTC2)] | |
| 1938 "" | |
| 1939 "* return iq2000_fill_delay_slot (\"mtc2\\t%0, %%%1\", DELAY_NONE, operands, insn);" | |
| 1940 [(set_attr "dslot" "ok_in_dslot")] | |
| 1941 ) | |
| 1942 | |
| 1943 (define_insn "mtc3" | |
| 1944 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r") | |
| 1945 (match_operand:SI 1 "const_int_operand" "I")] | |
| 1946 UNSPEC_MTC3)] | |
| 1947 "" | |
| 1948 "* return iq2000_fill_delay_slot (\"mtc3\\t%0, %%%1\", DELAY_NONE, operands, insn);" | |
| 1949 [(set_attr "dslot" "ok_in_dslot")] | |
| 1950 ) | |
| 1951 | |
| 1952 (define_insn "lur" | |
| 1953 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r") | |
| 1954 (match_operand:SI 1 "register_operand" "r")] | |
| 1955 UNSPEC_LUR)] | |
| 1956 "" | |
| 1957 "* return iq2000_fill_delay_slot (\"lur\\t%0, %1\", DELAY_NONE, operands, insn);" | |
| 1958 [(set_attr "dslot" "not_in_dslot")] | |
| 1959 ) | |
| 1960 | |
| 1961 (define_insn "rb" | |
| 1962 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r") | |
| 1963 (match_operand:SI 1 "register_operand" "r")] | |
| 1964 UNSPEC_RB)] | |
| 1965 "" | |
| 1966 "* return iq2000_fill_delay_slot (\"rb\\t%0, %1\", DELAY_NONE, operands, insn);" | |
| 1967 [(set_attr "dslot" "not_in_dslot")] | |
| 1968 ) | |
| 1969 | |
| 1970 (define_insn "rx" | |
| 1971 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r") | |
| 1972 (match_operand:SI 1 "register_operand" "r")] | |
| 1973 UNSPEC_RX)] | |
| 1974 "" | |
| 1975 "* return iq2000_fill_delay_slot (\"rx\\t%0, %1\", DELAY_NONE, operands, insn);" | |
| 1976 [(set_attr "dslot" "not_in_dslot")] | |
| 1977 ) | |
| 1978 | |
| 1979 (define_insn "srrd" | |
| 1980 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")] | |
| 1981 UNSPEC_SRRD)] | |
| 1982 "" | |
| 1983 "* return iq2000_fill_delay_slot (\"srrd\\t%0\", DELAY_NONE, operands, insn);" | |
| 1984 [(set_attr "dslot" "not_in_dslot")] | |
| 1985 ) | |
| 1986 | |
| 1987 (define_insn "srwr" | |
| 1988 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r") | |
| 1989 (match_operand:SI 1 "register_operand" "r")] | |
| 1990 UNSPEC_SRWR)] | |
| 1991 "" | |
| 1992 "* return iq2000_fill_delay_slot (\"srwr\\t%0, %1\", DELAY_NONE, operands, insn);" | |
| 1993 [(set_attr "dslot" "not_in_dslot")] | |
| 1994 ) | |
| 1995 | |
| 1996 (define_insn "wb" | |
| 1997 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r") | |
| 1998 (match_operand:SI 1 "register_operand" "r")] | |
| 1999 UNSPEC_WB)] | |
| 2000 "" | |
| 2001 "* return iq2000_fill_delay_slot (\"wb\\t%0, %1\", DELAY_NONE, operands, insn);" | |
| 2002 [(set_attr "dslot" "not_in_dslot")] | |
| 2003 ) | |
| 2004 | |
| 2005 (define_insn "wx" | |
| 2006 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r") | |
| 2007 (match_operand:SI 1 "register_operand" "r")] | |
| 2008 UNSPEC_WX)] | |
| 2009 "" | |
| 2010 "* return iq2000_fill_delay_slot (\"wx\\t%0, %1\", DELAY_NONE, operands, insn);" | |
| 2011 [(set_attr "dslot" "not_in_dslot")] | |
| 2012 ) | |
| 2013 | |
| 2014 (define_insn "luc32" | |
| 2015 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r") | |
| 2016 (match_operand:SI 1 "register_operand" "r")] | |
| 2017 UNSPEC_LUC32)] | |
| 2018 "" | |
| 2019 "* return iq2000_fill_delay_slot (\"luc32\\t%0, %1\", DELAY_NONE, operands, insn);" | |
| 2020 [(set_attr "dslot" "not_in_dslot")] | |
| 2021 ) | |
| 2022 | |
| 2023 (define_insn "luc32l" | |
| 2024 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r") | |
| 2025 (match_operand:SI 1 "register_operand" "r")] | |
| 2026 UNSPEC_LUC32L)] | |
| 2027 "" | |
| 2028 "* return iq2000_fill_delay_slot (\"luc32l\\t%0, %1\", DELAY_NONE, operands, insn);" | |
| 2029 [(set_attr "dslot" "not_in_dslot")] | |
| 2030 ) | |
| 2031 | |
| 2032 (define_insn "luc64" | |
| 2033 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r") | |
| 2034 (match_operand:SI 1 "register_operand" "r")] | |
| 2035 UNSPEC_LUC64)] | |
| 2036 "" | |
| 2037 "* return iq2000_fill_delay_slot (\"luc64\\t%0, %1\", DELAY_NONE, operands, insn);" | |
| 2038 [(set_attr "dslot" "not_in_dslot")] | |
| 2039 ) | |
| 2040 | |
| 2041 (define_insn "luc64l" | |
| 2042 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r") | |
| 2043 (match_operand:SI 1 "register_operand" "r")] | |
| 2044 UNSPEC_LUC64L)] | |
| 2045 "" | |
| 2046 "* return iq2000_fill_delay_slot (\"luc64l\\t%0, %1\", DELAY_NONE, operands, insn);" | |
| 2047 [(set_attr "dslot" "not_in_dslot")] | |
| 2048 ) | |
| 2049 | |
| 2050 (define_insn "luk" | |
| 2051 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r") | |
| 2052 (match_operand:SI 1 "register_operand" "r")] | |
| 2053 UNSPEC_LUK)] | |
| 2054 "" | |
| 2055 "* return iq2000_fill_delay_slot (\"luk\\t%0, %1\", DELAY_NONE, operands, insn);" | |
| 2056 [(set_attr "dslot" "ok_in_dslot")] | |
| 2057 ) | |
| 2058 | |
| 2059 (define_insn "lulck" | |
| 2060 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")] | |
| 2061 UNSPEC_LULCK)] | |
| 2062 "" | |
| 2063 "* return iq2000_fill_delay_slot (\"lulck\\t%0\", DELAY_NONE, operands, insn);" | |
| 2064 [(set_attr "dslot" "not_in_dslot")] | |
| 2065 ) | |
| 2066 | |
| 2067 (define_insn "lum32" | |
| 2068 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r") | |
| 2069 (match_operand:SI 1 "register_operand" "r")] | |
| 2070 UNSPEC_LUM32)] | |
| 2071 "" | |
| 2072 "* return iq2000_fill_delay_slot (\"lum32\\t%0, %1\", DELAY_NONE, operands, insn);" | |
| 2073 [(set_attr "dslot" "not_in_dslot")] | |
| 2074 ) | |
| 2075 | |
| 2076 (define_insn "lum32l" | |
| 2077 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r") | |
| 2078 (match_operand:SI 1 "register_operand" "r")] | |
| 2079 UNSPEC_LUM32L)] | |
| 2080 "" | |
| 2081 "* return iq2000_fill_delay_slot (\"lum32l\\t%0, %1\", DELAY_NONE, operands, insn);" | |
| 2082 [(set_attr "dslot" "not_in_dslot")] | |
| 2083 ) | |
| 2084 | |
| 2085 (define_insn "lum64" | |
| 2086 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r") | |
| 2087 (match_operand:SI 1 "register_operand" "r")] | |
| 2088 UNSPEC_LUM64)] | |
| 2089 "" | |
| 2090 "* return iq2000_fill_delay_slot (\"lum64\\t%0, %1\", DELAY_NONE, operands, insn);" | |
| 2091 [(set_attr "dslot" "not_in_dslot")] | |
| 2092 ) | |
| 2093 | |
| 2094 (define_insn "lum64l" | |
| 2095 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r") | |
| 2096 (match_operand:SI 1 "register_operand" "r")] | |
| 2097 UNSPEC_LUM64L)] | |
| 2098 "" | |
| 2099 "* return iq2000_fill_delay_slot (\"lum64l\\t%0, %1\", DELAY_NONE, operands, insn);" | |
| 2100 [(set_attr "dslot" "not_in_dslot")] | |
| 2101 ) | |
| 2102 | |
| 2103 (define_insn "lurl" | |
| 2104 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r") | |
| 2105 (match_operand:SI 1 "register_operand" "r")] | |
| 2106 UNSPEC_LURL)] | |
| 2107 "" | |
| 2108 "* return iq2000_fill_delay_slot (\"lurl\\t%0, %1\", DELAY_NONE, operands, insn);" | |
| 2109 [(set_attr "dslot" "not_in_dslot")] | |
| 2110 ) | |
| 2111 | |
| 2112 (define_insn "mrgb" | |
| 2113 [(set (match_operand:SI 0 "register_operand" "=r") | |
| 2114 (unspec_volatile:SI [(match_operand:SI 1 "register_operand" "r") | |
| 2115 (match_operand:SI 2 "register_operand" "r") | |
| 2116 (match_operand:SI 3 "const_int_operand" "I")] | |
| 2117 UNSPEC_MRGB))] | |
| 2118 "" | |
| 2119 "* return iq2000_fill_delay_slot (\"mrgb\\t%0, %1, %2, %3\", DELAY_LOAD, operands, insn);" | |
| 2120 [(set_attr "dslot" "ok_in_dslot")] | |
| 2121 ) | |
| 2122 | |
| 2123 (define_insn "srrdl" | |
| 2124 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")] | |
| 2125 UNSPEC_SRRDL)] | |
| 2126 "" | |
| 2127 "* return iq2000_fill_delay_slot (\"srrdl\\t%0\", DELAY_NONE, operands, insn);" | |
| 2128 [(set_attr "dslot" "not_in_dslot")] | |
| 2129 ) | |
| 2130 | |
| 2131 (define_insn "srulck" | |
| 2132 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")] | |
| 2133 UNSPEC_SRULCK)] | |
| 2134 "" | |
| 2135 "* return iq2000_fill_delay_slot (\"srulck\\t%0\", DELAY_NONE, operands, insn);" | |
| 2136 [(set_attr "dslot" "not_in_dslot")] | |
| 2137 ) | |
| 2138 | |
| 2139 (define_insn "srwru" | |
| 2140 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r") | |
| 2141 (match_operand:SI 1 "register_operand" "r")] | |
| 2142 UNSPEC_SRWRU)] | |
| 2143 "" | |
| 2144 "* return iq2000_fill_delay_slot (\"srwru\\t%0, %1\", DELAY_NONE, operands, insn);" | |
| 2145 [(set_attr "dslot" "not_in_dslot")] | |
| 2146 ) | |
| 2147 | |
| 2148 (define_insn "trapqfl" | |
| 2149 [(unspec_volatile:SI [(const_int 1)] UNSPEC_TRAPQFL)] | |
| 2150 "" | |
| 2151 "* return iq2000_fill_delay_slot (\"trapqfl\", DELAY_NONE, operands, insn);" | |
| 2152 [(set_attr "dslot" "not_in_dslot")] | |
| 2153 ) | |
| 2154 | |
| 2155 (define_insn "trapqne" | |
| 2156 [(unspec_volatile:SI [(const_int 2)] UNSPEC_TRAPQNE)] | |
| 2157 "" | |
| 2158 "* return iq2000_fill_delay_slot (\"trapqne\", DELAY_NONE, operands, insn);" | |
| 2159 [(set_attr "dslot" "not_in_dslot")] | |
| 2160 ) | |
| 2161 | |
| 2162 (define_insn "traprel" | |
| 2163 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")] | |
| 2164 UNSPEC_TRAPREL)] | |
| 2165 "" | |
| 2166 "* return iq2000_fill_delay_slot (\"traprel %0\", DELAY_NONE, operands, insn);" | |
| 2167 [(set_attr "dslot" "not_in_dslot")] | |
| 2168 ) | |
| 2169 | |
| 2170 (define_insn "wbu" | |
| 2171 [(unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r") | |
| 2172 (match_operand:SI 1 "register_operand" "r")] | |
| 2173 UNSPEC_WBU)] | |
| 2174 "" | |
| 2175 "* return iq2000_fill_delay_slot (\"wbu\\t%0, %1\", DELAY_NONE, operands, insn);" | |
| 2176 [(set_attr "dslot" "not_in_dslot")] | |
| 2177 ) | |
| 2178 | |
| 2179 (define_insn "syscall" | |
| 2180 [(unspec_volatile:SI [(const_int 2)] UNSPEC_SYSCALL)] | |
| 2181 "" | |
| 2182 "syscall" | |
| 2183 [(set_attr "dslot" "not_in_dslot")] | |
| 2184 ) |