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annotate gcc/ira.h @ 55:77e2b8dfacca gcc-4.4.5

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update it from 4.4.3 to 4.5.0
author ryoma <e075725@ie.u-ryukyu.ac.jp>
date Fri, 12 Feb 2010 23:39:51 +0900
parents a06113de4d67
children f6334be47118
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1 /* Communication between the Integrated Register Allocator (IRA) and
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2 the rest of the compiler.
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3 Copyright (C) 2006, 2007, 2008, 2009
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4 Free Software Foundation, Inc.
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5 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
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6
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7 This file is part of GCC.
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8
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9 GCC is free software; you can redistribute it and/or modify it under
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10 the terms of the GNU General Public License as published by the Free
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11 Software Foundation; either version 3, or (at your option) any later
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12 version.
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13
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14 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
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15 WARRANTY; without even the implied warranty of MERCHANTABILITY or
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16 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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17 for more details.
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18
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19 You should have received a copy of the GNU General Public License
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20 along with GCC; see the file COPYING3. If not see
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21 <http://www.gnu.org/licenses/>. */
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22
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23 /* Number of given class hard registers available for the register
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24 allocation for given classes. */
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25 extern int ira_available_class_regs[N_REG_CLASSES];
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26
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27 /* Map: hard register number -> cover class it belongs to. If the
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28 corresponding class is NO_REGS, the hard register is not available
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29 for allocation. */
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30 extern enum reg_class ira_hard_regno_cover_class[FIRST_PSEUDO_REGISTER];
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31
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32 /* Number of cover classes. Cover classes is non-intersected register
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33 classes containing all hard-registers available for the
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34 allocation. */
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35 extern int ira_reg_class_cover_size;
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36
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37 /* The array containing cover classes (see also comments for macro
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38 IRA_COVER_CLASSES). Only first IRA_REG_CLASS_COVER_SIZE elements are
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39 used for this. */
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40 extern enum reg_class ira_reg_class_cover[N_REG_CLASSES];
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41
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42 /* Map of all register classes to corresponding cover class containing
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43 the given class. If given class is not a subset of a cover class,
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44 we translate it into the cheapest cover class. */
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45 extern enum reg_class ira_class_translate[N_REG_CLASSES];
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46
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47 /* Map: register class x machine mode -> number of hard registers of
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48 given class needed to store value of given mode. If the number for
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49 some hard-registers of the register class is different, the size
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50 will be negative. */
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51 extern int ira_reg_class_nregs[N_REG_CLASSES][MAX_MACHINE_MODE];
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52
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53 /* Function specific hard registers can not be used for the register
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54 allocation. */
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55 extern HARD_REG_SET ira_no_alloc_regs;
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56
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57 /* True if we have allocno conflicts. It is false for non-optimized
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58 mode or when the conflict table is too big. */
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59 extern bool ira_conflicts_p;
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60
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61 /* Array analogous to macro MEMORY_MOVE_COST. */
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62 extern short ira_memory_move_cost[MAX_MACHINE_MODE][N_REG_CLASSES][2];
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63
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64 /* Array of number of hard registers of given class which are
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65 available for the allocation. The order is defined by the
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66 allocation order. */
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67 extern short ira_class_hard_regs[N_REG_CLASSES][FIRST_PSEUDO_REGISTER];
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68
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69 /* The number of elements of the above array for given register
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70 class. */
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71 extern int ira_class_hard_regs_num[N_REG_CLASSES];
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72
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73 extern void ira_init_once (void);
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74 extern void ira_init (void);
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75 extern void ira_finish_once (void);
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76 extern void ira_setup_eliminable_regset (void);
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77 extern rtx ira_eliminate_regs (rtx, enum machine_mode);
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78 extern void ira_set_pseudo_classes (FILE *);
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79 extern void ira_implicitly_set_insn_hard_regs (HARD_REG_SET *);
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80
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81 extern void ira_sort_regnos_for_alter_reg (int *, int, unsigned int *);
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82 extern void ira_mark_allocation_change (int);
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83 extern void ira_mark_memory_move_deletion (int, int);
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84 extern bool ira_reassign_pseudos (int *, int, HARD_REG_SET, HARD_REG_SET *,
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85 HARD_REG_SET *, bitmap);
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86 extern rtx ira_reuse_stack_slot (int, unsigned int, unsigned int);
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87 extern void ira_mark_new_stack_slot (rtx, int, unsigned int);
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88 extern bool ira_better_spill_reload_regno_p (int *, int *, rtx, rtx, rtx);
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89