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1 /* Common hooks of Andes NDS32 cpu for GNU compiler
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2 Copyright (C) 2012-2018 Free Software Foundation, Inc.
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3 Contributed by Andes Technology Corporation.
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4
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5 This file is part of GCC.
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6
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7 GCC is free software; you can redistribute it and/or modify it
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8 under the terms of the GNU General Public License as published
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9 by the Free Software Foundation; either version 3, or (at your
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10 option) any later version.
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11
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12 GCC is distributed in the hope that it will be useful, but WITHOUT
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13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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15 License for more details.
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16
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17 You should have received a copy of the GNU General Public License
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18 along with GCC; see the file COPYING3. If not see
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19 <http://www.gnu.org/licenses/>. */
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20
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21 #include "config.h"
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22 #include "system.h"
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23 #include "coretypes.h"
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24 #include "diagnostic-core.h"
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25 #include "tm.h"
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26 #include "common/common-target.h"
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27 #include "common/common-target-def.h"
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28 #include "opts.h"
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29 #include "flags.h"
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30
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31 /* ------------------------------------------------------------------------ */
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32
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33 /* Implement TARGET_HANDLE_OPTION. */
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34 static bool
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35 nds32_handle_option (struct gcc_options *opts ATTRIBUTE_UNUSED,
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36 struct gcc_options *opts_set ATTRIBUTE_UNUSED,
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37 const struct cl_decoded_option *decoded,
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38 location_t loc)
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39 {
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40 size_t code = decoded->opt_index;
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41 int value = decoded->value;
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42
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43 switch (code)
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44 {
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45 case OPT_misr_vector_size_:
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46 /* Check the valid vector size: 4 or 16. */
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47 if (value != 4 && value != 16)
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48 {
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49 error_at (loc, "for the option -misr-vector-size=X, the valid X "
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50 "must be: 4 or 16");
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51 return false;
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52 }
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53
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54 return true;
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55
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56 case OPT_misr_secure_:
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57 /* Check the valid security level: 0 1 2 3. */
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58 if (value < 0 || value > 3)
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59 {
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60 error_at (loc, "for the option -misr-secure=X, the valid X "
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61 "must be: 0, 1, 2, or 3");
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62 return false;
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63 }
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64 return true;
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65
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66 case OPT_mcache_block_size_:
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67 /* Check valid value: 4 8 16 32 64 128 256 512. */
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68 if (exact_log2 (value) < 2 || exact_log2 (value) > 9)
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69 {
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70 error_at (loc, "for the option -mcache-block-size=X, the valid X "
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71 "must be: 4, 8, 16, 32, 64, 128, 256, or 512");
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72 return false;
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73 }
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74
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75 return true;
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76
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77 default:
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78 return true;
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79 }
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80 }
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81
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82 /* ------------------------------------------------------------------------ */
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83
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84 /* Implement TARGET_OPTION_OPTIMIZATION_TABLE. */
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85 static const struct default_options nds32_option_optimization_table[] =
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86 {
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87 #if TARGET_LINUX_ABI == 0
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88 /* Disable -fdelete-null-pointer-checks by default in ELF toolchain. */
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89 { OPT_LEVELS_ALL, OPT_fdelete_null_pointer_checks,
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90 NULL, 0 },
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91 #endif
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92 /* Enable -fsched-pressure by default at -O1 and above. */
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93 { OPT_LEVELS_1_PLUS, OPT_fsched_pressure, NULL, 1 },
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94 /* Enable -fomit-frame-pointer by default at all optimization levels. */
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95 { OPT_LEVELS_ALL, OPT_fomit_frame_pointer, NULL, 1 },
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96 /* Enable -mrelax-hint by default at all optimization levels. */
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97 { OPT_LEVELS_ALL, OPT_mrelax_hint, NULL, 1 },
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98 /* Enalbe -malways-align by default at -O1 and above, but not -Os or -Og. */
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99 { OPT_LEVELS_1_PLUS_SPEED_ONLY, OPT_malways_align, NULL, 1 },
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100 /* Enable -mv3push by default at -Os, but it is useless under V2 ISA. */
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101 { OPT_LEVELS_SIZE, OPT_mv3push, NULL, 1 },
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102
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103 { OPT_LEVELS_NONE, 0, NULL, 0 }
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104 };
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105
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106 /* ------------------------------------------------------------------------ */
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107
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108 /* Implement TARGET_EXCEPT_UNWIND_INFO. */
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109 static enum unwind_info_type
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110 nds32_except_unwind_info (struct gcc_options *opts ATTRIBUTE_UNUSED)
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111 {
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112 if (TARGET_LINUX_ABI)
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113 return UI_DWARF2;
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114
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115 return UI_SJLJ;
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116 }
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117
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118 /* ------------------------------------------------------------------------ */
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119
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120
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121 /* Run-time Target Specification. */
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122
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123 /* The default target flags consist of
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124 TARGET_CPU_DEFAULT and other MASK_XXX flags.
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125
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126 The value of TARGET_CPU_DEFAULT is set by
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127 the process of 'configure' and 'make' stage.
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128 Please check gcc/config.gcc for more implementation detail.
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129
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130 Other MASK_XXX flags are set individually.
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131 By default we enable
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131
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132 TARGET_16_BIT : Generate 16/32 bit mixed length instruction.
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133 TARGET_EXT_PERF : Generate performance extention instrcution.
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134 TARGET_EXT_PERF2 : Generate performance extention version 2 instrcution.
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135 TARGET_EXT_STRING : Generate string extention instrcution.
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136 TARGET_HW_ABS : Generate hardware abs instruction.
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137 TARGET_CMOV : Generate conditional move instruction. */
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138 #undef TARGET_DEFAULT_TARGET_FLAGS
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139 #define TARGET_DEFAULT_TARGET_FLAGS \
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140 (TARGET_CPU_DEFAULT \
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141 | TARGET_DEFAULT_FPU_ISA \
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142 | TARGET_DEFAULT_FPU_FMA \
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143 | MASK_16_BIT \
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144 | MASK_EXT_PERF \
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145 | MASK_EXT_PERF2 \
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146 | MASK_EXT_STRING \
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147 | MASK_HW_ABS \
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148 | MASK_CMOV)
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149
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150 #undef TARGET_HANDLE_OPTION
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151 #define TARGET_HANDLE_OPTION nds32_handle_option
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152
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153 #undef TARGET_OPTION_OPTIMIZATION_TABLE
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154 #define TARGET_OPTION_OPTIMIZATION_TABLE nds32_option_optimization_table
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155
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156
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157 /* Defining the Output Assembler Language. */
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158
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159 #undef TARGET_EXCEPT_UNWIND_INFO
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160 #define TARGET_EXCEPT_UNWIND_INFO nds32_except_unwind_info
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161
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162 /* ------------------------------------------------------------------------ */
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163
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164 struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER;
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165
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166 /* ------------------------------------------------------------------------ */
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