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1 ; Options for the DEC Alpha port of the compiler
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2 ;
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3 ; Copyright (C) 2005-2018 Free Software Foundation, Inc.
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4 ;
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5 ; This file is part of GCC.
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6 ;
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7 ; GCC is free software; you can redistribute it and/or modify it under
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8 ; the terms of the GNU General Public License as published by the Free
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9 ; Software Foundation; either version 3, or (at your option) any later
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10 ; version.
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11 ;
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12 ; GCC is distributed in the hope that it will be useful, but WITHOUT
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13 ; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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14 ; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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15 ; License for more details.
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16 ;
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17 ; You should have received a copy of the GNU General Public License
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18 ; along with GCC; see the file COPYING3. If not see
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19 ; <http://www.gnu.org/licenses/>.
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20
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21 msoft-float
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22 Target Report Mask(SOFT_FP)
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111
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23 Do not use hardware fp.
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0
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24
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25 mfp-regs
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26 Target Report Mask(FPREGS)
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111
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27 Use fp registers.
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0
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28
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29 mgas
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30 Target Ignore
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31 Does nothing. Preserved for backward compatibility.
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0
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32
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33 mieee-conformant
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34 Target RejectNegative Mask(IEEE_CONFORMANT)
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35 Request IEEE-conformant math library routines (OSF/1).
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36
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37 mieee
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38 Target Report RejectNegative Mask(IEEE)
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39 Emit IEEE-conformant code, without inexact exceptions.
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40
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41 mieee-with-inexact
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42 Target Report RejectNegative Mask(IEEE_WITH_INEXACT)
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43
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44 mbuild-constants
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45 Target Report Mask(BUILD_CONSTANTS)
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46 Do not emit complex integer constants to read-only memory.
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47
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48 mfloat-vax
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49 Target Report RejectNegative Mask(FLOAT_VAX)
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50 Use VAX fp.
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51
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52 mfloat-ieee
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53 Target Report RejectNegative InverseMask(FLOAT_VAX)
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54 Do not use VAX fp.
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55
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56 mbwx
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57 Target Report Mask(BWX)
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111
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58 Emit code for the byte/word ISA extension.
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59
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60 mmax
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61 Target Report Mask(MAX)
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62 Emit code for the motion video ISA extension.
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63
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64 mfix
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65 Target Report Mask(FIX)
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66 Emit code for the fp move and sqrt ISA extension.
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67
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68 mcix
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69 Target Report Mask(CIX)
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70 Emit code for the counting ISA extension.
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71
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72 mexplicit-relocs
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73 Target Report Mask(EXPLICIT_RELOCS)
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74 Emit code using explicit relocation directives.
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75
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76 msmall-data
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77 Target Report RejectNegative Mask(SMALL_DATA)
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78 Emit 16-bit relocations to the small data areas.
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79
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80 mlarge-data
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81 Target Report RejectNegative InverseMask(SMALL_DATA)
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82 Emit 32-bit relocations to the small data areas.
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83
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84 msmall-text
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85 Target Report RejectNegative Mask(SMALL_TEXT)
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86 Emit direct branches to local functions.
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87
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88 mlarge-text
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89 Target Report RejectNegative InverseMask(SMALL_TEXT)
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90 Emit indirect branches to local functions.
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91
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92 mtls-kernel
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93 Target Report Mask(TLS_KERNEL)
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94 Emit rdval instead of rduniq for thread pointer.
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95
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96 mlong-double-128
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97 Target Report RejectNegative Mask(LONG_DOUBLE_128)
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98 Use 128-bit long double.
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99
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100 mlong-double-64
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101 Target Report RejectNegative InverseMask(LONG_DOUBLE_128)
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102 Use 64-bit long double.
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103
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104 mcpu=
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105 Target RejectNegative Joined Var(alpha_cpu_string)
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106 Use features of and schedule given CPU.
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107
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108 mtune=
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109 Target RejectNegative Joined Var(alpha_tune_string)
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110 Schedule given CPU.
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111
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112 mfp-rounding-mode=
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113 Target RejectNegative Joined Var(alpha_fprm_string)
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114 Control the generated fp rounding mode.
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115
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116 mfp-trap-mode=
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117 Target RejectNegative Joined Var(alpha_fptm_string)
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118 Control the IEEE trap mode.
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119
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120 mtrap-precision=
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121 Target RejectNegative Joined Var(alpha_tp_string)
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122 Control the precision given to fp exceptions.
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123
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124 mmemory-latency=
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125 Target RejectNegative Joined Var(alpha_mlat_string)
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126 Tune expected memory latency.
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127
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128 mtls-size=
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129 Target RejectNegative Joined UInteger Var(alpha_tls_size) Init(32)
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130 Specify bit size of immediate TLS offsets.
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