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1 ;; ARM Cortex-A17 pipeline description
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2 ;; Copyright (C) 2014-2018 Free Software Foundation, Inc.
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3 ;;
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4 ;; Contributed by ARM Ltd.
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5 ;;
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6 ;; This file is part of GCC.
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7 ;;
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8 ;; GCC is free software; you can redistribute it and/or modify it
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9 ;; under the terms of the GNU General Public License as published by
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10 ;; the Free Software Foundation; either version 3, or (at your option)
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11 ;; any later version.
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12 ;;
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13 ;; GCC is distributed in the hope that it will be useful, but
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14 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
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15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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16 ;; General Public License for more details.
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17 ;;
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18 ;; You should have received a copy of the GNU General Public License
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19 ;; along with GCC; see the file COPYING3. If not see
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20 ;; <http://www.gnu.org/licenses/>.
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21
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22
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23 (define_automaton "cortex_a17")
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24
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25 (define_cpu_unit "ca17_ls0, ca17_ls1" "cortex_a17")
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26 (define_cpu_unit "ca17_alu0, ca17_alu1" "cortex_a17")
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27 (define_cpu_unit "ca17_mac" "cortex_a17")
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28 (define_cpu_unit "ca17_idiv" "cortex_a17")
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29 (define_cpu_unit "ca17_bx" "cortex_a17")
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30
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31 (define_reservation "ca17_alu" "(ca17_alu0|ca17_alu1)")
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32
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33
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34
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35 ;; Simple Execution Unit:
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36 ;;
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37 ;; Simple ALU
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38 (define_insn_reservation "cortex_a17_alu" 1
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39 (and (eq_attr "tune" "cortexa17")
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40 (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
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41 alu_sreg,alus_sreg,logic_reg,logics_reg,\
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42 adc_imm,adcs_imm,adc_reg,adcs_reg,\
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43 adr, mov_imm,mov_reg,\
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44 mvn_imm,mvn_reg,extend,\
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45 mrs,multiple,no_insn"))
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46 "ca17_alu")
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47
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48 (define_insn_reservation "cortex_a17_alu_shiftimm" 2
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49 (and (eq_attr "tune" "cortexa17")
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50 (eq_attr "type" "bfm,clz,rev,rbit, alu_shift_imm, alus_shift_imm,
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51 logic_shift_imm,alu_dsp_reg, logics_shift_imm,shift_imm,\
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52 shift_reg, mov_shift,mvn_shift"))
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53 "ca17_alu")
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54
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55
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56 ;; ALU ops with register controlled shift.
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57 (define_insn_reservation "cortex_a17_alu_shift_reg" 2
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58 (and (eq_attr "tune" "cortexa17")
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59 (eq_attr "type" "alu_shift_reg,alus_shift_reg,\
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60 logic_shift_reg,logics_shift_reg"))
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61 "ca17_alu0")
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62
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63
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64 ;; Multiply Execution Unit:
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65
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66 ;; 32-bit multiplies
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67 (define_insn_reservation "cortex_a17_mult32" 4
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68 (and (eq_attr "tune" "cortexa17")
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69 (eq_attr "type" "mul,muls,smmul,smmulr"))
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70 "ca17_alu0+ca17_mac")
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71
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72 (define_insn_reservation "cortex_a17_mac32" 4
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73 (and (eq_attr "tune" "cortexa17")
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74 (eq_attr "type" "mla,mlas,smmla"))
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75 "ca17_alu0+ca17_mac,ca17_mac")
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76
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77 (define_insn_reservation "cortex_a17_mac32_other" 3
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78 (and (eq_attr "tune" "cortexa17")
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79 (eq_attr "type" "smlad,smladx,smlsd,smlsdx,smuad,smuadx,smusd,smusdx"))
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80 "ca17_alu0+ca17_mac,ca17_mac")
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81
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82 ;; 64-bit multiplies
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83 (define_insn_reservation "cortex_a17_mac64" 4
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84 (and (eq_attr "tune" "cortexa17")
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85 (eq_attr "type" "smlal,smlals,umaal,umlal,umlals"))
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86 "ca17_alu0+ca17_mac,ca17_mac")
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87
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88 (define_insn_reservation "cortex_a17_mac64_other" 3
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89 (and (eq_attr "tune" "cortexa17")
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90 (eq_attr "type" "smlald,smlalxy,smlsld"))
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91 "ca17_alu0+ca17_mac,ca17_mac")
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92
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93 (define_insn_reservation "cortex_a17_mult64" 4
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94 (and (eq_attr "tune" "cortexa17")
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95 (eq_attr "type" "smull,smulls,umull,umulls"))
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96 "ca17_alu0+ca17_mac,ca17_mac")
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97
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98
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99 (define_bypass 2 "cortex_a17_mult*, cortex_a17_mac*"
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100 "cortex_a17_mult*, cortex_a17_mac*"
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101 "arm_mac_accumulator_is_result")
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102
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103 ;; Integer divide
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104 (define_insn_reservation "cortex_a17_udiv" 19
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105 (and (eq_attr "tune" "cortexa17")
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106 (eq_attr "type" "udiv"))
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107 "ca17_alu1+ca17_idiv*10")
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108
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109 (define_insn_reservation "cortex_a17_sdiv" 20
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110 (and (eq_attr "tune" "cortexa17")
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111 (eq_attr "type" "sdiv"))
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112 "ca17_alu1+ca17_idiv*11")
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113
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114
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115
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116 ;; Branch execution Unit
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117 ;;
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118 ;; Branches take one issue slot.
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119 ;; No latency as there is no result
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120 (define_insn_reservation "cortex_a17_branch" 0
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121 (and (eq_attr "tune" "cortexa17")
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122 (eq_attr "type" "branch"))
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123 "ca17_bx")
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124
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125 ;; Load-store execution Unit
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126 ;;
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127 ;; Loads of up to two words.
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128 (define_insn_reservation "cortex_a17_load1" 4
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129 (and (eq_attr "tune" "cortexa17")
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130 (eq_attr "type" "load_byte,load_4,load_8"))
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131 "ca17_ls0|ca17_ls1")
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132
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133 ;; Loads of three words.
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134 (define_insn_reservation "cortex_a17_load3" 4
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135 (and (eq_attr "tune" "cortexa17")
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136 (eq_attr "type" "load_12"))
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137 "ca17_ls0+ca17_ls1")
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138
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139 ;; Loads of four words.
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140 (define_insn_reservation "cortex_a17_load4" 4
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141 (and (eq_attr "tune" "cortexa17")
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142 (eq_attr "type" "load_16"))
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143 "ca17_ls0+ca17_ls1")
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144
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145 ;; Stores of up to two words.
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146 (define_insn_reservation "cortex_a17_store1" 0
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147 (and (eq_attr "tune" "cortexa17")
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148 (eq_attr "type" "store_4,store_8"))
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149 "ca17_ls0|ca17_ls1")
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150
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151 ;; Stores of three words
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152 (define_insn_reservation "cortex_a17_store3" 0
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153 (and (eq_attr "tune" "cortexa17")
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154 (eq_attr "type" "store_12"))
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155 "ca17_ls0+ca17_ls1")
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156
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157 ;; Stores of four words.
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158 (define_insn_reservation "cortex_a17_store4" 0
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159 (and (eq_attr "tune" "cortexa17")
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160 (eq_attr "type" "store_16"))
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161 "ca17_ls0+ca17_ls1")
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162
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163 (define_insn_reservation "cortex_a17_call" 0
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164 (and (eq_attr "tune" "cortexa17")
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165 (eq_attr "type" "call"))
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166 "ca17_bx")
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167
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168
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169 (include "../arm/cortex-a17-neon.md")
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