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annotate gcc/config/arm/fa726te.md @ 131:84e7813d76e9

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gcc-8.2
author mir3636
date Thu, 25 Oct 2018 07:37:49 +0900
parents 04ced10e8804
children 1830386684a0
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
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1 ;; Faraday FA726TE Pipeline Description
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2 ;; Copyright (C) 2010-2018 Free Software Foundation, Inc.
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3 ;; Written by I-Jui Sung, based on ARM926EJ-S Pipeline Description.
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4 ;;
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5 ;; This file is part of GCC.
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6 ;;
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7 ;; GCC is free software; you can redistribute it and/or modify it under
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8 ;; the terms of the GNU General Public License as published by the Free
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9 ;; Software Foundation; either version 3, or (at your option) any later
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10 ;; version.
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11 ;;
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12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
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13 ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
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14 ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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15 ;; for more details.
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16 ;;
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17 ;; You should have received a copy of the GNU General Public License
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18 ;; along with GCC; see the file COPYING3. If not see
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19 ;; <http://www.gnu.org/licenses/>. */
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20
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21 ;; These descriptions are based on the information contained in the
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22 ;; FA726TE Core Design Note, Copyright (c) 2010 Faraday Technology Corp.
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23
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24 ;; This automaton provides a pipeline description for the Faraday
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25 ;; FA726TE core.
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26 ;;
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27 ;; The model given here assumes that the condition for all conditional
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28 ;; instructions is "true", i.e., that all of the instructions are
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29 ;; actually executed.
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30
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31 (define_automaton "fa726te")
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32
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33 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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34 ;; Pipelines
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35 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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36
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37 ;; The ALU pipeline has fetch, decode, execute, memory, and
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38 ;; write stages. We only need to model the execute, memory and write
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39 ;; stages.
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40
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41 ;; E1 E2 E3 E4 E5 WB
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42 ;;______________________________________________________
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43 ;;
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44 ;; <-------------- LD/ST ----------->
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45 ;; shifter + LU <-- AU -->
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46 ;; <-- AU --> shifter + LU CPSR (Pipe 0)
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47 ;;______________________________________________________
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48 ;;
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49 ;; <---------- MUL --------->
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50 ;; shifter + LU <-- AU -->
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51 ;; <-- AU --> shifter + LU CPSR (Pipe 1)
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52
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53
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54 (define_cpu_unit "fa726te_alu0_pipe,fa726te_alu1_pipe" "fa726te")
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55 (define_cpu_unit "fa726te_mac_pipe" "fa726te")
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56 (define_cpu_unit "fa726te_lsu_pipe_e,fa726te_lsu_pipe_w" "fa726te")
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57
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58 ;; Pretend we have 2 LSUs (the second is ONLY for LDR), which can possibly
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59 ;; improve code quality.
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60 (define_query_cpu_unit "fa726te_lsu1_pipe_e,fa726te_lsu1_pipe_w" "fa726te")
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61 (define_cpu_unit "fa726te_is0,fa726te_is1" "fa726te")
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62
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63 (define_reservation "fa726te_issue" "(fa726te_is0|fa726te_is1)")
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64 ;; Reservation to restrict issue to 1.
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65 (define_reservation "fa726te_blockage" "(fa726te_is0+fa726te_is1)")
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66
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67 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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68 ;; ALU Instructions
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69 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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70
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71 ;; ALU instructions require three cycles to execute, and use the ALU
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72 ;; pipeline in each of the three stages. The results are available
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73 ;; after the execute stage has finished.
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74 ;;
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75 ;; If the destination register is the PC, the pipelines are stalled
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76 ;; for several cycles. That case is not modeled here.
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77
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78 ;; Move instructions.
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79 (define_insn_reservation "726te_shift_op" 1
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80 (and (eq_attr "tune" "fa726te")
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81 (eq_attr "type" "mov_imm,mov_reg,mov_shift,mov_shift_reg,\
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82 mvn_imm,mvn_reg,mvn_shift,mvn_shift_reg"))
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83 "fa726te_issue+(fa726te_alu0_pipe|fa726te_alu1_pipe)")
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84
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85 ;; ALU operations with no shifted operand will finished in 1 cycle
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86 ;; Other ALU instructions 2 cycles.
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87 (define_insn_reservation "726te_alu_op" 1
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88 (and (eq_attr "tune" "fa726te")
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89 (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
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90 alu_sreg,alus_sreg,logic_reg,logics_reg,\
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91 adc_imm,adcs_imm,adc_reg,adcs_reg,\
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92 adr,bfm,rev,\
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93 shift_imm,shift_reg,\
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94 mrs,multiple,no_insn"))
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95 "fa726te_issue+(fa726te_alu0_pipe|fa726te_alu1_pipe)")
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96
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97 ;; ALU operations with a shift-by-register operand.
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98 ;; These really stall in the decoder, in order to read the shift value
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99 ;; in the first cycle. If the instruction uses both shifter and AU,
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100 ;; it takes 3 cycles.
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101 (define_insn_reservation "726te_alu_shift_op" 3
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102 (and (eq_attr "tune" "fa726te")
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103 (eq_attr "type" "extend,alu_shift_imm,alus_shift_imm,\
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104 logic_shift_imm,logics_shift_imm"))
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105 "fa726te_issue+(fa726te_alu0_pipe|fa726te_alu1_pipe)")
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106
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107 (define_insn_reservation "726te_alu_shift_reg_op" 3
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108 (and (eq_attr "tune" "fa726te")
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109 (eq_attr "type" "alu_shift_reg,alus_shift_reg,\
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110 logic_shift_reg,logics_shift_reg"))
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111 "fa726te_issue+(fa726te_alu0_pipe|fa726te_alu1_pipe)")
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112 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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113 ;; Multiplication Instructions
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114 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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115
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116 ;; Multiplication instructions loop in the execute stage until the
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117 ;; instruction has been passed through the multiplier array enough
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118 ;; times. Multiply operations occur in both the execute and memory
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119 ;; stages of the pipeline
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120
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121 (define_insn_reservation "726te_mult_op" 3
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122 (and (eq_attr "tune" "fa726te")
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123 (eq_attr "type" "smlalxy,mul,mla,muls,mlas,umull,umlal,smull,smlal,\
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124 umulls,umlals,smulls,smlals,smlawx,smulxy,smlaxy"))
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125 "fa726te_issue+fa726te_mac_pipe")
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126
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127 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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128 ;; Load/Store Instructions
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129 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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130
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
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131 ;; The models for load/store instructions do not accurately describe
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
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132 ;; the difference between operations with a base register writeback
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
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133 ;; (such as "ldm!"). These models assume that all memory references
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
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134 ;; hit in dcache.
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135
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
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136 ;; Loads with a shifted offset take 3 cycles, and are (a) probably the
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
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137 ;; most common and (b) the pessimistic assumption will lead to fewer stalls.
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138
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
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139 ;; Scalar loads are pipelined in FA726TE LSU pipe.
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
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140 ;; Here we model the resource conflict between Load@E3-stage & Store@W-stage.
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
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141 ;; The 2nd LSU (lsu1) is to model the fact that if 2 loads are scheduled in the
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
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142 ;; same "bundle", and the 2nd load will introudce another ISSUE stall but is
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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143 ;; still ok to execute (and may be benefical sometimes).
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144
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
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145 (define_insn_reservation "726te_load1_op" 3
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
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146 (and (eq_attr "tune" "fa726te")
111
kono
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147 (eq_attr "type" "load_4,load_byte"))
68
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
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148 "(fa726te_issue+fa726te_lsu_pipe_e+fa726te_lsu_pipe_w)\
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149 | (fa726te_issue+fa726te_lsu1_pipe_e+fa726te_lsu1_pipe_w,fa726te_blockage)")
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150
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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151 (define_insn_reservation "726te_store1_op" 1
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
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152 (and (eq_attr "tune" "fa726te")
111
kono
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153 (eq_attr "type" "store_4"))
68
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
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154 "fa726te_blockage*2")
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
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155
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
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156 ;; Load/Store Multiple blocks all pipelines in EX stages until WB.
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
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157 ;; No other instructions can be issued together. Since they essentially
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
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158 ;; prevent all scheduling opportunities, we model them together here.
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159
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160 ;; The LDM is breaking into multiple load instructions, later instruction in
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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161 ;; the pipe 1 is stalled.
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
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162 (define_insn_reservation "726te_ldm2_op" 4
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
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163 (and (eq_attr "tune" "fa726te")
111
kono
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164 (eq_attr "type" "load_8,load_12"))
68
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
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165 "fa726te_blockage*4")
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166
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
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167 (define_insn_reservation "726te_ldm3_op" 5
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168 (and (eq_attr "tune" "fa726te")
111
kono
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169 (eq_attr "type" "load_16"))
68
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170 "fa726te_blockage*5")
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171
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
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172 (define_insn_reservation "726te_stm2_op" 2
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173 (and (eq_attr "tune" "fa726te")
111
kono
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174 (eq_attr "type" "store_8,store_12"))
68
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
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175 "fa726te_blockage*3")
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176
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
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177 (define_insn_reservation "726te_stm3_op" 3
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
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178 (and (eq_attr "tune" "fa726te")
111
kono
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179 (eq_attr "type" "store_16"))
68
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180 "fa726te_blockage*4")
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
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181
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
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182 (define_bypass 1 "726te_load1_op,726te_ldm2_op,726te_ldm3_op" "726te_store1_op,\
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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183 726te_stm2_op,726te_stm3_op" "arm_no_early_store_addr_dep")
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
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184 (define_bypass 0 "726te_shift_op,726te_alu_op,726te_alu_shift_op,\
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
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185 726te_alu_shift_reg_op,726te_mult_op" "726te_store1_op"
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parents:
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186 "arm_no_early_store_addr_dep")
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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187 (define_bypass 0 "726te_shift_op,726te_alu_op" "726te_shift_op,726te_alu_op")
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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188 (define_bypass 1 "726te_alu_shift_op,726te_alu_shift_reg_op"
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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189 "726te_shift_op,726te_alu_op")
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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190 (define_bypass 1 "726te_alu_shift_op,726te_alu_shift_reg_op,726te_mult_op"
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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191 "726te_alu_shift_op" "arm_no_early_alu_shift_dep")
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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192 (define_bypass 1 "726te_alu_shift_op,726te_alu_shift_reg_op,726te_mult_op"
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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193 "726te_alu_shift_reg_op" "arm_no_early_alu_shift_value_dep")
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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194 (define_bypass 1 "726te_mult_op" "726te_shift_op,726te_alu_op")
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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195
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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196 (define_bypass 4 "726te_load1_op" "726te_mult_op")
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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197 (define_bypass 5 "726te_ldm2_op" "726te_mult_op")
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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198 (define_bypass 6 "726te_ldm3_op" "726te_mult_op")
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
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199
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parents:
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200 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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201 ;; Branch and Call Instructions
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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202 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
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203
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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204 ;; Branch instructions are difficult to model accurately. The FA726TE
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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205 ;; core can predict most branches. If the branch is predicted
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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206 ;; correctly, and predicted early enough, the branch can be completely
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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207 ;; eliminated from the instruction stream. Some branches can
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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208 ;; therefore appear to require zero cycle to execute. We assume that
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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209 ;; all branches are predicted correctly, and that the latency is
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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210 ;; therefore the minimum value.
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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211
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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212 (define_insn_reservation "726te_branch_op" 0
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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213 (and (eq_attr "tune" "fa726te")
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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214 (eq_attr "type" "branch"))
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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215 "fa726te_blockage")
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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216
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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217 ;; The latency for a call is actually the latency when the result is available.
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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218 ;; i.e. R0 is ready for int return value.
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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219 (define_insn_reservation "726te_call_op" 1
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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220 (and (eq_attr "tune" "fa726te")
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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221 (eq_attr "type" "call"))
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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222 "fa726te_blockage")
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
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223