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annotate gcc/config/arm/fmp626.md @ 131:84e7813d76e9

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gcc-8.2
author mir3636
date Thu, 25 Oct 2018 07:37:49 +0900
parents 04ced10e8804
children 1830386684a0
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
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1 ;; Faraday FA626TE Pipeline Description
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2 ;; Copyright (C) 2010-2018 Free Software Foundation, Inc.
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3 ;; Written by Mingfeng Wu, based on ARM926EJ-S Pipeline Description.
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4 ;;
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5 ;; This file is part of GCC.
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6 ;;
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7 ;; GCC is free software; you can redistribute it and/or modify it under
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8 ;; the terms of the GNU General Public License as published by the Free
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9 ;; Software Foundation; either version 3, or (at your option) any later
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10 ;; version.
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11 ;;
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12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
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13 ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
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14 ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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15 ;; for more details.
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16 ;;
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17 ;; You should have received a copy of the GNU General Public License
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18 ;; along with GCC; see the file COPYING3. If not see
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19 ;; <http://www.gnu.org/licenses/>. */
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20
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21 ;; These descriptions are based on the information contained in the
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22 ;; FMP626 Core Design Note, Copyright (c) 2010 Faraday Technology Corp.
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23
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24 ;; Pipeline architecture
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25 ;; S E M W(Q1) Q2
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26 ;; ___________________________________________
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27 ;; shifter alu
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28 ;; mul1 mul2 mul3
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29 ;; ld/st1 ld/st2 ld/st3 ld/st4 ld/st5
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30
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31 ;; This automaton provides a pipeline description for the Faraday
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32 ;; FMP626 core.
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33 ;;
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34 ;; The model given here assumes that the condition for all conditional
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35 ;; instructions is "true", i.e., that all of the instructions are
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36 ;; actually executed.
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37
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38 (define_automaton "fmp626")
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39
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40 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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41 ;; Pipelines
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42 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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43
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44 ;; There is a single pipeline
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45 ;;
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46 ;; The ALU pipeline has fetch, decode, execute, memory, and
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47 ;; write stages. We only need to model the execute, memory and write
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48 ;; stages.
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49
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50 (define_cpu_unit "fmp626_core" "fmp626")
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51
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52 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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53 ;; ALU Instructions
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54 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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55
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56 ;; ALU instructions require two cycles to execute, and use the ALU
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57 ;; pipeline in each of the three stages. The results are available
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58 ;; after the execute stage has finished.
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59 ;;
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60 ;; If the destination register is the PC, the pipelines are stalled
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61 ;; for several cycles. That case is not modeled here.
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62
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63 ;; ALU operations
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64 (define_insn_reservation "mp626_alu_op" 1
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65 (and (eq_attr "tune" "fmp626")
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66 (eq_attr "type" "alu_imm,alus_imm,alu_sreg,alus_sreg,\
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67 logic_imm,logics_imm,logic_reg,logics_reg,\
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68 adc_imm,adcs_imm,adc_reg,adcs_reg,\
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69 adr,bfm,rev,\
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70 shift_imm,shift_reg,\
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71 mov_imm,mov_reg,mvn_imm,mvn_reg"))
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72 "fmp626_core")
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73
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74 (define_insn_reservation "mp626_alu_shift_op" 2
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75 (and (eq_attr "tune" "fmp626")
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76 (eq_attr "type" "alu_shift_imm,logic_shift_imm,alus_shift_imm,logics_shift_imm,\
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77 alu_shift_reg,logic_shift_reg,alus_shift_reg,logics_shift_reg,\
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78 extend,\
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79 mov_shift,mov_shift_reg,\
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80 mvn_shift,mvn_shift_reg"))
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81 "fmp626_core")
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82
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83 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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84 ;; Multiplication Instructions
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85 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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86
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87 (define_insn_reservation "mp626_mult1" 2
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88 (and (eq_attr "tune" "fmp626")
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89 (eq_attr "type" "smulwy,smlawy,smulxy,smlaxy"))
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90 "fmp626_core")
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91
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92 (define_insn_reservation "mp626_mult2" 2
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93 (and (eq_attr "tune" "fmp626")
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94 (eq_attr "type" "mul,mla"))
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95 "fmp626_core")
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96
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97 (define_insn_reservation "mp626_mult3" 3
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98 (and (eq_attr "tune" "fmp626")
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99 (eq_attr "type" "muls,mlas,smull,smlal,umull,umlal,smlalxy,smlawx"))
68
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100 "fmp626_core*2")
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101
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102 (define_insn_reservation "mp626_mult4" 4
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103 (and (eq_attr "tune" "fmp626")
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104 (eq_attr "type" "smulls,smlals,umulls,umlals"))
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105 "fmp626_core*3")
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106
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107 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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108 ;; Load/Store Instructions
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109 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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110
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111 ;; The models for load/store instructions do not accurately describe
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112 ;; the difference between operations with a base register writeback
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113 ;; (such as "ldm!"). These models assume that all memory references
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114 ;; hit in dcache.
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115
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116 (define_insn_reservation "mp626_load1_op" 5
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117 (and (eq_attr "tune" "fmp626")
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118 (eq_attr "type" "load_4,load_byte"))
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119 "fmp626_core")
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120
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121 (define_insn_reservation "mp626_load2_op" 6
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122 (and (eq_attr "tune" "fmp626")
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123 (eq_attr "type" "load_8,load_12"))
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124 "fmp626_core*2")
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125
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126 (define_insn_reservation "mp626_load3_op" 7
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127 (and (eq_attr "tune" "fmp626")
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128 (eq_attr "type" "load_16"))
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129 "fmp626_core*3")
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130
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131 (define_insn_reservation "mp626_store1_op" 0
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132 (and (eq_attr "tune" "fmp626")
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133 (eq_attr "type" "store_4"))
68
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
134 "fmp626_core")
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
135
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
136 (define_insn_reservation "mp626_store2_op" 1
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
137 (and (eq_attr "tune" "fmp626")
111
kono
parents: 68
diff changeset
138 (eq_attr "type" "store_8,store_12"))
68
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
139 "fmp626_core*2")
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
140
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
141 (define_insn_reservation "mp626_store3_op" 2
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
142 (and (eq_attr "tune" "fmp626")
111
kono
parents: 68
diff changeset
143 (eq_attr "type" "store_16"))
68
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
144 "fmp626_core*3")
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
145
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
146 (define_bypass 1 "mp626_load1_op,mp626_load2_op,mp626_load3_op"
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
147 "mp626_store1_op,mp626_store2_op,mp626_store3_op"
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
148 "arm_no_early_store_addr_dep")
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
149 (define_bypass 1 "mp626_alu_op,mp626_alu_shift_op,mp626_mult1,mp626_mult2,\
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
150 mp626_mult3,mp626_mult4" "mp626_store1_op"
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
151 "arm_no_early_store_addr_dep")
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
152 (define_bypass 1 "mp626_alu_shift_op" "mp626_alu_op")
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
153 (define_bypass 1 "mp626_alu_shift_op" "mp626_alu_shift_op"
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
154 "arm_no_early_alu_shift_dep")
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
155 (define_bypass 1 "mp626_mult1,mp626_mult2" "mp626_alu_shift_op"
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
156 "arm_no_early_alu_shift_dep")
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
157 (define_bypass 2 "mp626_mult3" "mp626_alu_shift_op"
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
158 "arm_no_early_alu_shift_dep")
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
159 (define_bypass 3 "mp626_mult4" "mp626_alu_shift_op"
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
160 "arm_no_early_alu_shift_dep")
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
161 (define_bypass 1 "mp626_mult1,mp626_mult2" "mp626_alu_op")
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
162 (define_bypass 2 "mp626_mult3" "mp626_alu_op")
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
163 (define_bypass 3 "mp626_mult4" "mp626_alu_op")
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
164 (define_bypass 4 "mp626_load1_op" "mp626_alu_op")
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
165 (define_bypass 5 "mp626_load2_op" "mp626_alu_op")
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
166 (define_bypass 6 "mp626_load3_op" "mp626_alu_op")
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
167
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
168 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
169 ;; Branch and Call Instructions
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
170 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
171
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
172 ;; Branch instructions are difficult to model accurately. The FMP626
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
173 ;; core can predict most branches. If the branch is predicted
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
174 ;; correctly, and predicted early enough, the branch can be completely
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
175 ;; eliminated from the instruction stream. Some branches can
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
176 ;; therefore appear to require zero cycle to execute. We assume that
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
177 ;; all branches are predicted correctly, and that the latency is
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
178 ;; therefore the minimum value.
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
179
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
180 (define_insn_reservation "mp626_branch_op" 0
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
181 (and (eq_attr "tune" "fmp626")
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
182 (eq_attr "type" "branch"))
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
183 "fmp626_core")
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
184
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
185 ;; The latency for a call is actually the latency when the result is available.
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
186 ;; i.e. R0 ready for int return value.
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
187 (define_insn_reservation "mp626_call_op" 1
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
188 (and (eq_attr "tune" "fmp626")
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
189 (eq_attr "type" "call"))
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Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
190 "fmp626_core")
561a7518be6b update gcc-4.6
Nobuyasu Oshiro <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
191