Mercurial > hg > CbC > CbC_gcc
annotate gcc/config/arm/iwmmxt.md @ 131:84e7813d76e9
gcc-8.2
| author | mir3636 |
|---|---|
| date | Thu, 25 Oct 2018 07:37:49 +0900 |
| parents | 04ced10e8804 |
| children | 1830386684a0 |
| rev | line source |
|---|---|
| 0 | 1 ;; Patterns for the Intel Wireless MMX technology architecture. |
| 131 | 2 ;; Copyright (C) 2003-2018 Free Software Foundation, Inc. |
| 0 | 3 ;; Contributed by Red Hat. |
| 4 | |
| 5 ;; This file is part of GCC. | |
| 6 | |
| 7 ;; GCC is free software; you can redistribute it and/or modify it under | |
| 8 ;; the terms of the GNU General Public License as published by the Free | |
| 9 ;; Software Foundation; either version 3, or (at your option) any later | |
| 10 ;; version. | |
| 11 | |
| 12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT | |
| 13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
| 14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
| 15 ;; License for more details. | |
| 16 | |
| 17 ;; You should have received a copy of the GNU General Public License | |
| 18 ;; along with GCC; see the file COPYING3. If not see | |
| 19 ;; <http://www.gnu.org/licenses/>. | |
| 20 | |
| 111 | 21 ;; Register numbers. Need to sync with FIRST_IWMMXT_GR_REGNUM in arm.h |
| 22 (define_constants | |
| 23 [(WCGR0 96) | |
| 24 (WCGR1 97) | |
| 25 (WCGR2 98) | |
| 26 (WCGR3 99) | |
| 27 ] | |
| 28 ) | |
| 29 | |
| 30 (define_insn "tbcstv8qi" | |
| 31 [(set (match_operand:V8QI 0 "register_operand" "=y") | |
| 32 (vec_duplicate:V8QI (match_operand:QI 1 "s_register_operand" "r")))] | |
| 33 "TARGET_REALLY_IWMMXT" | |
| 34 "tbcstb%?\\t%0, %1" | |
| 35 [(set_attr "predicable" "yes") | |
| 36 (set_attr "type" "wmmx_tbcst")] | |
| 37 ) | |
| 38 | |
| 39 (define_insn "tbcstv4hi" | |
| 40 [(set (match_operand:V4HI 0 "register_operand" "=y") | |
| 41 (vec_duplicate:V4HI (match_operand:HI 1 "s_register_operand" "r")))] | |
| 42 "TARGET_REALLY_IWMMXT" | |
| 43 "tbcsth%?\\t%0, %1" | |
| 44 [(set_attr "predicable" "yes") | |
| 45 (set_attr "type" "wmmx_tbcst")] | |
| 46 ) | |
| 47 | |
| 48 (define_insn "tbcstv2si" | |
| 49 [(set (match_operand:V2SI 0 "register_operand" "=y") | |
| 50 (vec_duplicate:V2SI (match_operand:SI 1 "s_register_operand" "r")))] | |
| 51 "TARGET_REALLY_IWMMXT" | |
| 52 "tbcstw%?\\t%0, %1" | |
| 53 [(set_attr "predicable" "yes") | |
| 54 (set_attr "type" "wmmx_tbcst")] | |
| 55 ) | |
| 0 | 56 |
| 57 (define_insn "iwmmxt_iordi3" | |
| 58 [(set (match_operand:DI 0 "register_operand" "=y,?&r,?&r") | |
| 59 (ior:DI (match_operand:DI 1 "register_operand" "%y,0,r") | |
| 60 (match_operand:DI 2 "register_operand" "y,r,r")))] | |
| 61 "TARGET_REALLY_IWMMXT" | |
| 62 "@ | |
| 63 wor%?\\t%0, %1, %2 | |
| 64 # | |
| 65 #" | |
| 66 [(set_attr "predicable" "yes") | |
| 111 | 67 (set_attr "length" "4,8,8") |
| 68 (set_attr "type" "wmmx_wor,*,*")] | |
| 69 ) | |
| 0 | 70 |
| 71 (define_insn "iwmmxt_xordi3" | |
| 72 [(set (match_operand:DI 0 "register_operand" "=y,?&r,?&r") | |
| 73 (xor:DI (match_operand:DI 1 "register_operand" "%y,0,r") | |
| 74 (match_operand:DI 2 "register_operand" "y,r,r")))] | |
| 75 "TARGET_REALLY_IWMMXT" | |
| 76 "@ | |
| 77 wxor%?\\t%0, %1, %2 | |
| 78 # | |
| 79 #" | |
| 80 [(set_attr "predicable" "yes") | |
| 111 | 81 (set_attr "length" "4,8,8") |
| 82 (set_attr "type" "wmmx_wxor,*,*")] | |
| 83 ) | |
| 0 | 84 |
| 85 (define_insn "iwmmxt_anddi3" | |
| 86 [(set (match_operand:DI 0 "register_operand" "=y,?&r,?&r") | |
| 87 (and:DI (match_operand:DI 1 "register_operand" "%y,0,r") | |
| 88 (match_operand:DI 2 "register_operand" "y,r,r")))] | |
| 89 "TARGET_REALLY_IWMMXT" | |
| 90 "@ | |
| 91 wand%?\\t%0, %1, %2 | |
| 92 # | |
| 93 #" | |
| 94 [(set_attr "predicable" "yes") | |
| 111 | 95 (set_attr "length" "4,8,8") |
| 96 (set_attr "type" "wmmx_wand,*,*")] | |
| 97 ) | |
| 0 | 98 |
| 99 (define_insn "iwmmxt_nanddi3" | |
| 100 [(set (match_operand:DI 0 "register_operand" "=y") | |
| 101 (and:DI (match_operand:DI 1 "register_operand" "y") | |
| 102 (not:DI (match_operand:DI 2 "register_operand" "y"))))] | |
| 103 "TARGET_REALLY_IWMMXT" | |
| 104 "wandn%?\\t%0, %1, %2" | |
| 111 | 105 [(set_attr "predicable" "yes") |
| 106 (set_attr "type" "wmmx_wandn")] | |
| 107 ) | |
| 0 | 108 |
| 109 (define_insn "*iwmmxt_arm_movdi" | |
| 111 | 110 [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r, r, r, m,y,y,r, y,Uy,*w, r,*w,*w, *Uv") |
| 111 (match_operand:DI 1 "di_operand" "rDa,Db,Dc,mi,r,y,r,y,Uy,y, r,*w,*w,*Uvi,*w"))] | |
| 0 | 112 "TARGET_REALLY_IWMMXT |
| 113 && ( register_operand (operands[0], DImode) | |
| 114 || register_operand (operands[1], DImode))" | |
| 115 "* | |
| 116 switch (which_alternative) | |
| 117 { | |
| 118 case 0: | |
| 111 | 119 case 1: |
| 120 case 2: | |
| 0 | 121 return \"#\"; |
| 111 | 122 case 3: case 4: |
| 123 return output_move_double (operands, true, NULL); | |
| 124 case 5: | |
| 0 | 125 return \"wmov%?\\t%0,%1\"; |
| 111 | 126 case 6: |
| 0 | 127 return \"tmcrr%?\\t%0,%Q1,%R1\"; |
| 111 | 128 case 7: |
| 0 | 129 return \"tmrrc%?\\t%Q0,%R0,%1\"; |
| 111 | 130 case 8: |
| 0 | 131 return \"wldrd%?\\t%0,%1\"; |
| 111 | 132 case 9: |
| 0 | 133 return \"wstrd%?\\t%1,%0\"; |
| 111 | 134 case 10: |
| 135 return \"fmdrr%?\\t%P0, %Q1, %R1\\t%@ int\"; | |
| 136 case 11: | |
| 137 return \"fmrrd%?\\t%Q0, %R0, %P1\\t%@ int\"; | |
| 138 case 12: | |
| 139 if (TARGET_VFP_SINGLE) | |
| 140 return \"fcpys%?\\t%0, %1\\t%@ int\;fcpys%?\\t%p0, %p1\\t%@ int\"; | |
| 141 else | |
| 142 return \"fcpyd%?\\t%P0, %P1\\t%@ int\"; | |
| 143 case 13: case 14: | |
| 144 return output_move_vfp (operands); | |
| 145 default: | |
| 146 gcc_unreachable (); | |
| 0 | 147 } |
| 111 | 148 " |
| 149 [(set (attr "length") (cond [(eq_attr "alternative" "0,3,4") (const_int 8) | |
| 150 (eq_attr "alternative" "1") (const_int 12) | |
| 151 (eq_attr "alternative" "2") (const_int 16) | |
| 152 (eq_attr "alternative" "12") | |
| 153 (if_then_else | |
| 154 (eq (symbol_ref "TARGET_VFP_SINGLE") (const_int 1)) | |
| 155 (const_int 8) | |
| 156 (const_int 4))] | |
| 157 (const_int 4))) | |
| 158 (set_attr "type" "*,*,*,load_8,store_8,*,*,*,*,*,f_mcrr,f_mrrc,\ | |
| 159 ffarithd,f_loadd,f_stored") | |
| 160 (set_attr "arm_pool_range" "*,*,*,1020,*,*,*,*,*,*,*,*,*,1020,*") | |
| 161 (set_attr "arm_neg_pool_range" "*,*,*,1008,*,*,*,*,*,*,*,*,*,1008,*")] | |
| 0 | 162 ) |
| 163 | |
| 164 (define_insn "*iwmmxt_movsi_insn" | |
| 111 | 165 [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,r,rk, m,z,r,?z,?Uy,*t, r,*t,*t ,*Uv") |
| 166 (match_operand:SI 1 "general_operand" " rk,I,K,j,mi,rk,r,z,Uy, z, r,*t,*t,*Uvi, *t"))] | |
| 0 | 167 "TARGET_REALLY_IWMMXT |
| 168 && ( register_operand (operands[0], SImode) | |
| 169 || register_operand (operands[1], SImode))" | |
| 170 "* | |
| 171 switch (which_alternative) | |
| 111 | 172 { |
| 173 case 0: return \"mov\\t%0, %1\"; | |
| 174 case 1: return \"mov\\t%0, %1\"; | |
| 175 case 2: return \"mvn\\t%0, #%B1\"; | |
| 176 case 3: return \"movw\\t%0, %1\"; | |
| 177 case 4: return \"ldr\\t%0, %1\"; | |
| 178 case 5: return \"str\\t%1, %0\"; | |
| 179 case 6: return \"tmcr\\t%0, %1\"; | |
| 180 case 7: return \"tmrc\\t%0, %1\"; | |
| 181 case 8: return arm_output_load_gr (operands); | |
| 182 case 9: return \"wstrw\\t%1, %0\"; | |
| 183 case 10:return \"fmsr\\t%0, %1\"; | |
| 184 case 11:return \"fmrs\\t%0, %1\"; | |
| 185 case 12:return \"fcpys\\t%0, %1\\t%@ int\"; | |
| 186 case 13: case 14: | |
| 187 return output_move_vfp (operands); | |
| 188 default: | |
| 189 gcc_unreachable (); | |
| 190 }" | |
| 191 [(set_attr "type" "*,*,*,*,load_4,store_4,*,*,*,*,f_mcr,f_mrc,\ | |
| 192 fmov,f_loads,f_stores") | |
| 193 (set_attr "length" "*,*,*,*,*, *,*,*, 16, *,*,*,*,*,*") | |
| 194 (set_attr "pool_range" "*,*,*,*,4096, *,*,*,1024, *,*,*,*,1020,*") | |
| 195 (set_attr "neg_pool_range" "*,*,*,*,4084, *,*,*, *, 1012,*,*,*,1008,*") | |
| 0 | 196 ;; Note - the "predicable" attribute is not allowed to have alternatives. |
| 197 ;; Since the wSTRw wCx instruction is not predicable, we cannot support | |
| 198 ;; predicating any of the alternatives in this template. Instead, | |
| 199 ;; we do the predication ourselves, in cond_iwmmxt_movsi_insn. | |
| 200 (set_attr "predicable" "no") | |
| 201 ;; Also - we have to pretend that these insns clobber the condition code | |
| 202 ;; bits as otherwise arm_final_prescan_insn() will try to conditionalize | |
| 203 ;; them. | |
| 204 (set_attr "conds" "clob")] | |
| 205 ) | |
| 206 | |
| 207 ;; Because iwmmxt_movsi_insn is not predicable, we provide the | |
| 208 ;; cond_exec version explicitly, with appropriate constraints. | |
| 209 | |
| 210 (define_insn "*cond_iwmmxt_movsi_insn" | |
| 211 [(cond_exec | |
| 212 (match_operator 2 "arm_comparison_operator" | |
| 213 [(match_operand 3 "cc_register" "") | |
| 214 (const_int 0)]) | |
| 215 (set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r, m,z,r") | |
| 216 (match_operand:SI 1 "general_operand" "rI,K,mi,r,r,z")))] | |
| 217 "TARGET_REALLY_IWMMXT | |
| 218 && ( register_operand (operands[0], SImode) | |
| 219 || register_operand (operands[1], SImode))" | |
| 220 "* | |
| 221 switch (which_alternative) | |
| 222 { | |
| 223 case 0: return \"mov%?\\t%0, %1\"; | |
| 224 case 1: return \"mvn%?\\t%0, #%B1\"; | |
| 225 case 2: return \"ldr%?\\t%0, %1\"; | |
| 226 case 3: return \"str%?\\t%1, %0\"; | |
| 227 case 4: return \"tmcr%?\\t%0, %1\"; | |
| 228 default: return \"tmrc%?\\t%0, %1\"; | |
| 229 }" | |
| 111 | 230 [(set_attr "type" "*,*,load_4,store_4,*,*") |
| 0 | 231 (set_attr "pool_range" "*,*,4096, *,*,*") |
| 232 (set_attr "neg_pool_range" "*,*,4084, *,*,*")] | |
| 233 ) | |
| 234 | |
| 235 (define_insn "mov<mode>_internal" | |
| 236 [(set (match_operand:VMMX 0 "nonimmediate_operand" "=y,m,y,?r,?y,?r,?r,?m") | |
| 237 (match_operand:VMMX 1 "general_operand" "y,y,mi,y,r,r,mi,r"))] | |
| 238 "TARGET_REALLY_IWMMXT" | |
| 239 "* | |
| 240 switch (which_alternative) | |
| 241 { | |
| 242 case 0: return \"wmov%?\\t%0, %1\"; | |
| 243 case 1: return \"wstrd%?\\t%1, %0\"; | |
| 244 case 2: return \"wldrd%?\\t%0, %1\"; | |
| 245 case 3: return \"tmrrc%?\\t%Q0, %R0, %1\"; | |
| 246 case 4: return \"tmcrr%?\\t%0, %Q1, %R1\"; | |
| 247 case 5: return \"#\"; | |
| 111 | 248 default: return output_move_double (operands, true, NULL); |
| 0 | 249 }" |
| 250 [(set_attr "predicable" "yes") | |
| 251 (set_attr "length" "4, 4, 4,4,4,8, 8,8") | |
| 111 | 252 (set_attr "type" "wmmx_wmov,wmmx_wstr,wmmx_wldr,wmmx_tmrrc,wmmx_tmcrr,*,load_4,store_4") |
| 0 | 253 (set_attr "pool_range" "*, *, 256,*,*,*, 256,*") |
| 111 | 254 (set_attr "neg_pool_range" "*, *, 244,*,*,*, 244,*")] |
| 255 ) | |
| 256 | |
| 257 (define_expand "iwmmxt_setwcgr0" | |
| 258 [(set (reg:SI WCGR0) | |
| 259 (match_operand:SI 0 "register_operand" ""))] | |
| 260 "TARGET_REALLY_IWMMXT" | |
| 261 {} | |
| 262 ) | |
| 263 | |
| 264 (define_expand "iwmmxt_setwcgr1" | |
| 265 [(set (reg:SI WCGR1) | |
| 266 (match_operand:SI 0 "register_operand" ""))] | |
| 267 "TARGET_REALLY_IWMMXT" | |
| 268 {} | |
| 269 ) | |
| 270 | |
| 271 (define_expand "iwmmxt_setwcgr2" | |
| 272 [(set (reg:SI WCGR2) | |
| 273 (match_operand:SI 0 "register_operand" ""))] | |
| 274 "TARGET_REALLY_IWMMXT" | |
| 275 {} | |
| 276 ) | |
| 277 | |
| 278 (define_expand "iwmmxt_setwcgr3" | |
| 279 [(set (reg:SI WCGR3) | |
| 280 (match_operand:SI 0 "register_operand" ""))] | |
| 281 "TARGET_REALLY_IWMMXT" | |
| 282 {} | |
| 283 ) | |
| 284 | |
| 285 (define_expand "iwmmxt_getwcgr0" | |
| 286 [(set (match_operand:SI 0 "register_operand" "") | |
| 287 (reg:SI WCGR0))] | |
| 288 "TARGET_REALLY_IWMMXT" | |
| 289 {} | |
| 290 ) | |
| 291 | |
| 292 (define_expand "iwmmxt_getwcgr1" | |
| 293 [(set (match_operand:SI 0 "register_operand" "") | |
| 294 (reg:SI WCGR1))] | |
| 295 "TARGET_REALLY_IWMMXT" | |
| 296 {} | |
| 297 ) | |
| 298 | |
| 299 (define_expand "iwmmxt_getwcgr2" | |
| 300 [(set (match_operand:SI 0 "register_operand" "") | |
| 301 (reg:SI WCGR2))] | |
| 302 "TARGET_REALLY_IWMMXT" | |
| 303 {} | |
| 304 ) | |
| 305 | |
| 306 (define_expand "iwmmxt_getwcgr3" | |
| 307 [(set (match_operand:SI 0 "register_operand" "") | |
| 308 (reg:SI WCGR3))] | |
| 309 "TARGET_REALLY_IWMMXT" | |
| 310 {} | |
| 311 ) | |
| 312 | |
| 313 (define_insn "*and<mode>3_iwmmxt" | |
| 314 [(set (match_operand:VMMX 0 "register_operand" "=y") | |
| 315 (and:VMMX (match_operand:VMMX 1 "register_operand" "y") | |
| 316 (match_operand:VMMX 2 "register_operand" "y")))] | |
| 317 "TARGET_REALLY_IWMMXT" | |
| 318 "wand\\t%0, %1, %2" | |
| 319 [(set_attr "predicable" "yes") | |
| 320 (set_attr "type" "wmmx_wand")] | |
| 321 ) | |
| 322 | |
| 323 (define_insn "*ior<mode>3_iwmmxt" | |
| 324 [(set (match_operand:VMMX 0 "register_operand" "=y") | |
| 325 (ior:VMMX (match_operand:VMMX 1 "register_operand" "y") | |
| 326 (match_operand:VMMX 2 "register_operand" "y")))] | |
| 327 "TARGET_REALLY_IWMMXT" | |
| 328 "wor\\t%0, %1, %2" | |
| 329 [(set_attr "predicable" "yes") | |
| 330 (set_attr "type" "wmmx_wor")] | |
| 331 ) | |
| 332 | |
| 333 (define_insn "*xor<mode>3_iwmmxt" | |
| 334 [(set (match_operand:VMMX 0 "register_operand" "=y") | |
| 335 (xor:VMMX (match_operand:VMMX 1 "register_operand" "y") | |
| 336 (match_operand:VMMX 2 "register_operand" "y")))] | |
| 337 "TARGET_REALLY_IWMMXT" | |
| 338 "wxor\\t%0, %1, %2" | |
| 339 [(set_attr "predicable" "yes") | |
| 340 (set_attr "type" "wmmx_wxor")] | |
| 341 ) | |
| 342 | |
| 0 | 343 |
| 344 ;; Vector add/subtract | |
| 345 | |
| 346 (define_insn "*add<mode>3_iwmmxt" | |
| 347 [(set (match_operand:VMMX 0 "register_operand" "=y") | |
| 111 | 348 (plus:VMMX (match_operand:VMMX 1 "register_operand" "y") |
| 349 (match_operand:VMMX 2 "register_operand" "y")))] | |
| 0 | 350 "TARGET_REALLY_IWMMXT" |
| 351 "wadd<MMX_char>%?\\t%0, %1, %2" | |
| 111 | 352 [(set_attr "predicable" "yes") |
| 353 (set_attr "type" "wmmx_wadd")] | |
| 354 ) | |
| 0 | 355 |
| 356 (define_insn "ssaddv8qi3" | |
| 357 [(set (match_operand:V8QI 0 "register_operand" "=y") | |
| 358 (ss_plus:V8QI (match_operand:V8QI 1 "register_operand" "y") | |
| 359 (match_operand:V8QI 2 "register_operand" "y")))] | |
| 360 "TARGET_REALLY_IWMMXT" | |
| 361 "waddbss%?\\t%0, %1, %2" | |
| 111 | 362 [(set_attr "predicable" "yes") |
| 363 (set_attr "type" "wmmx_wadd")] | |
| 364 ) | |
| 0 | 365 |
| 366 (define_insn "ssaddv4hi3" | |
| 367 [(set (match_operand:V4HI 0 "register_operand" "=y") | |
| 368 (ss_plus:V4HI (match_operand:V4HI 1 "register_operand" "y") | |
| 369 (match_operand:V4HI 2 "register_operand" "y")))] | |
| 370 "TARGET_REALLY_IWMMXT" | |
| 371 "waddhss%?\\t%0, %1, %2" | |
| 111 | 372 [(set_attr "predicable" "yes") |
| 373 (set_attr "type" "wmmx_wadd")] | |
| 374 ) | |
| 0 | 375 |
| 376 (define_insn "ssaddv2si3" | |
| 377 [(set (match_operand:V2SI 0 "register_operand" "=y") | |
| 378 (ss_plus:V2SI (match_operand:V2SI 1 "register_operand" "y") | |
| 379 (match_operand:V2SI 2 "register_operand" "y")))] | |
| 380 "TARGET_REALLY_IWMMXT" | |
| 381 "waddwss%?\\t%0, %1, %2" | |
| 111 | 382 [(set_attr "predicable" "yes") |
| 383 (set_attr "type" "wmmx_wadd")] | |
| 384 ) | |
| 0 | 385 |
| 386 (define_insn "usaddv8qi3" | |
| 387 [(set (match_operand:V8QI 0 "register_operand" "=y") | |
| 388 (us_plus:V8QI (match_operand:V8QI 1 "register_operand" "y") | |
| 389 (match_operand:V8QI 2 "register_operand" "y")))] | |
| 390 "TARGET_REALLY_IWMMXT" | |
| 391 "waddbus%?\\t%0, %1, %2" | |
| 111 | 392 [(set_attr "predicable" "yes") |
| 393 (set_attr "type" "wmmx_wadd")] | |
| 394 ) | |
| 0 | 395 |
| 396 (define_insn "usaddv4hi3" | |
| 397 [(set (match_operand:V4HI 0 "register_operand" "=y") | |
| 398 (us_plus:V4HI (match_operand:V4HI 1 "register_operand" "y") | |
| 399 (match_operand:V4HI 2 "register_operand" "y")))] | |
| 400 "TARGET_REALLY_IWMMXT" | |
| 401 "waddhus%?\\t%0, %1, %2" | |
| 111 | 402 [(set_attr "predicable" "yes") |
| 403 (set_attr "type" "wmmx_wadd")] | |
| 404 ) | |
| 0 | 405 |
| 406 (define_insn "usaddv2si3" | |
| 407 [(set (match_operand:V2SI 0 "register_operand" "=y") | |
| 408 (us_plus:V2SI (match_operand:V2SI 1 "register_operand" "y") | |
| 409 (match_operand:V2SI 2 "register_operand" "y")))] | |
| 410 "TARGET_REALLY_IWMMXT" | |
| 411 "waddwus%?\\t%0, %1, %2" | |
| 111 | 412 [(set_attr "predicable" "yes") |
| 413 (set_attr "type" "wmmx_wadd")] | |
| 414 ) | |
| 0 | 415 |
| 416 (define_insn "*sub<mode>3_iwmmxt" | |
| 417 [(set (match_operand:VMMX 0 "register_operand" "=y") | |
| 418 (minus:VMMX (match_operand:VMMX 1 "register_operand" "y") | |
| 419 (match_operand:VMMX 2 "register_operand" "y")))] | |
| 420 "TARGET_REALLY_IWMMXT" | |
| 421 "wsub<MMX_char>%?\\t%0, %1, %2" | |
| 111 | 422 [(set_attr "predicable" "yes") |
| 423 (set_attr "type" "wmmx_wsub")] | |
| 424 ) | |
| 0 | 425 |
| 426 (define_insn "sssubv8qi3" | |
| 427 [(set (match_operand:V8QI 0 "register_operand" "=y") | |
| 428 (ss_minus:V8QI (match_operand:V8QI 1 "register_operand" "y") | |
| 429 (match_operand:V8QI 2 "register_operand" "y")))] | |
| 430 "TARGET_REALLY_IWMMXT" | |
| 431 "wsubbss%?\\t%0, %1, %2" | |
| 111 | 432 [(set_attr "predicable" "yes") |
| 433 (set_attr "type" "wmmx_wsub")] | |
| 434 ) | |
| 0 | 435 |
| 436 (define_insn "sssubv4hi3" | |
| 437 [(set (match_operand:V4HI 0 "register_operand" "=y") | |
| 438 (ss_minus:V4HI (match_operand:V4HI 1 "register_operand" "y") | |
| 439 (match_operand:V4HI 2 "register_operand" "y")))] | |
| 440 "TARGET_REALLY_IWMMXT" | |
| 441 "wsubhss%?\\t%0, %1, %2" | |
| 111 | 442 [(set_attr "predicable" "yes") |
| 443 (set_attr "type" "wmmx_wsub")] | |
| 444 ) | |
| 0 | 445 |
| 446 (define_insn "sssubv2si3" | |
| 447 [(set (match_operand:V2SI 0 "register_operand" "=y") | |
| 448 (ss_minus:V2SI (match_operand:V2SI 1 "register_operand" "y") | |
| 449 (match_operand:V2SI 2 "register_operand" "y")))] | |
| 450 "TARGET_REALLY_IWMMXT" | |
| 451 "wsubwss%?\\t%0, %1, %2" | |
| 111 | 452 [(set_attr "predicable" "yes") |
| 453 (set_attr "type" "wmmx_wsub")] | |
| 454 ) | |
| 0 | 455 |
| 456 (define_insn "ussubv8qi3" | |
| 457 [(set (match_operand:V8QI 0 "register_operand" "=y") | |
| 458 (us_minus:V8QI (match_operand:V8QI 1 "register_operand" "y") | |
| 459 (match_operand:V8QI 2 "register_operand" "y")))] | |
| 460 "TARGET_REALLY_IWMMXT" | |
| 461 "wsubbus%?\\t%0, %1, %2" | |
| 111 | 462 [(set_attr "predicable" "yes") |
| 463 (set_attr "type" "wmmx_wsub")] | |
| 464 ) | |
| 0 | 465 |
| 466 (define_insn "ussubv4hi3" | |
| 467 [(set (match_operand:V4HI 0 "register_operand" "=y") | |
| 468 (us_minus:V4HI (match_operand:V4HI 1 "register_operand" "y") | |
| 469 (match_operand:V4HI 2 "register_operand" "y")))] | |
| 470 "TARGET_REALLY_IWMMXT" | |
| 471 "wsubhus%?\\t%0, %1, %2" | |
| 111 | 472 [(set_attr "predicable" "yes") |
| 473 (set_attr "type" "wmmx_wsub")] | |
| 474 ) | |
| 0 | 475 |
| 476 (define_insn "ussubv2si3" | |
| 477 [(set (match_operand:V2SI 0 "register_operand" "=y") | |
| 478 (us_minus:V2SI (match_operand:V2SI 1 "register_operand" "y") | |
| 479 (match_operand:V2SI 2 "register_operand" "y")))] | |
| 480 "TARGET_REALLY_IWMMXT" | |
| 481 "wsubwus%?\\t%0, %1, %2" | |
| 111 | 482 [(set_attr "predicable" "yes") |
| 483 (set_attr "type" "wmmx_wsub")] | |
| 484 ) | |
| 0 | 485 |
| 486 (define_insn "*mulv4hi3_iwmmxt" | |
| 487 [(set (match_operand:V4HI 0 "register_operand" "=y") | |
| 488 (mult:V4HI (match_operand:V4HI 1 "register_operand" "y") | |
| 489 (match_operand:V4HI 2 "register_operand" "y")))] | |
| 490 "TARGET_REALLY_IWMMXT" | |
| 491 "wmulul%?\\t%0, %1, %2" | |
| 111 | 492 [(set_attr "predicable" "yes") |
| 493 (set_attr "type" "wmmx_wmul")] | |
| 494 ) | |
| 0 | 495 |
| 496 (define_insn "smulv4hi3_highpart" | |
| 111 | 497 [(set (match_operand:V4HI 0 "register_operand" "=y") |
| 498 (truncate:V4HI | |
| 499 (lshiftrt:V4SI | |
| 500 (mult:V4SI (sign_extend:V4SI (match_operand:V4HI 1 "register_operand" "y")) | |
| 501 (sign_extend:V4SI (match_operand:V4HI 2 "register_operand" "y"))) | |
| 502 (const_int 16))))] | |
| 0 | 503 "TARGET_REALLY_IWMMXT" |
| 504 "wmulsm%?\\t%0, %1, %2" | |
| 111 | 505 [(set_attr "predicable" "yes") |
| 506 (set_attr "type" "wmmx_wmul")] | |
| 507 ) | |
| 0 | 508 |
| 509 (define_insn "umulv4hi3_highpart" | |
| 111 | 510 [(set (match_operand:V4HI 0 "register_operand" "=y") |
| 511 (truncate:V4HI | |
| 512 (lshiftrt:V4SI | |
| 513 (mult:V4SI (zero_extend:V4SI (match_operand:V4HI 1 "register_operand" "y")) | |
| 514 (zero_extend:V4SI (match_operand:V4HI 2 "register_operand" "y"))) | |
| 515 (const_int 16))))] | |
| 0 | 516 "TARGET_REALLY_IWMMXT" |
| 517 "wmulum%?\\t%0, %1, %2" | |
| 111 | 518 [(set_attr "predicable" "yes") |
| 519 (set_attr "type" "wmmx_wmul")] | |
| 520 ) | |
| 0 | 521 |
| 522 (define_insn "iwmmxt_wmacs" | |
| 523 [(set (match_operand:DI 0 "register_operand" "=y") | |
| 524 (unspec:DI [(match_operand:DI 1 "register_operand" "0") | |
| 111 | 525 (match_operand:V4HI 2 "register_operand" "y") |
| 526 (match_operand:V4HI 3 "register_operand" "y")] UNSPEC_WMACS))] | |
| 0 | 527 "TARGET_REALLY_IWMMXT" |
| 528 "wmacs%?\\t%0, %2, %3" | |
| 111 | 529 [(set_attr "predicable" "yes") |
| 530 (set_attr "type" "wmmx_wmac")] | |
| 531 ) | |
| 0 | 532 |
| 533 (define_insn "iwmmxt_wmacsz" | |
| 534 [(set (match_operand:DI 0 "register_operand" "=y") | |
| 535 (unspec:DI [(match_operand:V4HI 1 "register_operand" "y") | |
| 111 | 536 (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WMACSZ))] |
| 0 | 537 "TARGET_REALLY_IWMMXT" |
| 538 "wmacsz%?\\t%0, %1, %2" | |
| 111 | 539 [(set_attr "predicable" "yes") |
| 540 (set_attr "type" "wmmx_wmac")] | |
| 541 ) | |
| 0 | 542 |
| 543 (define_insn "iwmmxt_wmacu" | |
| 544 [(set (match_operand:DI 0 "register_operand" "=y") | |
| 545 (unspec:DI [(match_operand:DI 1 "register_operand" "0") | |
| 111 | 546 (match_operand:V4HI 2 "register_operand" "y") |
| 547 (match_operand:V4HI 3 "register_operand" "y")] UNSPEC_WMACU))] | |
| 0 | 548 "TARGET_REALLY_IWMMXT" |
| 549 "wmacu%?\\t%0, %2, %3" | |
| 111 | 550 [(set_attr "predicable" "yes") |
| 551 (set_attr "type" "wmmx_wmac")] | |
| 552 ) | |
| 0 | 553 |
| 554 (define_insn "iwmmxt_wmacuz" | |
| 555 [(set (match_operand:DI 0 "register_operand" "=y") | |
| 556 (unspec:DI [(match_operand:V4HI 1 "register_operand" "y") | |
| 111 | 557 (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WMACUZ))] |
| 0 | 558 "TARGET_REALLY_IWMMXT" |
| 559 "wmacuz%?\\t%0, %1, %2" | |
| 111 | 560 [(set_attr "predicable" "yes") |
| 561 (set_attr "type" "wmmx_wmac")] | |
| 562 ) | |
| 0 | 563 |
| 564 ;; Same as xordi3, but don't show input operands so that we don't think | |
| 565 ;; they are live. | |
| 566 (define_insn "iwmmxt_clrdi" | |
| 567 [(set (match_operand:DI 0 "register_operand" "=y") | |
| 568 (unspec:DI [(const_int 0)] UNSPEC_CLRDI))] | |
| 569 "TARGET_REALLY_IWMMXT" | |
| 570 "wxor%?\\t%0, %0, %0" | |
| 111 | 571 [(set_attr "predicable" "yes") |
| 572 (set_attr "type" "wmmx_wxor")] | |
| 573 ) | |
| 0 | 574 |
| 575 ;; Seems like cse likes to generate these, so we have to support them. | |
| 576 | |
| 111 | 577 (define_insn "iwmmxt_clrv8qi" |
| 578 [(set (match_operand:V8QI 0 "s_register_operand" "=y") | |
| 0 | 579 (const_vector:V8QI [(const_int 0) (const_int 0) |
| 580 (const_int 0) (const_int 0) | |
| 581 (const_int 0) (const_int 0) | |
| 582 (const_int 0) (const_int 0)]))] | |
| 583 "TARGET_REALLY_IWMMXT" | |
| 584 "wxor%?\\t%0, %0, %0" | |
| 111 | 585 [(set_attr "predicable" "yes") |
| 586 (set_attr "type" "wmmx_wxor")] | |
| 587 ) | |
| 0 | 588 |
| 111 | 589 (define_insn "iwmmxt_clrv4hi" |
| 590 [(set (match_operand:V4HI 0 "s_register_operand" "=y") | |
| 0 | 591 (const_vector:V4HI [(const_int 0) (const_int 0) |
| 592 (const_int 0) (const_int 0)]))] | |
| 593 "TARGET_REALLY_IWMMXT" | |
| 594 "wxor%?\\t%0, %0, %0" | |
| 111 | 595 [(set_attr "predicable" "yes") |
| 596 (set_attr "type" "wmmx_wxor")] | |
| 597 ) | |
| 0 | 598 |
| 111 | 599 (define_insn "iwmmxt_clrv2si" |
| 0 | 600 [(set (match_operand:V2SI 0 "register_operand" "=y") |
| 601 (const_vector:V2SI [(const_int 0) (const_int 0)]))] | |
| 602 "TARGET_REALLY_IWMMXT" | |
| 603 "wxor%?\\t%0, %0, %0" | |
| 111 | 604 [(set_attr "predicable" "yes") |
| 605 (set_attr "type" "wmmx_wxor")] | |
| 606 ) | |
| 0 | 607 |
| 608 ;; Unsigned averages/sum of absolute differences | |
| 609 | |
| 610 (define_insn "iwmmxt_uavgrndv8qi3" | |
| 111 | 611 [(set (match_operand:V8QI 0 "register_operand" "=y") |
| 612 (truncate:V8QI | |
| 613 (lshiftrt:V8HI | |
| 614 (plus:V8HI | |
| 615 (plus:V8HI (zero_extend:V8HI (match_operand:V8QI 1 "register_operand" "y")) | |
| 616 (zero_extend:V8HI (match_operand:V8QI 2 "register_operand" "y"))) | |
| 617 (const_vector:V8HI [(const_int 1) | |
| 618 (const_int 1) | |
| 619 (const_int 1) | |
| 620 (const_int 1) | |
| 621 (const_int 1) | |
| 622 (const_int 1) | |
| 623 (const_int 1) | |
| 624 (const_int 1)])) | |
| 625 (const_int 1))))] | |
| 0 | 626 "TARGET_REALLY_IWMMXT" |
| 627 "wavg2br%?\\t%0, %1, %2" | |
| 111 | 628 [(set_attr "predicable" "yes") |
| 629 (set_attr "type" "wmmx_wavg2")] | |
| 630 ) | |
| 0 | 631 |
| 632 (define_insn "iwmmxt_uavgrndv4hi3" | |
| 111 | 633 [(set (match_operand:V4HI 0 "register_operand" "=y") |
| 634 (truncate:V4HI | |
| 635 (lshiftrt:V4SI | |
| 636 (plus:V4SI | |
| 637 (plus:V4SI (zero_extend:V4SI (match_operand:V4HI 1 "register_operand" "y")) | |
| 638 (zero_extend:V4SI (match_operand:V4HI 2 "register_operand" "y"))) | |
| 639 (const_vector:V4SI [(const_int 1) | |
| 640 (const_int 1) | |
| 641 (const_int 1) | |
| 642 (const_int 1)])) | |
| 643 (const_int 1))))] | |
| 0 | 644 "TARGET_REALLY_IWMMXT" |
| 645 "wavg2hr%?\\t%0, %1, %2" | |
| 111 | 646 [(set_attr "predicable" "yes") |
| 647 (set_attr "type" "wmmx_wavg2")] | |
| 648 ) | |
| 0 | 649 |
| 650 (define_insn "iwmmxt_uavgv8qi3" | |
| 111 | 651 [(set (match_operand:V8QI 0 "register_operand" "=y") |
| 652 (truncate:V8QI | |
| 653 (lshiftrt:V8HI | |
| 654 (plus:V8HI (zero_extend:V8HI (match_operand:V8QI 1 "register_operand" "y")) | |
| 655 (zero_extend:V8HI (match_operand:V8QI 2 "register_operand" "y"))) | |
| 656 (const_int 1))))] | |
| 0 | 657 "TARGET_REALLY_IWMMXT" |
| 658 "wavg2b%?\\t%0, %1, %2" | |
| 111 | 659 [(set_attr "predicable" "yes") |
| 660 (set_attr "type" "wmmx_wavg2")] | |
| 661 ) | |
| 0 | 662 |
| 663 (define_insn "iwmmxt_uavgv4hi3" | |
| 111 | 664 [(set (match_operand:V4HI 0 "register_operand" "=y") |
| 665 (truncate:V4HI | |
| 666 (lshiftrt:V4SI | |
| 667 (plus:V4SI (zero_extend:V4SI (match_operand:V4HI 1 "register_operand" "y")) | |
| 668 (zero_extend:V4SI (match_operand:V4HI 2 "register_operand" "y"))) | |
| 669 (const_int 1))))] | |
| 0 | 670 "TARGET_REALLY_IWMMXT" |
| 671 "wavg2h%?\\t%0, %1, %2" | |
| 111 | 672 [(set_attr "predicable" "yes") |
| 673 (set_attr "type" "wmmx_wavg2")] | |
| 674 ) | |
| 0 | 675 |
| 676 ;; Insert/extract/shuffle | |
| 677 | |
| 678 (define_insn "iwmmxt_tinsrb" | |
| 111 | 679 [(set (match_operand:V8QI 0 "register_operand" "=y") |
| 680 (vec_merge:V8QI | |
| 681 (vec_duplicate:V8QI | |
| 682 (truncate:QI (match_operand:SI 2 "nonimmediate_operand" "r"))) | |
| 683 (match_operand:V8QI 1 "register_operand" "0") | |
| 684 (match_operand:SI 3 "immediate_operand" "i")))] | |
| 0 | 685 "TARGET_REALLY_IWMMXT" |
| 111 | 686 "* |
| 687 { | |
| 688 return arm_output_iwmmxt_tinsr (operands); | |
| 689 } | |
| 690 " | |
| 691 [(set_attr "predicable" "yes") | |
| 692 (set_attr "type" "wmmx_tinsr")] | |
| 693 ) | |
| 0 | 694 |
| 695 (define_insn "iwmmxt_tinsrh" | |
| 111 | 696 [(set (match_operand:V4HI 0 "register_operand" "=y") |
| 697 (vec_merge:V4HI | |
| 698 (vec_duplicate:V4HI | |
| 699 (truncate:HI (match_operand:SI 2 "nonimmediate_operand" "r"))) | |
| 700 (match_operand:V4HI 1 "register_operand" "0") | |
| 701 (match_operand:SI 3 "immediate_operand" "i")))] | |
| 0 | 702 "TARGET_REALLY_IWMMXT" |
| 111 | 703 "* |
| 704 { | |
| 705 return arm_output_iwmmxt_tinsr (operands); | |
| 706 } | |
| 707 " | |
| 708 [(set_attr "predicable" "yes") | |
| 709 (set_attr "type" "wmmx_tinsr")] | |
| 710 ) | |
| 0 | 711 |
| 712 (define_insn "iwmmxt_tinsrw" | |
| 111 | 713 [(set (match_operand:V2SI 0 "register_operand" "=y") |
| 714 (vec_merge:V2SI | |
| 715 (vec_duplicate:V2SI | |
| 716 (match_operand:SI 2 "nonimmediate_operand" "r")) | |
| 717 (match_operand:V2SI 1 "register_operand" "0") | |
| 718 (match_operand:SI 3 "immediate_operand" "i")))] | |
| 0 | 719 "TARGET_REALLY_IWMMXT" |
| 111 | 720 "* |
| 721 { | |
| 722 return arm_output_iwmmxt_tinsr (operands); | |
| 723 } | |
| 724 " | |
| 725 [(set_attr "predicable" "yes") | |
| 726 (set_attr "type" "wmmx_tinsr")] | |
| 727 ) | |
| 0 | 728 |
| 729 (define_insn "iwmmxt_textrmub" | |
| 111 | 730 [(set (match_operand:SI 0 "register_operand" "=r") |
| 731 (zero_extend:SI (vec_select:QI (match_operand:V8QI 1 "register_operand" "y") | |
| 732 (parallel | |
| 733 [(match_operand:SI 2 "immediate_operand" "i")]))))] | |
| 0 | 734 "TARGET_REALLY_IWMMXT" |
| 735 "textrmub%?\\t%0, %1, %2" | |
| 111 | 736 [(set_attr "predicable" "yes") |
| 737 (set_attr "type" "wmmx_textrm")] | |
| 738 ) | |
| 0 | 739 |
| 740 (define_insn "iwmmxt_textrmsb" | |
| 111 | 741 [(set (match_operand:SI 0 "register_operand" "=r") |
| 742 (sign_extend:SI (vec_select:QI (match_operand:V8QI 1 "register_operand" "y") | |
| 0 | 743 (parallel |
| 111 | 744 [(match_operand:SI 2 "immediate_operand" "i")]))))] |
| 0 | 745 "TARGET_REALLY_IWMMXT" |
| 746 "textrmsb%?\\t%0, %1, %2" | |
| 111 | 747 [(set_attr "predicable" "yes") |
| 748 (set_attr "type" "wmmx_textrm")] | |
| 749 ) | |
| 0 | 750 |
| 751 (define_insn "iwmmxt_textrmuh" | |
| 111 | 752 [(set (match_operand:SI 0 "register_operand" "=r") |
| 753 (zero_extend:SI (vec_select:HI (match_operand:V4HI 1 "register_operand" "y") | |
| 0 | 754 (parallel |
| 111 | 755 [(match_operand:SI 2 "immediate_operand" "i")]))))] |
| 0 | 756 "TARGET_REALLY_IWMMXT" |
| 757 "textrmuh%?\\t%0, %1, %2" | |
| 111 | 758 [(set_attr "predicable" "yes") |
| 759 (set_attr "type" "wmmx_textrm")] | |
| 760 ) | |
| 0 | 761 |
| 762 (define_insn "iwmmxt_textrmsh" | |
| 111 | 763 [(set (match_operand:SI 0 "register_operand" "=r") |
| 764 (sign_extend:SI (vec_select:HI (match_operand:V4HI 1 "register_operand" "y") | |
| 0 | 765 (parallel |
| 111 | 766 [(match_operand:SI 2 "immediate_operand" "i")]))))] |
| 0 | 767 "TARGET_REALLY_IWMMXT" |
| 768 "textrmsh%?\\t%0, %1, %2" | |
| 111 | 769 [(set_attr "predicable" "yes") |
| 770 (set_attr "type" "wmmx_textrm")] | |
| 771 ) | |
| 0 | 772 |
| 773 ;; There are signed/unsigned variants of this instruction, but they are | |
| 774 ;; pointless. | |
| 775 (define_insn "iwmmxt_textrmw" | |
| 776 [(set (match_operand:SI 0 "register_operand" "=r") | |
| 777 (vec_select:SI (match_operand:V2SI 1 "register_operand" "y") | |
| 778 (parallel [(match_operand:SI 2 "immediate_operand" "i")])))] | |
| 779 "TARGET_REALLY_IWMMXT" | |
| 780 "textrmsw%?\\t%0, %1, %2" | |
| 111 | 781 [(set_attr "predicable" "yes") |
| 782 (set_attr "type" "wmmx_textrm")] | |
| 783 ) | |
| 0 | 784 |
| 785 (define_insn "iwmmxt_wshufh" | |
| 786 [(set (match_operand:V4HI 0 "register_operand" "=y") | |
| 787 (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "y") | |
| 788 (match_operand:SI 2 "immediate_operand" "i")] UNSPEC_WSHUFH))] | |
| 789 "TARGET_REALLY_IWMMXT" | |
| 790 "wshufh%?\\t%0, %1, %2" | |
| 111 | 791 [(set_attr "predicable" "yes") |
| 792 (set_attr "type" "wmmx_wshufh")] | |
| 793 ) | |
| 0 | 794 |
| 795 ;; Mask-generating comparisons | |
| 796 ;; | |
| 797 ;; Note - you cannot use patterns like these here: | |
| 798 ;; | |
|
67
f6334be47118
update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents:
0
diff
changeset
|
799 ;; (set (match:<vector>) (<comparator>:<vector> (match:<vector>) (match:<vector>))) |
| 0 | 800 ;; |
| 801 ;; Because GCC will assume that the truth value (1 or 0) is installed | |
| 802 ;; into the entire destination vector, (with the '1' going into the least | |
| 803 ;; significant element of the vector). This is not how these instructions | |
| 804 ;; behave. | |
| 805 | |
| 806 (define_insn "eqv8qi3" | |
| 111 | 807 [(set (match_operand:V8QI 0 "register_operand" "=y") |
| 808 (unspec_volatile:V8QI [(match_operand:V8QI 1 "register_operand" "y") | |
| 809 (match_operand:V8QI 2 "register_operand" "y")] | |
| 810 VUNSPEC_WCMP_EQ))] | |
| 0 | 811 "TARGET_REALLY_IWMMXT" |
| 812 "wcmpeqb%?\\t%0, %1, %2" | |
| 111 | 813 [(set_attr "predicable" "yes") |
| 814 (set_attr "type" "wmmx_wcmpeq")] | |
| 815 ) | |
| 0 | 816 |
| 817 (define_insn "eqv4hi3" | |
| 111 | 818 [(set (match_operand:V4HI 0 "register_operand" "=y") |
| 819 (unspec_volatile:V4HI [(match_operand:V4HI 1 "register_operand" "y") | |
| 820 (match_operand:V4HI 2 "register_operand" "y")] | |
| 821 VUNSPEC_WCMP_EQ))] | |
| 0 | 822 "TARGET_REALLY_IWMMXT" |
| 823 "wcmpeqh%?\\t%0, %1, %2" | |
| 111 | 824 [(set_attr "predicable" "yes") |
| 825 (set_attr "type" "wmmx_wcmpeq")] | |
| 826 ) | |
| 0 | 827 |
| 828 (define_insn "eqv2si3" | |
| 111 | 829 [(set (match_operand:V2SI 0 "register_operand" "=y") |
| 830 (unspec_volatile:V2SI | |
| 831 [(match_operand:V2SI 1 "register_operand" "y") | |
| 832 (match_operand:V2SI 2 "register_operand" "y")] | |
| 833 VUNSPEC_WCMP_EQ))] | |
| 0 | 834 "TARGET_REALLY_IWMMXT" |
| 835 "wcmpeqw%?\\t%0, %1, %2" | |
| 111 | 836 [(set_attr "predicable" "yes") |
| 837 (set_attr "type" "wmmx_wcmpeq")] | |
| 838 ) | |
| 0 | 839 |
| 840 (define_insn "gtuv8qi3" | |
| 111 | 841 [(set (match_operand:V8QI 0 "register_operand" "=y") |
| 842 (unspec_volatile:V8QI [(match_operand:V8QI 1 "register_operand" "y") | |
| 843 (match_operand:V8QI 2 "register_operand" "y")] | |
| 844 VUNSPEC_WCMP_GTU))] | |
| 0 | 845 "TARGET_REALLY_IWMMXT" |
| 846 "wcmpgtub%?\\t%0, %1, %2" | |
| 111 | 847 [(set_attr "predicable" "yes") |
| 848 (set_attr "type" "wmmx_wcmpgt")] | |
| 849 ) | |
| 0 | 850 |
| 851 (define_insn "gtuv4hi3" | |
| 111 | 852 [(set (match_operand:V4HI 0 "register_operand" "=y") |
| 853 (unspec_volatile:V4HI [(match_operand:V4HI 1 "register_operand" "y") | |
| 854 (match_operand:V4HI 2 "register_operand" "y")] | |
| 855 VUNSPEC_WCMP_GTU))] | |
| 0 | 856 "TARGET_REALLY_IWMMXT" |
| 857 "wcmpgtuh%?\\t%0, %1, %2" | |
| 111 | 858 [(set_attr "predicable" "yes") |
| 859 (set_attr "type" "wmmx_wcmpgt")] | |
| 860 ) | |
| 0 | 861 |
| 862 (define_insn "gtuv2si3" | |
| 111 | 863 [(set (match_operand:V2SI 0 "register_operand" "=y") |
| 864 (unspec_volatile:V2SI [(match_operand:V2SI 1 "register_operand" "y") | |
| 865 (match_operand:V2SI 2 "register_operand" "y")] | |
| 866 VUNSPEC_WCMP_GTU))] | |
| 0 | 867 "TARGET_REALLY_IWMMXT" |
| 868 "wcmpgtuw%?\\t%0, %1, %2" | |
| 111 | 869 [(set_attr "predicable" "yes") |
| 870 (set_attr "type" "wmmx_wcmpgt")] | |
| 871 ) | |
| 0 | 872 |
| 873 (define_insn "gtv8qi3" | |
| 111 | 874 [(set (match_operand:V8QI 0 "register_operand" "=y") |
| 875 (unspec_volatile:V8QI [(match_operand:V8QI 1 "register_operand" "y") | |
| 876 (match_operand:V8QI 2 "register_operand" "y")] | |
| 877 VUNSPEC_WCMP_GT))] | |
| 0 | 878 "TARGET_REALLY_IWMMXT" |
| 879 "wcmpgtsb%?\\t%0, %1, %2" | |
| 111 | 880 [(set_attr "predicable" "yes") |
| 881 (set_attr "type" "wmmx_wcmpgt")] | |
| 882 ) | |
| 0 | 883 |
| 884 (define_insn "gtv4hi3" | |
| 111 | 885 [(set (match_operand:V4HI 0 "register_operand" "=y") |
| 886 (unspec_volatile:V4HI [(match_operand:V4HI 1 "register_operand" "y") | |
| 887 (match_operand:V4HI 2 "register_operand" "y")] | |
| 888 VUNSPEC_WCMP_GT))] | |
| 0 | 889 "TARGET_REALLY_IWMMXT" |
| 890 "wcmpgtsh%?\\t%0, %1, %2" | |
| 111 | 891 [(set_attr "predicable" "yes") |
| 892 (set_attr "type" "wmmx_wcmpgt")] | |
| 893 ) | |
| 0 | 894 |
| 895 (define_insn "gtv2si3" | |
| 111 | 896 [(set (match_operand:V2SI 0 "register_operand" "=y") |
| 897 (unspec_volatile:V2SI [(match_operand:V2SI 1 "register_operand" "y") | |
| 898 (match_operand:V2SI 2 "register_operand" "y")] | |
| 899 VUNSPEC_WCMP_GT))] | |
| 0 | 900 "TARGET_REALLY_IWMMXT" |
| 901 "wcmpgtsw%?\\t%0, %1, %2" | |
| 111 | 902 [(set_attr "predicable" "yes") |
| 903 (set_attr "type" "wmmx_wcmpgt")] | |
| 904 ) | |
| 0 | 905 |
| 906 ;; Max/min insns | |
| 907 | |
| 908 (define_insn "*smax<mode>3_iwmmxt" | |
| 909 [(set (match_operand:VMMX 0 "register_operand" "=y") | |
| 910 (smax:VMMX (match_operand:VMMX 1 "register_operand" "y") | |
| 911 (match_operand:VMMX 2 "register_operand" "y")))] | |
| 912 "TARGET_REALLY_IWMMXT" | |
| 913 "wmaxs<MMX_char>%?\\t%0, %1, %2" | |
| 111 | 914 [(set_attr "predicable" "yes") |
| 915 (set_attr "type" "wmmx_wmax")] | |
| 916 ) | |
| 0 | 917 |
| 918 (define_insn "*umax<mode>3_iwmmxt" | |
| 919 [(set (match_operand:VMMX 0 "register_operand" "=y") | |
| 920 (umax:VMMX (match_operand:VMMX 1 "register_operand" "y") | |
| 921 (match_operand:VMMX 2 "register_operand" "y")))] | |
| 922 "TARGET_REALLY_IWMMXT" | |
| 923 "wmaxu<MMX_char>%?\\t%0, %1, %2" | |
| 111 | 924 [(set_attr "predicable" "yes") |
| 925 (set_attr "type" "wmmx_wmax")] | |
| 926 ) | |
| 0 | 927 |
| 928 (define_insn "*smin<mode>3_iwmmxt" | |
| 929 [(set (match_operand:VMMX 0 "register_operand" "=y") | |
| 930 (smin:VMMX (match_operand:VMMX 1 "register_operand" "y") | |
| 931 (match_operand:VMMX 2 "register_operand" "y")))] | |
| 932 "TARGET_REALLY_IWMMXT" | |
| 933 "wmins<MMX_char>%?\\t%0, %1, %2" | |
| 111 | 934 [(set_attr "predicable" "yes") |
| 935 (set_attr "type" "wmmx_wmin")] | |
| 936 ) | |
| 0 | 937 |
| 938 (define_insn "*umin<mode>3_iwmmxt" | |
| 939 [(set (match_operand:VMMX 0 "register_operand" "=y") | |
| 940 (umin:VMMX (match_operand:VMMX 1 "register_operand" "y") | |
| 941 (match_operand:VMMX 2 "register_operand" "y")))] | |
| 942 "TARGET_REALLY_IWMMXT" | |
| 943 "wminu<MMX_char>%?\\t%0, %1, %2" | |
| 111 | 944 [(set_attr "predicable" "yes") |
| 945 (set_attr "type" "wmmx_wmin")] | |
| 946 ) | |
| 0 | 947 |
| 948 ;; Pack/unpack insns. | |
| 949 | |
| 950 (define_insn "iwmmxt_wpackhss" | |
| 111 | 951 [(set (match_operand:V8QI 0 "register_operand" "=y") |
| 0 | 952 (vec_concat:V8QI |
| 111 | 953 (ss_truncate:V4QI (match_operand:V4HI 1 "register_operand" "y")) |
| 954 (ss_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))] | |
| 0 | 955 "TARGET_REALLY_IWMMXT" |
| 956 "wpackhss%?\\t%0, %1, %2" | |
| 111 | 957 [(set_attr "predicable" "yes") |
| 958 (set_attr "type" "wmmx_wpack")] | |
| 959 ) | |
| 0 | 960 |
| 961 (define_insn "iwmmxt_wpackwss" | |
| 111 | 962 [(set (match_operand:V4HI 0 "register_operand" "=y") |
| 963 (vec_concat:V4HI | |
| 964 (ss_truncate:V2HI (match_operand:V2SI 1 "register_operand" "y")) | |
| 965 (ss_truncate:V2HI (match_operand:V2SI 2 "register_operand" "y"))))] | |
| 0 | 966 "TARGET_REALLY_IWMMXT" |
| 967 "wpackwss%?\\t%0, %1, %2" | |
| 111 | 968 [(set_attr "predicable" "yes") |
| 969 (set_attr "type" "wmmx_wpack")] | |
| 970 ) | |
| 0 | 971 |
| 972 (define_insn "iwmmxt_wpackdss" | |
| 111 | 973 [(set (match_operand:V2SI 0 "register_operand" "=y") |
| 0 | 974 (vec_concat:V2SI |
| 111 | 975 (ss_truncate:SI (match_operand:DI 1 "register_operand" "y")) |
| 976 (ss_truncate:SI (match_operand:DI 2 "register_operand" "y"))))] | |
| 0 | 977 "TARGET_REALLY_IWMMXT" |
| 978 "wpackdss%?\\t%0, %1, %2" | |
| 111 | 979 [(set_attr "predicable" "yes") |
| 980 (set_attr "type" "wmmx_wpack")] | |
| 981 ) | |
| 0 | 982 |
| 983 (define_insn "iwmmxt_wpackhus" | |
| 111 | 984 [(set (match_operand:V8QI 0 "register_operand" "=y") |
| 0 | 985 (vec_concat:V8QI |
| 111 | 986 (us_truncate:V4QI (match_operand:V4HI 1 "register_operand" "y")) |
| 987 (us_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))] | |
| 0 | 988 "TARGET_REALLY_IWMMXT" |
| 989 "wpackhus%?\\t%0, %1, %2" | |
| 111 | 990 [(set_attr "predicable" "yes") |
| 991 (set_attr "type" "wmmx_wpack")] | |
| 992 ) | |
| 0 | 993 |
| 994 (define_insn "iwmmxt_wpackwus" | |
| 111 | 995 [(set (match_operand:V4HI 0 "register_operand" "=y") |
| 0 | 996 (vec_concat:V4HI |
| 111 | 997 (us_truncate:V2HI (match_operand:V2SI 1 "register_operand" "y")) |
| 998 (us_truncate:V2HI (match_operand:V2SI 2 "register_operand" "y"))))] | |
| 0 | 999 "TARGET_REALLY_IWMMXT" |
| 1000 "wpackwus%?\\t%0, %1, %2" | |
| 111 | 1001 [(set_attr "predicable" "yes") |
| 1002 (set_attr "type" "wmmx_wpack")] | |
| 1003 ) | |
| 0 | 1004 |
| 1005 (define_insn "iwmmxt_wpackdus" | |
| 111 | 1006 [(set (match_operand:V2SI 0 "register_operand" "=y") |
| 0 | 1007 (vec_concat:V2SI |
| 111 | 1008 (us_truncate:SI (match_operand:DI 1 "register_operand" "y")) |
| 1009 (us_truncate:SI (match_operand:DI 2 "register_operand" "y"))))] | |
| 0 | 1010 "TARGET_REALLY_IWMMXT" |
| 1011 "wpackdus%?\\t%0, %1, %2" | |
| 111 | 1012 [(set_attr "predicable" "yes") |
| 1013 (set_attr "type" "wmmx_wpack")] | |
| 1014 ) | |
| 0 | 1015 |
| 1016 (define_insn "iwmmxt_wunpckihb" | |
| 111 | 1017 [(set (match_operand:V8QI 0 "register_operand" "=y") |
| 0 | 1018 (vec_merge:V8QI |
| 111 | 1019 (vec_select:V8QI (match_operand:V8QI 1 "register_operand" "y") |
| 1020 (parallel [(const_int 4) | |
| 1021 (const_int 0) | |
| 1022 (const_int 5) | |
| 1023 (const_int 1) | |
| 1024 (const_int 6) | |
| 1025 (const_int 2) | |
| 1026 (const_int 7) | |
| 1027 (const_int 3)])) | |
| 1028 (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "y") | |
| 1029 (parallel [(const_int 0) | |
| 1030 (const_int 4) | |
| 1031 (const_int 1) | |
| 1032 (const_int 5) | |
| 1033 (const_int 2) | |
| 1034 (const_int 6) | |
| 1035 (const_int 3) | |
| 1036 (const_int 7)])) | |
| 1037 (const_int 85)))] | |
| 0 | 1038 "TARGET_REALLY_IWMMXT" |
| 1039 "wunpckihb%?\\t%0, %1, %2" | |
| 111 | 1040 [(set_attr "predicable" "yes") |
| 1041 (set_attr "type" "wmmx_wunpckih")] | |
| 1042 ) | |
| 0 | 1043 |
| 1044 (define_insn "iwmmxt_wunpckihh" | |
| 111 | 1045 [(set (match_operand:V4HI 0 "register_operand" "=y") |
| 0 | 1046 (vec_merge:V4HI |
| 111 | 1047 (vec_select:V4HI (match_operand:V4HI 1 "register_operand" "y") |
| 1048 (parallel [(const_int 2) | |
| 1049 (const_int 0) | |
| 1050 (const_int 3) | |
| 1051 (const_int 1)])) | |
| 1052 (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y") | |
| 1053 (parallel [(const_int 0) | |
| 1054 (const_int 2) | |
| 1055 (const_int 1) | |
| 1056 (const_int 3)])) | |
| 1057 (const_int 5)))] | |
| 0 | 1058 "TARGET_REALLY_IWMMXT" |
| 1059 "wunpckihh%?\\t%0, %1, %2" | |
| 111 | 1060 [(set_attr "predicable" "yes") |
| 1061 (set_attr "type" "wmmx_wunpckih")] | |
| 1062 ) | |
| 0 | 1063 |
| 1064 (define_insn "iwmmxt_wunpckihw" | |
| 111 | 1065 [(set (match_operand:V2SI 0 "register_operand" "=y") |
| 0 | 1066 (vec_merge:V2SI |
| 111 | 1067 (vec_select:V2SI (match_operand:V2SI 1 "register_operand" "y") |
| 1068 (parallel [(const_int 1) | |
| 1069 (const_int 0)])) | |
| 1070 (vec_select:V2SI (match_operand:V2SI 2 "register_operand" "y") | |
| 1071 (parallel [(const_int 0) | |
| 1072 (const_int 1)])) | |
| 1073 (const_int 1)))] | |
| 0 | 1074 "TARGET_REALLY_IWMMXT" |
| 1075 "wunpckihw%?\\t%0, %1, %2" | |
| 111 | 1076 [(set_attr "predicable" "yes") |
| 1077 (set_attr "type" "wmmx_wunpckih")] | |
| 1078 ) | |
| 0 | 1079 |
| 1080 (define_insn "iwmmxt_wunpckilb" | |
| 111 | 1081 [(set (match_operand:V8QI 0 "register_operand" "=y") |
| 0 | 1082 (vec_merge:V8QI |
| 111 | 1083 (vec_select:V8QI (match_operand:V8QI 1 "register_operand" "y") |
| 1084 (parallel [(const_int 0) | |
| 1085 (const_int 4) | |
| 1086 (const_int 1) | |
| 1087 (const_int 5) | |
| 1088 (const_int 2) | |
| 1089 (const_int 6) | |
| 1090 (const_int 3) | |
| 1091 (const_int 7)])) | |
| 1092 (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "y") | |
| 1093 (parallel [(const_int 4) | |
| 1094 (const_int 0) | |
| 1095 (const_int 5) | |
| 1096 (const_int 1) | |
| 1097 (const_int 6) | |
| 1098 (const_int 2) | |
| 1099 (const_int 7) | |
| 1100 (const_int 3)])) | |
| 1101 (const_int 85)))] | |
| 0 | 1102 "TARGET_REALLY_IWMMXT" |
| 1103 "wunpckilb%?\\t%0, %1, %2" | |
| 111 | 1104 [(set_attr "predicable" "yes") |
| 1105 (set_attr "type" "wmmx_wunpckil")] | |
| 1106 ) | |
| 0 | 1107 |
| 1108 (define_insn "iwmmxt_wunpckilh" | |
| 111 | 1109 [(set (match_operand:V4HI 0 "register_operand" "=y") |
| 0 | 1110 (vec_merge:V4HI |
| 111 | 1111 (vec_select:V4HI (match_operand:V4HI 1 "register_operand" "y") |
| 1112 (parallel [(const_int 0) | |
| 1113 (const_int 2) | |
| 1114 (const_int 1) | |
| 1115 (const_int 3)])) | |
| 1116 (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y") | |
| 1117 (parallel [(const_int 2) | |
| 1118 (const_int 0) | |
| 1119 (const_int 3) | |
| 1120 (const_int 1)])) | |
| 1121 (const_int 5)))] | |
| 0 | 1122 "TARGET_REALLY_IWMMXT" |
| 1123 "wunpckilh%?\\t%0, %1, %2" | |
| 111 | 1124 [(set_attr "predicable" "yes") |
| 1125 (set_attr "type" "wmmx_wunpckil")] | |
| 1126 ) | |
| 0 | 1127 |
| 1128 (define_insn "iwmmxt_wunpckilw" | |
| 111 | 1129 [(set (match_operand:V2SI 0 "register_operand" "=y") |
| 0 | 1130 (vec_merge:V2SI |
| 111 | 1131 (vec_select:V2SI (match_operand:V2SI 1 "register_operand" "y") |
| 1132 (parallel [(const_int 0) | |
| 1133 (const_int 1)])) | |
| 1134 (vec_select:V2SI (match_operand:V2SI 2 "register_operand" "y") | |
| 1135 (parallel [(const_int 1) | |
| 1136 (const_int 0)])) | |
| 1137 (const_int 1)))] | |
| 0 | 1138 "TARGET_REALLY_IWMMXT" |
| 1139 "wunpckilw%?\\t%0, %1, %2" | |
| 111 | 1140 [(set_attr "predicable" "yes") |
| 1141 (set_attr "type" "wmmx_wunpckil")] | |
| 1142 ) | |
| 0 | 1143 |
| 1144 (define_insn "iwmmxt_wunpckehub" | |
| 111 | 1145 [(set (match_operand:V4HI 0 "register_operand" "=y") |
| 1146 (vec_select:V4HI | |
| 1147 (zero_extend:V8HI (match_operand:V8QI 1 "register_operand" "y")) | |
| 1148 (parallel [(const_int 4) (const_int 5) | |
| 1149 (const_int 6) (const_int 7)])))] | |
| 0 | 1150 "TARGET_REALLY_IWMMXT" |
| 1151 "wunpckehub%?\\t%0, %1" | |
| 111 | 1152 [(set_attr "predicable" "yes") |
| 1153 (set_attr "type" "wmmx_wunpckeh")] | |
| 1154 ) | |
| 0 | 1155 |
| 1156 (define_insn "iwmmxt_wunpckehuh" | |
| 111 | 1157 [(set (match_operand:V2SI 0 "register_operand" "=y") |
| 1158 (vec_select:V2SI | |
| 1159 (zero_extend:V4SI (match_operand:V4HI 1 "register_operand" "y")) | |
| 1160 (parallel [(const_int 2) (const_int 3)])))] | |
| 0 | 1161 "TARGET_REALLY_IWMMXT" |
| 1162 "wunpckehuh%?\\t%0, %1" | |
| 111 | 1163 [(set_attr "predicable" "yes") |
| 1164 (set_attr "type" "wmmx_wunpckeh")] | |
| 1165 ) | |
| 0 | 1166 |
| 1167 (define_insn "iwmmxt_wunpckehuw" | |
| 111 | 1168 [(set (match_operand:DI 0 "register_operand" "=y") |
| 1169 (vec_select:DI | |
| 1170 (zero_extend:V2DI (match_operand:V2SI 1 "register_operand" "y")) | |
| 1171 (parallel [(const_int 1)])))] | |
| 0 | 1172 "TARGET_REALLY_IWMMXT" |
| 1173 "wunpckehuw%?\\t%0, %1" | |
| 111 | 1174 [(set_attr "predicable" "yes") |
| 1175 (set_attr "type" "wmmx_wunpckeh")] | |
| 1176 ) | |
| 0 | 1177 |
| 1178 (define_insn "iwmmxt_wunpckehsb" | |
| 111 | 1179 [(set (match_operand:V4HI 0 "register_operand" "=y") |
| 1180 (vec_select:V4HI | |
| 1181 (sign_extend:V8HI (match_operand:V8QI 1 "register_operand" "y")) | |
| 1182 (parallel [(const_int 4) (const_int 5) | |
| 1183 (const_int 6) (const_int 7)])))] | |
| 0 | 1184 "TARGET_REALLY_IWMMXT" |
| 1185 "wunpckehsb%?\\t%0, %1" | |
| 111 | 1186 [(set_attr "predicable" "yes") |
| 1187 (set_attr "type" "wmmx_wunpckeh")] | |
| 1188 ) | |
| 0 | 1189 |
| 1190 (define_insn "iwmmxt_wunpckehsh" | |
| 111 | 1191 [(set (match_operand:V2SI 0 "register_operand" "=y") |
| 1192 (vec_select:V2SI | |
| 1193 (sign_extend:V4SI (match_operand:V4HI 1 "register_operand" "y")) | |
| 1194 (parallel [(const_int 2) (const_int 3)])))] | |
| 0 | 1195 "TARGET_REALLY_IWMMXT" |
| 1196 "wunpckehsh%?\\t%0, %1" | |
| 111 | 1197 [(set_attr "predicable" "yes") |
| 1198 (set_attr "type" "wmmx_wunpckeh")] | |
| 1199 ) | |
| 0 | 1200 |
| 1201 (define_insn "iwmmxt_wunpckehsw" | |
| 111 | 1202 [(set (match_operand:DI 0 "register_operand" "=y") |
| 1203 (vec_select:DI | |
| 1204 (sign_extend:V2DI (match_operand:V2SI 1 "register_operand" "y")) | |
| 1205 (parallel [(const_int 1)])))] | |
| 0 | 1206 "TARGET_REALLY_IWMMXT" |
| 1207 "wunpckehsw%?\\t%0, %1" | |
| 111 | 1208 [(set_attr "predicable" "yes") |
| 1209 (set_attr "type" "wmmx_wunpckeh")] | |
| 1210 ) | |
| 0 | 1211 |
| 1212 (define_insn "iwmmxt_wunpckelub" | |
| 111 | 1213 [(set (match_operand:V4HI 0 "register_operand" "=y") |
| 1214 (vec_select:V4HI | |
| 1215 (zero_extend:V8HI (match_operand:V8QI 1 "register_operand" "y")) | |
| 1216 (parallel [(const_int 0) (const_int 1) | |
| 1217 (const_int 2) (const_int 3)])))] | |
| 0 | 1218 "TARGET_REALLY_IWMMXT" |
| 1219 "wunpckelub%?\\t%0, %1" | |
| 111 | 1220 [(set_attr "predicable" "yes") |
| 1221 (set_attr "type" "wmmx_wunpckel")] | |
| 1222 ) | |
| 0 | 1223 |
| 1224 (define_insn "iwmmxt_wunpckeluh" | |
| 111 | 1225 [(set (match_operand:V2SI 0 "register_operand" "=y") |
| 1226 (vec_select:V2SI | |
| 1227 (zero_extend:V4SI (match_operand:V4HI 1 "register_operand" "y")) | |
| 1228 (parallel [(const_int 0) (const_int 1)])))] | |
| 0 | 1229 "TARGET_REALLY_IWMMXT" |
| 1230 "wunpckeluh%?\\t%0, %1" | |
| 111 | 1231 [(set_attr "predicable" "yes") |
| 1232 (set_attr "type" "wmmx_wunpckel")] | |
| 1233 ) | |
| 0 | 1234 |
| 1235 (define_insn "iwmmxt_wunpckeluw" | |
| 111 | 1236 [(set (match_operand:DI 0 "register_operand" "=y") |
| 1237 (vec_select:DI | |
| 1238 (zero_extend:V2DI (match_operand:V2SI 1 "register_operand" "y")) | |
| 1239 (parallel [(const_int 0)])))] | |
| 0 | 1240 "TARGET_REALLY_IWMMXT" |
| 1241 "wunpckeluw%?\\t%0, %1" | |
| 111 | 1242 [(set_attr "predicable" "yes") |
| 1243 (set_attr "type" "wmmx_wunpckel")] | |
| 1244 ) | |
| 0 | 1245 |
| 1246 (define_insn "iwmmxt_wunpckelsb" | |
| 111 | 1247 [(set (match_operand:V4HI 0 "register_operand" "=y") |
| 1248 (vec_select:V4HI | |
| 1249 (sign_extend:V8HI (match_operand:V8QI 1 "register_operand" "y")) | |
| 1250 (parallel [(const_int 0) (const_int 1) | |
| 1251 (const_int 2) (const_int 3)])))] | |
| 0 | 1252 "TARGET_REALLY_IWMMXT" |
| 1253 "wunpckelsb%?\\t%0, %1" | |
| 111 | 1254 [(set_attr "predicable" "yes") |
| 1255 (set_attr "type" "wmmx_wunpckel")] | |
| 1256 ) | |
| 0 | 1257 |
| 1258 (define_insn "iwmmxt_wunpckelsh" | |
| 111 | 1259 [(set (match_operand:V2SI 0 "register_operand" "=y") |
| 1260 (vec_select:V2SI | |
| 1261 (sign_extend:V4SI (match_operand:V4HI 1 "register_operand" "y")) | |
| 1262 (parallel [(const_int 0) (const_int 1)])))] | |
| 0 | 1263 "TARGET_REALLY_IWMMXT" |
| 1264 "wunpckelsh%?\\t%0, %1" | |
| 111 | 1265 [(set_attr "predicable" "yes") |
| 1266 (set_attr "type" "wmmx_wunpckel")] | |
| 1267 ) | |
| 0 | 1268 |
| 1269 (define_insn "iwmmxt_wunpckelsw" | |
| 111 | 1270 [(set (match_operand:DI 0 "register_operand" "=y") |
| 1271 (vec_select:DI | |
| 1272 (sign_extend:V2DI (match_operand:V2SI 1 "register_operand" "y")) | |
| 1273 (parallel [(const_int 0)])))] | |
| 0 | 1274 "TARGET_REALLY_IWMMXT" |
| 1275 "wunpckelsw%?\\t%0, %1" | |
| 111 | 1276 [(set_attr "predicable" "yes") |
| 1277 (set_attr "type" "wmmx_wunpckel")] | |
| 1278 ) | |
| 0 | 1279 |
| 1280 ;; Shifts | |
| 1281 | |
| 111 | 1282 (define_insn "ror<mode>3" |
| 1283 [(set (match_operand:VSHFT 0 "register_operand" "=y,y") | |
| 1284 (rotatert:VSHFT (match_operand:VSHFT 1 "register_operand" "y,y") | |
| 1285 (match_operand:SI 2 "imm_or_reg_operand" "z,i")))] | |
| 0 | 1286 "TARGET_REALLY_IWMMXT" |
| 111 | 1287 "* |
| 1288 switch (which_alternative) | |
| 1289 { | |
| 1290 case 0: | |
| 1291 return \"wror<MMX_char>g%?\\t%0, %1, %2\"; | |
| 1292 case 1: | |
| 1293 return arm_output_iwmmxt_shift_immediate (\"wror<MMX_char>\", operands, true); | |
| 1294 default: | |
| 1295 gcc_unreachable (); | |
| 1296 } | |
| 1297 " | |
| 1298 [(set_attr "predicable" "yes") | |
| 1299 (set_attr "arch" "*, iwmmxt2") | |
| 1300 (set_attr "type" "wmmx_wror, wmmx_wror")] | |
| 1301 ) | |
| 0 | 1302 |
| 1303 (define_insn "ashr<mode>3_iwmmxt" | |
| 111 | 1304 [(set (match_operand:VSHFT 0 "register_operand" "=y,y") |
| 1305 (ashiftrt:VSHFT (match_operand:VSHFT 1 "register_operand" "y,y") | |
| 1306 (match_operand:SI 2 "imm_or_reg_operand" "z,i")))] | |
| 0 | 1307 "TARGET_REALLY_IWMMXT" |
| 111 | 1308 "* |
| 1309 switch (which_alternative) | |
| 1310 { | |
| 1311 case 0: | |
| 1312 return \"wsra<MMX_char>g%?\\t%0, %1, %2\"; | |
| 1313 case 1: | |
| 1314 return arm_output_iwmmxt_shift_immediate (\"wsra<MMX_char>\", operands, true); | |
| 1315 default: | |
| 1316 gcc_unreachable (); | |
| 1317 } | |
| 1318 " | |
| 1319 [(set_attr "predicable" "yes") | |
| 1320 (set_attr "arch" "*, iwmmxt2") | |
| 1321 (set_attr "type" "wmmx_wsra, wmmx_wsra")] | |
| 1322 ) | |
| 0 | 1323 |
| 1324 (define_insn "lshr<mode>3_iwmmxt" | |
| 111 | 1325 [(set (match_operand:VSHFT 0 "register_operand" "=y,y") |
| 1326 (lshiftrt:VSHFT (match_operand:VSHFT 1 "register_operand" "y,y") | |
| 1327 (match_operand:SI 2 "imm_or_reg_operand" "z,i")))] | |
| 0 | 1328 "TARGET_REALLY_IWMMXT" |
| 111 | 1329 "* |
| 1330 switch (which_alternative) | |
| 1331 { | |
| 1332 case 0: | |
| 1333 return \"wsrl<MMX_char>g%?\\t%0, %1, %2\"; | |
| 1334 case 1: | |
| 1335 return arm_output_iwmmxt_shift_immediate (\"wsrl<MMX_char>\", operands, false); | |
| 1336 default: | |
| 1337 gcc_unreachable (); | |
| 1338 } | |
| 1339 " | |
| 1340 [(set_attr "predicable" "yes") | |
| 1341 (set_attr "arch" "*, iwmmxt2") | |
| 1342 (set_attr "type" "wmmx_wsrl, wmmx_wsrl")] | |
| 1343 ) | |
| 0 | 1344 |
| 1345 (define_insn "ashl<mode>3_iwmmxt" | |
| 111 | 1346 [(set (match_operand:VSHFT 0 "register_operand" "=y,y") |
| 1347 (ashift:VSHFT (match_operand:VSHFT 1 "register_operand" "y,y") | |
| 1348 (match_operand:SI 2 "imm_or_reg_operand" "z,i")))] | |
| 0 | 1349 "TARGET_REALLY_IWMMXT" |
| 111 | 1350 "* |
| 1351 switch (which_alternative) | |
| 1352 { | |
| 1353 case 0: | |
| 1354 return \"wsll<MMX_char>g%?\\t%0, %1, %2\"; | |
| 1355 case 1: | |
| 1356 return arm_output_iwmmxt_shift_immediate (\"wsll<MMX_char>\", operands, false); | |
| 1357 default: | |
| 1358 gcc_unreachable (); | |
| 1359 } | |
| 1360 " | |
| 1361 [(set_attr "predicable" "yes") | |
| 1362 (set_attr "arch" "*, iwmmxt2") | |
| 1363 (set_attr "type" "wmmx_wsll, wmmx_wsll")] | |
| 1364 ) | |
| 0 | 1365 |
| 111 | 1366 (define_insn "ror<mode>3_di" |
| 1367 [(set (match_operand:VSHFT 0 "register_operand" "=y,y") | |
| 1368 (rotatert:VSHFT (match_operand:VSHFT 1 "register_operand" "y,y") | |
| 1369 (match_operand:DI 2 "imm_or_reg_operand" "y,i")))] | |
| 0 | 1370 "TARGET_REALLY_IWMMXT" |
| 111 | 1371 "* |
| 1372 switch (which_alternative) | |
| 1373 { | |
| 1374 case 0: | |
| 1375 return \"wror<MMX_char>%?\\t%0, %1, %2\"; | |
| 1376 case 1: | |
| 1377 return arm_output_iwmmxt_shift_immediate (\"wror<MMX_char>\", operands, true); | |
| 1378 default: | |
| 1379 gcc_unreachable (); | |
| 1380 } | |
| 1381 " | |
| 1382 [(set_attr "predicable" "yes") | |
| 1383 (set_attr "arch" "*, iwmmxt2") | |
| 1384 (set_attr "type" "wmmx_wror, wmmx_wror")] | |
| 1385 ) | |
| 0 | 1386 |
| 111 | 1387 (define_insn "ashr<mode>3_di" |
| 1388 [(set (match_operand:VSHFT 0 "register_operand" "=y,y") | |
| 1389 (ashiftrt:VSHFT (match_operand:VSHFT 1 "register_operand" "y,y") | |
| 1390 (match_operand:DI 2 "imm_or_reg_operand" "y,i")))] | |
| 0 | 1391 "TARGET_REALLY_IWMMXT" |
| 111 | 1392 "* |
| 1393 switch (which_alternative) | |
| 1394 { | |
| 1395 case 0: | |
| 1396 return \"wsra<MMX_char>%?\\t%0, %1, %2\"; | |
| 1397 case 1: | |
| 1398 return arm_output_iwmmxt_shift_immediate (\"wsra<MMX_char>\", operands, true); | |
| 1399 default: | |
| 1400 gcc_unreachable (); | |
| 1401 } | |
| 1402 " | |
| 1403 [(set_attr "predicable" "yes") | |
| 1404 (set_attr "arch" "*, iwmmxt2") | |
| 1405 (set_attr "type" "wmmx_wsra, wmmx_wsra")] | |
| 1406 ) | |
| 0 | 1407 |
| 111 | 1408 (define_insn "lshr<mode>3_di" |
| 1409 [(set (match_operand:VSHFT 0 "register_operand" "=y,y") | |
| 1410 (lshiftrt:VSHFT (match_operand:VSHFT 1 "register_operand" "y,y") | |
| 1411 (match_operand:DI 2 "register_operand" "y,i")))] | |
| 0 | 1412 "TARGET_REALLY_IWMMXT" |
| 111 | 1413 "* |
| 1414 switch (which_alternative) | |
| 1415 { | |
| 1416 case 0: | |
| 1417 return \"wsrl<MMX_char>%?\\t%0, %1, %2\"; | |
| 1418 case 1: | |
| 1419 return arm_output_iwmmxt_shift_immediate (\"wsrl<MMX_char>\", operands, false); | |
| 1420 default: | |
| 1421 gcc_unreachable (); | |
| 1422 } | |
| 1423 " | |
| 1424 [(set_attr "predicable" "yes") | |
| 1425 (set_attr "arch" "*, iwmmxt2") | |
| 1426 (set_attr "type" "wmmx_wsrl, wmmx_wsrl")] | |
| 1427 ) | |
| 0 | 1428 |
| 111 | 1429 (define_insn "ashl<mode>3_di" |
| 1430 [(set (match_operand:VSHFT 0 "register_operand" "=y,y") | |
| 1431 (ashift:VSHFT (match_operand:VSHFT 1 "register_operand" "y,y") | |
| 1432 (match_operand:DI 2 "imm_or_reg_operand" "y,i")))] | |
| 0 | 1433 "TARGET_REALLY_IWMMXT" |
| 111 | 1434 "* |
| 1435 switch (which_alternative) | |
| 1436 { | |
| 1437 case 0: | |
| 1438 return \"wsll<MMX_char>%?\\t%0, %1, %2\"; | |
| 1439 case 1: | |
| 1440 return arm_output_iwmmxt_shift_immediate (\"wsll<MMX_char>\", operands, false); | |
| 1441 default: | |
| 1442 gcc_unreachable (); | |
| 1443 } | |
| 1444 " | |
| 1445 [(set_attr "predicable" "yes") | |
| 1446 (set_attr "arch" "*, iwmmxt2") | |
| 1447 (set_attr "type" "wmmx_wsll, wmmx_wsll")] | |
| 1448 ) | |
| 0 | 1449 |
| 1450 (define_insn "iwmmxt_wmadds" | |
| 111 | 1451 [(set (match_operand:V2SI 0 "register_operand" "=y") |
| 1452 (plus:V2SI | |
| 1453 (mult:V2SI | |
| 1454 (vec_select:V2SI (sign_extend:V4SI (match_operand:V4HI 1 "register_operand" "y")) | |
| 1455 (parallel [(const_int 1) (const_int 3)])) | |
| 1456 (vec_select:V2SI (sign_extend:V4SI (match_operand:V4HI 2 "register_operand" "y")) | |
| 1457 (parallel [(const_int 1) (const_int 3)]))) | |
| 1458 (mult:V2SI | |
| 1459 (vec_select:V2SI (sign_extend:V4SI (match_dup 1)) | |
| 1460 (parallel [(const_int 0) (const_int 2)])) | |
| 1461 (vec_select:V2SI (sign_extend:V4SI (match_dup 2)) | |
| 1462 (parallel [(const_int 0) (const_int 2)])))))] | |
| 0 | 1463 "TARGET_REALLY_IWMMXT" |
| 1464 "wmadds%?\\t%0, %1, %2" | |
| 111 | 1465 [(set_attr "predicable" "yes") |
| 1466 (set_attr "type" "wmmx_wmadd")] | |
| 1467 ) | |
| 0 | 1468 |
| 1469 (define_insn "iwmmxt_wmaddu" | |
| 111 | 1470 [(set (match_operand:V2SI 0 "register_operand" "=y") |
| 1471 (plus:V2SI | |
| 1472 (mult:V2SI | |
| 1473 (vec_select:V2SI (zero_extend:V4SI (match_operand:V4HI 1 "register_operand" "y")) | |
| 1474 (parallel [(const_int 1) (const_int 3)])) | |
| 1475 (vec_select:V2SI (zero_extend:V4SI (match_operand:V4HI 2 "register_operand" "y")) | |
| 1476 (parallel [(const_int 1) (const_int 3)]))) | |
| 1477 (mult:V2SI | |
| 1478 (vec_select:V2SI (zero_extend:V4SI (match_dup 1)) | |
| 1479 (parallel [(const_int 0) (const_int 2)])) | |
| 1480 (vec_select:V2SI (zero_extend:V4SI (match_dup 2)) | |
| 1481 (parallel [(const_int 0) (const_int 2)])))))] | |
| 0 | 1482 "TARGET_REALLY_IWMMXT" |
| 1483 "wmaddu%?\\t%0, %1, %2" | |
| 111 | 1484 [(set_attr "predicable" "yes") |
| 1485 (set_attr "type" "wmmx_wmadd")] | |
| 1486 ) | |
| 0 | 1487 |
| 1488 (define_insn "iwmmxt_tmia" | |
| 111 | 1489 [(set (match_operand:DI 0 "register_operand" "=y") |
| 1490 (plus:DI (match_operand:DI 1 "register_operand" "0") | |
| 0 | 1491 (mult:DI (sign_extend:DI |
| 111 | 1492 (match_operand:SI 2 "register_operand" "r")) |
| 0 | 1493 (sign_extend:DI |
| 111 | 1494 (match_operand:SI 3 "register_operand" "r")))))] |
| 0 | 1495 "TARGET_REALLY_IWMMXT" |
| 1496 "tmia%?\\t%0, %2, %3" | |
| 111 | 1497 [(set_attr "predicable" "yes") |
| 1498 (set_attr "type" "wmmx_tmia")] | |
| 1499 ) | |
| 0 | 1500 |
| 1501 (define_insn "iwmmxt_tmiaph" | |
| 111 | 1502 [(set (match_operand:DI 0 "register_operand" "=y") |
| 1503 (plus:DI (match_operand:DI 1 "register_operand" "0") | |
| 0 | 1504 (plus:DI |
| 111 | 1505 (mult:DI (sign_extend:DI |
| 1506 (truncate:HI (match_operand:SI 2 "register_operand" "r"))) | |
| 1507 (sign_extend:DI | |
| 1508 (truncate:HI (match_operand:SI 3 "register_operand" "r")))) | |
| 1509 (mult:DI (sign_extend:DI | |
| 1510 (truncate:HI (ashiftrt:SI (match_dup 2) (const_int 16)))) | |
| 1511 (sign_extend:DI | |
| 1512 (truncate:HI (ashiftrt:SI (match_dup 3) (const_int 16))))))))] | |
| 0 | 1513 "TARGET_REALLY_IWMMXT" |
| 1514 "tmiaph%?\\t%0, %2, %3" | |
| 111 | 1515 [(set_attr "predicable" "yes") |
| 1516 (set_attr "type" "wmmx_tmiaph")] | |
| 1517 ) | |
| 0 | 1518 |
| 1519 (define_insn "iwmmxt_tmiabb" | |
| 111 | 1520 [(set (match_operand:DI 0 "register_operand" "=y") |
| 1521 (plus:DI (match_operand:DI 1 "register_operand" "0") | |
| 0 | 1522 (mult:DI (sign_extend:DI |
| 111 | 1523 (truncate:HI (match_operand:SI 2 "register_operand" "r"))) |
| 0 | 1524 (sign_extend:DI |
| 111 | 1525 (truncate:HI (match_operand:SI 3 "register_operand" "r"))))))] |
| 0 | 1526 "TARGET_REALLY_IWMMXT" |
| 1527 "tmiabb%?\\t%0, %2, %3" | |
| 111 | 1528 [(set_attr "predicable" "yes") |
| 1529 (set_attr "type" "wmmx_tmiaxy")] | |
| 1530 ) | |
| 0 | 1531 |
| 1532 (define_insn "iwmmxt_tmiatb" | |
| 111 | 1533 [(set (match_operand:DI 0 "register_operand" "=y") |
| 1534 (plus:DI (match_operand:DI 1 "register_operand" "0") | |
| 0 | 1535 (mult:DI (sign_extend:DI |
| 111 | 1536 (truncate:HI |
| 1537 (ashiftrt:SI | |
| 1538 (match_operand:SI 2 "register_operand" "r") | |
| 1539 (const_int 16)))) | |
| 0 | 1540 (sign_extend:DI |
| 111 | 1541 (truncate:HI |
| 1542 (match_operand:SI 3 "register_operand" "r"))))))] | |
| 0 | 1543 "TARGET_REALLY_IWMMXT" |
| 1544 "tmiatb%?\\t%0, %2, %3" | |
| 111 | 1545 [(set_attr "predicable" "yes") |
| 1546 (set_attr "type" "wmmx_tmiaxy")] | |
| 1547 ) | |
| 0 | 1548 |
| 1549 (define_insn "iwmmxt_tmiabt" | |
| 111 | 1550 [(set (match_operand:DI 0 "register_operand" "=y") |
| 1551 (plus:DI (match_operand:DI 1 "register_operand" "0") | |
| 0 | 1552 (mult:DI (sign_extend:DI |
| 111 | 1553 (truncate:HI |
| 1554 (match_operand:SI 2 "register_operand" "r"))) | |
| 0 | 1555 (sign_extend:DI |
| 111 | 1556 (truncate:HI |
| 1557 (ashiftrt:SI | |
| 1558 (match_operand:SI 3 "register_operand" "r") | |
| 1559 (const_int 16)))))))] | |
| 0 | 1560 "TARGET_REALLY_IWMMXT" |
| 1561 "tmiabt%?\\t%0, %2, %3" | |
| 111 | 1562 [(set_attr "predicable" "yes") |
| 1563 (set_attr "type" "wmmx_tmiaxy")] | |
| 1564 ) | |
| 0 | 1565 |
| 1566 (define_insn "iwmmxt_tmiatt" | |
| 1567 [(set (match_operand:DI 0 "register_operand" "=y") | |
| 1568 (plus:DI (match_operand:DI 1 "register_operand" "0") | |
| 1569 (mult:DI (sign_extend:DI | |
| 111 | 1570 (truncate:HI |
| 1571 (ashiftrt:SI | |
| 1572 (match_operand:SI 2 "register_operand" "r") | |
| 1573 (const_int 16)))) | |
| 0 | 1574 (sign_extend:DI |
| 111 | 1575 (truncate:HI |
| 1576 (ashiftrt:SI | |
| 1577 (match_operand:SI 3 "register_operand" "r") | |
| 1578 (const_int 16)))))))] | |
| 0 | 1579 "TARGET_REALLY_IWMMXT" |
| 1580 "tmiatt%?\\t%0, %2, %3" | |
| 111 | 1581 [(set_attr "predicable" "yes") |
| 1582 (set_attr "type" "wmmx_tmiaxy")] | |
| 1583 ) | |
| 0 | 1584 |
| 1585 (define_insn "iwmmxt_tmovmskb" | |
| 1586 [(set (match_operand:SI 0 "register_operand" "=r") | |
| 1587 (unspec:SI [(match_operand:V8QI 1 "register_operand" "y")] UNSPEC_TMOVMSK))] | |
| 1588 "TARGET_REALLY_IWMMXT" | |
| 1589 "tmovmskb%?\\t%0, %1" | |
| 111 | 1590 [(set_attr "predicable" "yes") |
| 1591 (set_attr "type" "wmmx_tmovmsk")] | |
| 1592 ) | |
| 0 | 1593 |
| 1594 (define_insn "iwmmxt_tmovmskh" | |
| 1595 [(set (match_operand:SI 0 "register_operand" "=r") | |
| 1596 (unspec:SI [(match_operand:V4HI 1 "register_operand" "y")] UNSPEC_TMOVMSK))] | |
| 1597 "TARGET_REALLY_IWMMXT" | |
| 1598 "tmovmskh%?\\t%0, %1" | |
| 111 | 1599 [(set_attr "predicable" "yes") |
| 1600 (set_attr "type" "wmmx_tmovmsk")] | |
| 1601 ) | |
| 0 | 1602 |
| 1603 (define_insn "iwmmxt_tmovmskw" | |
| 1604 [(set (match_operand:SI 0 "register_operand" "=r") | |
| 1605 (unspec:SI [(match_operand:V2SI 1 "register_operand" "y")] UNSPEC_TMOVMSK))] | |
| 1606 "TARGET_REALLY_IWMMXT" | |
| 1607 "tmovmskw%?\\t%0, %1" | |
| 111 | 1608 [(set_attr "predicable" "yes") |
| 1609 (set_attr "type" "wmmx_tmovmsk")] | |
| 1610 ) | |
| 0 | 1611 |
| 1612 (define_insn "iwmmxt_waccb" | |
| 1613 [(set (match_operand:DI 0 "register_operand" "=y") | |
| 1614 (unspec:DI [(match_operand:V8QI 1 "register_operand" "y")] UNSPEC_WACC))] | |
| 1615 "TARGET_REALLY_IWMMXT" | |
| 1616 "waccb%?\\t%0, %1" | |
| 111 | 1617 [(set_attr "predicable" "yes") |
| 1618 (set_attr "type" "wmmx_wacc")] | |
| 1619 ) | |
| 0 | 1620 |
| 1621 (define_insn "iwmmxt_wacch" | |
| 1622 [(set (match_operand:DI 0 "register_operand" "=y") | |
| 1623 (unspec:DI [(match_operand:V4HI 1 "register_operand" "y")] UNSPEC_WACC))] | |
| 1624 "TARGET_REALLY_IWMMXT" | |
| 1625 "wacch%?\\t%0, %1" | |
| 111 | 1626 [(set_attr "predicable" "yes") |
| 1627 (set_attr "type" "wmmx_wacc")] | |
| 1628 ) | |
| 0 | 1629 |
| 1630 (define_insn "iwmmxt_waccw" | |
| 1631 [(set (match_operand:DI 0 "register_operand" "=y") | |
| 1632 (unspec:DI [(match_operand:V2SI 1 "register_operand" "y")] UNSPEC_WACC))] | |
| 1633 "TARGET_REALLY_IWMMXT" | |
| 1634 "waccw%?\\t%0, %1" | |
| 111 | 1635 [(set_attr "predicable" "yes") |
| 1636 (set_attr "type" "wmmx_wacc")] | |
| 1637 ) | |
| 0 | 1638 |
| 111 | 1639 ;; use unspec here to prevent 8 * imm to be optimized by cse |
| 1640 (define_insn "iwmmxt_waligni" | |
| 1641 [(set (match_operand:V8QI 0 "register_operand" "=y") | |
| 1642 (unspec:V8QI [(subreg:V8QI | |
| 1643 (ashiftrt:TI | |
| 1644 (subreg:TI (vec_concat:V16QI | |
| 1645 (match_operand:V8QI 1 "register_operand" "y") | |
| 1646 (match_operand:V8QI 2 "register_operand" "y")) 0) | |
| 1647 (mult:SI | |
| 1648 (match_operand:SI 3 "immediate_operand" "i") | |
| 1649 (const_int 8))) 0)] UNSPEC_WALIGNI))] | |
| 1650 "TARGET_REALLY_IWMMXT" | |
| 1651 "waligni%?\\t%0, %1, %2, %3" | |
| 1652 [(set_attr "predicable" "yes") | |
| 1653 (set_attr "type" "wmmx_waligni")] | |
| 1654 ) | |
| 1655 | |
| 1656 (define_insn "iwmmxt_walignr" | |
| 1657 [(set (match_operand:V8QI 0 "register_operand" "=y") | |
| 0 | 1658 (subreg:V8QI (ashiftrt:TI |
| 111 | 1659 (subreg:TI (vec_concat:V16QI |
| 1660 (match_operand:V8QI 1 "register_operand" "y") | |
| 1661 (match_operand:V8QI 2 "register_operand" "y")) 0) | |
| 1662 (mult:SI | |
| 1663 (zero_extract:SI (match_operand:SI 3 "register_operand" "z") (const_int 3) (const_int 0)) | |
| 1664 (const_int 8))) 0))] | |
| 1665 "TARGET_REALLY_IWMMXT" | |
| 1666 "walignr%U3%?\\t%0, %1, %2" | |
| 1667 [(set_attr "predicable" "yes") | |
| 1668 (set_attr "type" "wmmx_walignr")] | |
| 1669 ) | |
| 1670 | |
| 1671 (define_insn "iwmmxt_walignr0" | |
| 1672 [(set (match_operand:V8QI 0 "register_operand" "=y") | |
| 1673 (subreg:V8QI (ashiftrt:TI | |
| 1674 (subreg:TI (vec_concat:V16QI | |
| 1675 (match_operand:V8QI 1 "register_operand" "y") | |
| 1676 (match_operand:V8QI 2 "register_operand" "y")) 0) | |
| 1677 (mult:SI | |
| 1678 (zero_extract:SI (reg:SI WCGR0) (const_int 3) (const_int 0)) | |
| 1679 (const_int 8))) 0))] | |
| 0 | 1680 "TARGET_REALLY_IWMMXT" |
| 111 | 1681 "walignr0%?\\t%0, %1, %2" |
| 1682 [(set_attr "predicable" "yes") | |
| 1683 (set_attr "type" "wmmx_walignr")] | |
| 1684 ) | |
| 0 | 1685 |
| 111 | 1686 (define_insn "iwmmxt_walignr1" |
| 1687 [(set (match_operand:V8QI 0 "register_operand" "=y") | |
| 1688 (subreg:V8QI (ashiftrt:TI | |
| 1689 (subreg:TI (vec_concat:V16QI | |
| 1690 (match_operand:V8QI 1 "register_operand" "y") | |
| 1691 (match_operand:V8QI 2 "register_operand" "y")) 0) | |
| 1692 (mult:SI | |
| 1693 (zero_extract:SI (reg:SI WCGR1) (const_int 3) (const_int 0)) | |
| 1694 (const_int 8))) 0))] | |
| 0 | 1695 "TARGET_REALLY_IWMMXT" |
| 111 | 1696 "walignr1%?\\t%0, %1, %2" |
| 1697 [(set_attr "predicable" "yes") | |
| 1698 (set_attr "type" "wmmx_walignr")] | |
| 1699 ) | |
| 0 | 1700 |
| 111 | 1701 (define_insn "iwmmxt_walignr2" |
| 1702 [(set (match_operand:V8QI 0 "register_operand" "=y") | |
| 1703 (subreg:V8QI (ashiftrt:TI | |
| 1704 (subreg:TI (vec_concat:V16QI | |
| 1705 (match_operand:V8QI 1 "register_operand" "y") | |
| 1706 (match_operand:V8QI 2 "register_operand" "y")) 0) | |
| 1707 (mult:SI | |
| 1708 (zero_extract:SI (reg:SI WCGR2) (const_int 3) (const_int 0)) | |
| 1709 (const_int 8))) 0))] | |
| 0 | 1710 "TARGET_REALLY_IWMMXT" |
| 111 | 1711 "walignr2%?\\t%0, %1, %2" |
| 1712 [(set_attr "predicable" "yes") | |
| 1713 (set_attr "type" "wmmx_walignr")] | |
| 1714 ) | |
| 1715 | |
| 1716 (define_insn "iwmmxt_walignr3" | |
| 1717 [(set (match_operand:V8QI 0 "register_operand" "=y") | |
| 1718 (subreg:V8QI (ashiftrt:TI | |
| 1719 (subreg:TI (vec_concat:V16QI | |
| 1720 (match_operand:V8QI 1 "register_operand" "y") | |
| 1721 (match_operand:V8QI 2 "register_operand" "y")) 0) | |
| 1722 (mult:SI | |
| 1723 (zero_extract:SI (reg:SI WCGR3) (const_int 3) (const_int 0)) | |
| 1724 (const_int 8))) 0))] | |
| 1725 "TARGET_REALLY_IWMMXT" | |
| 1726 "walignr3%?\\t%0, %1, %2" | |
| 1727 [(set_attr "predicable" "yes") | |
| 1728 (set_attr "type" "wmmx_walignr")] | |
| 1729 ) | |
| 0 | 1730 |
| 1731 (define_insn "iwmmxt_wsadb" | |
| 111 | 1732 [(set (match_operand:V2SI 0 "register_operand" "=y") |
| 1733 (unspec:V2SI [ | |
| 1734 (match_operand:V2SI 1 "register_operand" "0") | |
| 1735 (match_operand:V8QI 2 "register_operand" "y") | |
| 1736 (match_operand:V8QI 3 "register_operand" "y")] UNSPEC_WSAD))] | |
| 0 | 1737 "TARGET_REALLY_IWMMXT" |
| 111 | 1738 "wsadb%?\\t%0, %2, %3" |
| 1739 [(set_attr "predicable" "yes") | |
| 1740 (set_attr "type" "wmmx_wsad")] | |
| 1741 ) | |
| 0 | 1742 |
| 1743 (define_insn "iwmmxt_wsadh" | |
| 111 | 1744 [(set (match_operand:V2SI 0 "register_operand" "=y") |
| 1745 (unspec:V2SI [ | |
| 1746 (match_operand:V2SI 1 "register_operand" "0") | |
| 1747 (match_operand:V4HI 2 "register_operand" "y") | |
| 1748 (match_operand:V4HI 3 "register_operand" "y")] UNSPEC_WSAD))] | |
| 0 | 1749 "TARGET_REALLY_IWMMXT" |
| 111 | 1750 "wsadh%?\\t%0, %2, %3" |
| 1751 [(set_attr "predicable" "yes") | |
| 1752 (set_attr "type" "wmmx_wsad")] | |
| 1753 ) | |
| 0 | 1754 |
| 1755 (define_insn "iwmmxt_wsadbz" | |
| 111 | 1756 [(set (match_operand:V2SI 0 "register_operand" "=y") |
| 1757 (unspec:V2SI [(match_operand:V8QI 1 "register_operand" "y") | |
| 0 | 1758 (match_operand:V8QI 2 "register_operand" "y")] UNSPEC_WSADZ))] |
| 1759 "TARGET_REALLY_IWMMXT" | |
| 1760 "wsadbz%?\\t%0, %1, %2" | |
| 111 | 1761 [(set_attr "predicable" "yes") |
| 1762 (set_attr "type" "wmmx_wsad")] | |
| 1763 ) | |
| 0 | 1764 |
| 1765 (define_insn "iwmmxt_wsadhz" | |
| 111 | 1766 [(set (match_operand:V2SI 0 "register_operand" "=y") |
| 1767 (unspec:V2SI [(match_operand:V4HI 1 "register_operand" "y") | |
| 0 | 1768 (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WSADZ))] |
| 1769 "TARGET_REALLY_IWMMXT" | |
| 1770 "wsadhz%?\\t%0, %1, %2" | |
| 111 | 1771 [(set_attr "predicable" "yes") |
| 1772 (set_attr "type" "wmmx_wsad")] | |
| 1773 ) | |
| 0 | 1774 |
| 111 | 1775 (include "iwmmxt2.md") |