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111
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1 ;; Unspec defintions.
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131
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2 ;; Copyright (C) 2012-2018 Free Software Foundation, Inc.
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3 ;; Contributed by ARM Ltd.
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4
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5 ;; This file is part of GCC.
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6
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7 ;; GCC is free software; you can redistribute it and/or modify it
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8 ;; under the terms of the GNU General Public License as published
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9 ;; by the Free Software Foundation; either version 3, or (at your
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10 ;; option) any later version.
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11
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12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
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13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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15 ;; License for more details.
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16
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17 ;; You should have received a copy of the GNU General Public License
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18 ;; along with GCC; see the file COPYING3. If not see
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19 ;; <http://www.gnu.org/licenses/>.
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20
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21 ;; UNSPEC Usage:
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22 ;; Note: sin and cos are no-longer used.
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23 ;; Unspec enumerators for Neon are defined in neon.md.
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24 ;; Unspec enumerators for iwmmxt2 are defined in iwmmxt2.md
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25
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26 (define_c_enum "unspec" [
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27 UNSPEC_PUSH_MULT ; `push multiple' operation:
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28 ; operand 0 is the first register,
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29 ; subsequent registers are in parallel (use ...)
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30 ; expressions.
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31 UNSPEC_PIC_SYM ; A symbol that has been treated properly for pic
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32 ; usage, that is, we will add the pic_register
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33 ; value to it before trying to dereference it.
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34 UNSPEC_PIC_BASE ; Add PC and all but the last operand together,
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35 ; The last operand is the number of a PIC_LABEL
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36 ; that points at the containing instruction.
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37 UNSPEC_PRLG_STK ; A special barrier that prevents frame accesses
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38 ; being scheduled before the stack adjustment insn.
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39 UNSPEC_REGISTER_USE ; As USE insns are not meaningful after reload,
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40 ; this unspec is used to prevent the deletion of
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41 ; instructions setting registers for EH handling
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42 ; and stack frame generation. Operand 0 is the
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43 ; register to "use".
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44 UNSPEC_CHECK_ARCH ; Set CCs to indicate 26-bit or 32-bit mode.
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45 UNSPEC_WSHUFH ; Used by the intrinsic form of the iWMMXt WSHUFH instruction.
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46 UNSPEC_WACC ; Used by the intrinsic form of the iWMMXt WACC instruction.
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47 UNSPEC_TMOVMSK ; Used by the intrinsic form of the iWMMXt TMOVMSK instruction.
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48 UNSPEC_WSAD ; Used by the intrinsic form of the iWMMXt WSAD instruction.
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49 UNSPEC_WSADZ ; Used by the intrinsic form of the iWMMXt WSADZ instruction.
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50 UNSPEC_WMACS ; Used by the intrinsic form of the iWMMXt WMACS instruction.
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51 UNSPEC_WMACU ; Used by the intrinsic form of the iWMMXt WMACU instruction.
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52 UNSPEC_WMACSZ ; Used by the intrinsic form of the iWMMXt WMACSZ instruction.
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53 UNSPEC_WMACUZ ; Used by the intrinsic form of the iWMMXt WMACUZ instruction.
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54 UNSPEC_CLRDI ; Used by the intrinsic form of the iWMMXt CLRDI instruction.
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55 UNSPEC_WALIGNI ; Used by the intrinsic form of the iWMMXt WALIGN instruction.
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56 UNSPEC_TLS ; A symbol that has been treated properly for TLS usage.
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57 UNSPEC_PIC_LABEL ; A label used for PIC access that does not appear in the
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58 ; instruction stream.
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59 UNSPEC_PIC_OFFSET ; A symbolic 12-bit OFFSET that has been treated
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60 ; correctly for PIC usage.
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61 UNSPEC_GOTSYM_OFF ; The offset of the start of the GOT from a
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62 ; a given symbolic address.
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63 UNSPEC_THUMB1_CASESI ; A Thumb1 compressed dispatch-table call.
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64 UNSPEC_RBIT ; rbit operation.
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65 UNSPEC_SYMBOL_OFFSET ; The offset of the start of the symbol from
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66 ; another symbolic address.
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67 UNSPEC_MEMORY_BARRIER ; Represent a memory barrier.
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68 UNSPEC_UNALIGNED_LOAD ; Used to represent ldr/ldrh instructions that access
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69 ; unaligned locations, on architectures which support
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70 ; that.
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71 UNSPEC_UNALIGNED_STORE ; Same for str/strh.
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72 UNSPEC_PIC_UNIFIED ; Create a common pic addressing form.
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73 UNSPEC_LL ; Represent an unpaired load-register-exclusive.
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74 UNSPEC_VRINTZ ; Represent a float to integral float rounding
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75 ; towards zero.
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76 UNSPEC_VRINTP ; Represent a float to integral float rounding
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77 ; towards +Inf.
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78 UNSPEC_VRINTM ; Represent a float to integral float rounding
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79 ; towards -Inf.
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80 UNSPEC_VRINTR ; Represent a float to integral float rounding
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81 ; FPSCR rounding mode.
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82 UNSPEC_VRINTX ; Represent a float to integral float rounding
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83 ; FPSCR rounding mode and signal inexactness.
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84 UNSPEC_VRINTA ; Represent a float to integral float rounding
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85 ; towards nearest, ties away from zero.
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86 UNSPEC_PROBE_STACK ; Probe stack memory reference
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87 UNSPEC_NONSECURE_MEM ; Represent non-secure memory in ARMv8-M with
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88 ; security extension
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89 ])
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90
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91 (define_c_enum "unspec" [
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92 UNSPEC_WADDC ; Used by the intrinsic form of the iWMMXt WADDC instruction.
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93 UNSPEC_WABS ; Used by the intrinsic form of the iWMMXt WABS instruction.
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94 UNSPEC_WQMULWMR ; Used by the intrinsic form of the iWMMXt WQMULWMR instruction.
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95 UNSPEC_WQMULMR ; Used by the intrinsic form of the iWMMXt WQMULMR instruction.
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96 UNSPEC_WQMULWM ; Used by the intrinsic form of the iWMMXt WQMULWM instruction.
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97 UNSPEC_WQMULM ; Used by the intrinsic form of the iWMMXt WQMULM instruction.
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98 UNSPEC_WQMIAxyn ; Used by the intrinsic form of the iWMMXt WMIAxyn instruction.
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99 UNSPEC_WQMIAxy ; Used by the intrinsic form of the iWMMXt WMIAxy instruction.
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100 UNSPEC_TANDC ; Used by the intrinsic form of the iWMMXt TANDC instruction.
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101 UNSPEC_TORC ; Used by the intrinsic form of the iWMMXt TORC instruction.
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102 UNSPEC_TORVSC ; Used by the intrinsic form of the iWMMXt TORVSC instruction.
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103 UNSPEC_TEXTRC ; Used by the intrinsic form of the iWMMXt TEXTRC instruction.
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104 ])
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105
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106
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107 ;; UNSPEC_VOLATILE Usage:
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108
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109 (define_c_enum "unspecv" [
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110 VUNSPEC_BLOCKAGE ; `blockage' insn to prevent scheduling across an
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111 ; insn in the code.
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112 VUNSPEC_EPILOGUE ; `epilogue' insn, used to represent any part of the
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113 ; instruction epilogue sequence that isn't expanded
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114 ; into normal RTL. Used for both normal and sibcall
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115 ; epilogues.
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116 VUNSPEC_THUMB1_INTERWORK ; `prologue_thumb1_interwork' insn, used to swap
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117 ; modes from arm to thumb.
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118 VUNSPEC_ALIGN ; `align' insn. Used at the head of a minipool table
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119 ; for inlined constants.
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120 VUNSPEC_POOL_END ; `end-of-table'. Used to mark the end of a minipool
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121 ; table.
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122 VUNSPEC_POOL_1 ; `pool-entry(1)'. An entry in the constant pool for
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123 ; an 8-bit object.
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124 VUNSPEC_POOL_2 ; `pool-entry(2)'. An entry in the constant pool for
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125 ; a 16-bit object.
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126 VUNSPEC_POOL_4 ; `pool-entry(4)'. An entry in the constant pool for
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127 ; a 32-bit object.
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128 VUNSPEC_POOL_8 ; `pool-entry(8)'. An entry in the constant pool for
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129 ; a 64-bit object.
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130 VUNSPEC_POOL_16 ; `pool-entry(16)'. An entry in the constant pool for
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131 ; a 128-bit object.
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132 VUNSPEC_TMRC ; Used by the iWMMXt TMRC instruction.
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133 VUNSPEC_TMCR ; Used by the iWMMXt TMCR instruction.
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134 VUNSPEC_ALIGN8 ; 8-byte alignment version of VUNSPEC_ALIGN
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135 VUNSPEC_WCMP_EQ ; Used by the iWMMXt WCMPEQ instructions
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136 VUNSPEC_WCMP_GTU ; Used by the iWMMXt WCMPGTU instructions
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137 VUNSPEC_WCMP_GT ; Used by the iwMMXT WCMPGT instructions
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138 VUNSPEC_EH_RETURN ; Use to override the return address for exception
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139 ; handling.
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140 VUNSPEC_ATOMIC_CAS ; Represent an atomic compare swap.
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141 VUNSPEC_ATOMIC_XCHG ; Represent an atomic exchange.
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142 VUNSPEC_ATOMIC_OP ; Represent an atomic operation.
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143 VUNSPEC_LL ; Represent a load-register-exclusive.
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144 VUNSPEC_LDRD_ATOMIC ; Represent an LDRD used as an atomic DImode load.
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145 VUNSPEC_SC ; Represent a store-register-exclusive.
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146 VUNSPEC_LAX ; Represent a load-register-acquire-exclusive.
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147 VUNSPEC_SLX ; Represent a store-register-release-exclusive.
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148 VUNSPEC_LDA ; Represent a store-register-acquire.
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149 VUNSPEC_STL ; Represent a store-register-release.
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150 VUNSPEC_GET_FPSCR ; Represent fetch of FPSCR content.
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151 VUNSPEC_SET_FPSCR ; Represent assign of FPSCR content.
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152 VUNSPEC_PROBE_STACK_RANGE ; Represent stack range probing.
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153 VUNSPEC_CDP ; Represent the coprocessor cdp instruction.
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154 VUNSPEC_CDP2 ; Represent the coprocessor cdp2 instruction.
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155 VUNSPEC_LDC ; Represent the coprocessor ldc instruction.
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156 VUNSPEC_LDC2 ; Represent the coprocessor ldc2 instruction.
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157 VUNSPEC_LDCL ; Represent the coprocessor ldcl instruction.
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158 VUNSPEC_LDC2L ; Represent the coprocessor ldc2l instruction.
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159 VUNSPEC_STC ; Represent the coprocessor stc instruction.
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160 VUNSPEC_STC2 ; Represent the coprocessor stc2 instruction.
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161 VUNSPEC_STCL ; Represent the coprocessor stcl instruction.
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162 VUNSPEC_STC2L ; Represent the coprocessor stc2l instruction.
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163 VUNSPEC_MCR ; Represent the coprocessor mcr instruction.
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164 VUNSPEC_MCR2 ; Represent the coprocessor mcr2 instruction.
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165 VUNSPEC_MRC ; Represent the coprocessor mrc instruction.
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166 VUNSPEC_MRC2 ; Represent the coprocessor mrc2 instruction.
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167 VUNSPEC_MCRR ; Represent the coprocessor mcrr instruction.
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168 VUNSPEC_MCRR2 ; Represent the coprocessor mcrr2 instruction.
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169 VUNSPEC_MRRC ; Represent the coprocessor mrrc instruction.
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170 VUNSPEC_MRRC2 ; Represent the coprocessor mrrc2 instruction.
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131
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171 VUNSPEC_SPECULATION_BARRIER ; Represents an unconditional speculation barrier.
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111
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172 ])
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173
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174 ;; Enumerators for NEON unspecs.
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175 (define_c_enum "unspec" [
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176 UNSPEC_ASHIFT_SIGNED
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177 UNSPEC_ASHIFT_UNSIGNED
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178 UNSPEC_CRC32B
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179 UNSPEC_CRC32H
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180 UNSPEC_CRC32W
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181 UNSPEC_CRC32CB
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182 UNSPEC_CRC32CH
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183 UNSPEC_CRC32CW
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184 UNSPEC_AESD
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185 UNSPEC_AESE
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186 UNSPEC_AESIMC
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187 UNSPEC_AESMC
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188 UNSPEC_SHA1C
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189 UNSPEC_SHA1M
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190 UNSPEC_SHA1P
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191 UNSPEC_SHA1H
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192 UNSPEC_SHA1SU0
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193 UNSPEC_SHA1SU1
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194 UNSPEC_SHA256H
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195 UNSPEC_SHA256H2
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196 UNSPEC_SHA256SU0
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197 UNSPEC_SHA256SU1
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198 UNSPEC_VMULLP64
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199 UNSPEC_LOAD_COUNT
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200 UNSPEC_VABD_F
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201 UNSPEC_VABD_S
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202 UNSPEC_VABD_U
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203 UNSPEC_VABDL_S
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204 UNSPEC_VABDL_U
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205 UNSPEC_VADD
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206 UNSPEC_VADDHN
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207 UNSPEC_VRADDHN
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208 UNSPEC_VADDL_S
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209 UNSPEC_VADDL_U
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210 UNSPEC_VADDW_S
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211 UNSPEC_VADDW_U
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212 UNSPEC_VBSL
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213 UNSPEC_VCAGE
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214 UNSPEC_VCAGT
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215 UNSPEC_VCALE
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216 UNSPEC_VCALT
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217 UNSPEC_VCEQ
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218 UNSPEC_VCGE
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219 UNSPEC_VCGEU
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220 UNSPEC_VCGT
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221 UNSPEC_VCGTU
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222 UNSPEC_VCLS
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223 UNSPEC_VCONCAT
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224 UNSPEC_VCVT
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225 UNSPEC_VCVT_S
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226 UNSPEC_VCVT_U
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227 UNSPEC_VCVT_S_N
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228 UNSPEC_VCVT_U_N
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229 UNSPEC_VCVT_HF_S_N
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230 UNSPEC_VCVT_HF_U_N
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231 UNSPEC_VCVT_SI_S_N
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232 UNSPEC_VCVT_SI_U_N
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233 UNSPEC_VCVTH_S
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234 UNSPEC_VCVTH_U
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235 UNSPEC_VCVTA_S
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236 UNSPEC_VCVTA_U
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237 UNSPEC_VCVTM_S
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238 UNSPEC_VCVTM_U
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239 UNSPEC_VCVTN_S
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240 UNSPEC_VCVTN_U
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241 UNSPEC_VCVTP_S
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242 UNSPEC_VCVTP_U
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243 UNSPEC_VEXT
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244 UNSPEC_VHADD_S
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245 UNSPEC_VHADD_U
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246 UNSPEC_VRHADD_S
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247 UNSPEC_VRHADD_U
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248 UNSPEC_VHSUB_S
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249 UNSPEC_VHSUB_U
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250 UNSPEC_VLD1
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251 UNSPEC_VLD1_LANE
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252 UNSPEC_VLD2
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253 UNSPEC_VLD2_DUP
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254 UNSPEC_VLD2_LANE
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255 UNSPEC_VLD3
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256 UNSPEC_VLD3A
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257 UNSPEC_VLD3B
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258 UNSPEC_VLD3_DUP
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259 UNSPEC_VLD3_LANE
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260 UNSPEC_VLD4
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261 UNSPEC_VLD4A
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262 UNSPEC_VLD4B
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263 UNSPEC_VLD4_DUP
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264 UNSPEC_VLD4_LANE
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265 UNSPEC_VMAX
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266 UNSPEC_VMAX_U
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267 UNSPEC_VMAXNM
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268 UNSPEC_VMIN
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269 UNSPEC_VMIN_U
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270 UNSPEC_VMINNM
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271 UNSPEC_VMLA
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272 UNSPEC_VMLA_LANE
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273 UNSPEC_VMLAL_S
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274 UNSPEC_VMLAL_U
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275 UNSPEC_VMLAL_S_LANE
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276 UNSPEC_VMLAL_U_LANE
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277 UNSPEC_VMLS
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278 UNSPEC_VMLS_LANE
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279 UNSPEC_VMLSL_S
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280 UNSPEC_VMLSL_U
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281 UNSPEC_VMLSL_S_LANE
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282 UNSPEC_VMLSL_U_LANE
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283 UNSPEC_VMLSL_LANE
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284 UNSPEC_VFMA_LANE
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285 UNSPEC_VFMS_LANE
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286 UNSPEC_VMOVL_S
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287 UNSPEC_VMOVL_U
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288 UNSPEC_VMOVN
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289 UNSPEC_VMUL
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290 UNSPEC_VMULL_P
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291 UNSPEC_VMULL_S
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292 UNSPEC_VMULL_U
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293 UNSPEC_VMUL_LANE
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294 UNSPEC_VMULL_S_LANE
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295 UNSPEC_VMULL_U_LANE
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296 UNSPEC_VPADAL_S
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297 UNSPEC_VPADAL_U
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298 UNSPEC_VPADD
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299 UNSPEC_VPADDL_S
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300 UNSPEC_VPADDL_U
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301 UNSPEC_VPMAX
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302 UNSPEC_VPMAX_U
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303 UNSPEC_VPMIN
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304 UNSPEC_VPMIN_U
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305 UNSPEC_VPSMAX
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306 UNSPEC_VPSMIN
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307 UNSPEC_VPUMAX
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308 UNSPEC_VPUMIN
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309 UNSPEC_VQABS
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310 UNSPEC_VQADD_S
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311 UNSPEC_VQADD_U
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312 UNSPEC_VQDMLAL
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313 UNSPEC_VQDMLAL_LANE
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314 UNSPEC_VQDMLSL
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315 UNSPEC_VQDMLSL_LANE
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316 UNSPEC_VQDMULH
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317 UNSPEC_VQDMULH_LANE
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318 UNSPEC_VQRDMULH
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319 UNSPEC_VQRDMULH_LANE
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320 UNSPEC_VQDMULL
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321 UNSPEC_VQDMULL_LANE
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322 UNSPEC_VQMOVN_S
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323 UNSPEC_VQMOVN_U
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324 UNSPEC_VQMOVUN
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325 UNSPEC_VQNEG
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326 UNSPEC_VQSHL_S
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327 UNSPEC_VQSHL_U
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328 UNSPEC_VQRSHL_S
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329 UNSPEC_VQRSHL_U
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330 UNSPEC_VQSHL_S_N
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331 UNSPEC_VQSHL_U_N
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332 UNSPEC_VQSHLU_N
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333 UNSPEC_VQSHRN_S_N
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334 UNSPEC_VQSHRN_U_N
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335 UNSPEC_VQRSHRN_S_N
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336 UNSPEC_VQRSHRN_U_N
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337 UNSPEC_VQSHRUN_N
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338 UNSPEC_VQRSHRUN_N
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339 UNSPEC_VQSUB_S
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340 UNSPEC_VQSUB_U
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341 UNSPEC_VRECPE
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342 UNSPEC_VRECPS
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343 UNSPEC_VREV16
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|
|
344 UNSPEC_VREV32
|
|
|
345 UNSPEC_VREV64
|
|
|
346 UNSPEC_VRSQRTE
|
|
|
347 UNSPEC_VRSQRTS
|
|
|
348 UNSPEC_VSHL_S
|
|
|
349 UNSPEC_VSHL_U
|
|
|
350 UNSPEC_VRSHL_S
|
|
|
351 UNSPEC_VRSHL_U
|
|
|
352 UNSPEC_VSHLL_S_N
|
|
|
353 UNSPEC_VSHLL_U_N
|
|
|
354 UNSPEC_VSHL_N
|
|
|
355 UNSPEC_VSHR_S_N
|
|
|
356 UNSPEC_VSHR_U_N
|
|
|
357 UNSPEC_VRSHR_S_N
|
|
|
358 UNSPEC_VRSHR_U_N
|
|
|
359 UNSPEC_VSHRN_N
|
|
|
360 UNSPEC_VRSHRN_N
|
|
|
361 UNSPEC_VSLI
|
|
|
362 UNSPEC_VSRA_S_N
|
|
|
363 UNSPEC_VSRA_U_N
|
|
|
364 UNSPEC_VRSRA_S_N
|
|
|
365 UNSPEC_VRSRA_U_N
|
|
|
366 UNSPEC_VSRI
|
|
|
367 UNSPEC_VST1
|
|
|
368 UNSPEC_VST1_LANE
|
|
|
369 UNSPEC_VST2
|
|
|
370 UNSPEC_VST2_LANE
|
|
|
371 UNSPEC_VST3
|
|
|
372 UNSPEC_VST3A
|
|
|
373 UNSPEC_VST3B
|
|
|
374 UNSPEC_VST3_LANE
|
|
|
375 UNSPEC_VST4
|
|
|
376 UNSPEC_VST4A
|
|
|
377 UNSPEC_VST4B
|
|
|
378 UNSPEC_VST4_LANE
|
|
|
379 UNSPEC_VSTRUCTDUMMY
|
|
|
380 UNSPEC_VSUB
|
|
|
381 UNSPEC_VSUBHN
|
|
|
382 UNSPEC_VRSUBHN
|
|
|
383 UNSPEC_VSUBL_S
|
|
|
384 UNSPEC_VSUBL_U
|
|
|
385 UNSPEC_VSUBW_S
|
|
|
386 UNSPEC_VSUBW_U
|
|
|
387 UNSPEC_VTBL
|
|
|
388 UNSPEC_VTBX
|
|
|
389 UNSPEC_VTRN1
|
|
|
390 UNSPEC_VTRN2
|
|
|
391 UNSPEC_VTST
|
|
|
392 UNSPEC_VUZP1
|
|
|
393 UNSPEC_VUZP2
|
|
|
394 UNSPEC_VZIP1
|
|
|
395 UNSPEC_VZIP2
|
|
|
396 UNSPEC_MISALIGNED_ACCESS
|
|
|
397 UNSPEC_VCLE
|
|
|
398 UNSPEC_VCLT
|
|
|
399 UNSPEC_NVRINTZ
|
|
|
400 UNSPEC_NVRINTP
|
|
|
401 UNSPEC_NVRINTM
|
|
|
402 UNSPEC_NVRINTX
|
|
|
403 UNSPEC_NVRINTA
|
|
|
404 UNSPEC_NVRINTN
|
|
|
405 UNSPEC_VQRDMLAH
|
|
|
406 UNSPEC_VQRDMLSH
|
|
|
407 UNSPEC_VRND
|
|
|
408 UNSPEC_VRNDA
|
|
|
409 UNSPEC_VRNDI
|
|
|
410 UNSPEC_VRNDM
|
|
|
411 UNSPEC_VRNDN
|
|
|
412 UNSPEC_VRNDP
|
|
|
413 UNSPEC_VRNDX
|
|
|
414 UNSPEC_DOT_S
|
|
|
415 UNSPEC_DOT_U
|
|
131
|
416 UNSPEC_VFML_LO
|
|
|
417 UNSPEC_VFML_HI
|
|
111
|
418 ])
|
