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1 ;; Predicates of machine description for CR16.
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2 ;; Copyright (C) 2012-2018 Free Software Foundation, Inc.
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3 ;; Contributed by KPIT Cummins Infosystems Limited.
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4 ;;
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5 ;; This file is part of GCC.
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6 ;;
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7 ;; GCC is free software; you can redistribute it and/or modify it
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8 ;; under the terms of the GNU General Public License as published
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9 ;; by the Free Software Foundation; either version 3, or (at your
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10 ;; option) any later version.
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11 ;;
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12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
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13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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15 ;; License for more details.
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16 ;;
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17 ;; You should have received a copy of the GNU General Public License
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18 ;; along with GCC; see the file COPYING3. If not see
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19 ;; <http://www.gnu.org/licenses/>.
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20
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21 ;; Predicates
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22
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23 ;; Predicates for sbit/cbit instructions
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24 ;; bit operand used for the generation of bit insn generation
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25 (define_predicate "bit_operand"
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26 (match_code "mem")
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27 {
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28 return ((GET_CODE (op) == MEM && OK_FOR_Z (op)));
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29 })
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30
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31 ;; Unsigned 4-bits constant int or double value.
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32 (define_predicate "u4bits_operand"
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33 (match_code "const_int,const_double")
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34 {
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35 if (GET_CODE (op) == CONST_DOUBLE)
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36 return cr16_const_double_ok (op);
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37 return (UNSIGNED_INT_FITS_N_BITS(INTVAL (op), 4)) ? 1 : 0;
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38 })
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39
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40 ;; Operand is a constant integer where
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41 ;; only one bit is set to 1.
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42 (define_predicate "one_bit_operand"
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43 (match_code "const_int")
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44 {
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45 unsigned int val;
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46
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47 val = INTVAL (op);
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48 if (mode == QImode)
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49 val &= 0xff;
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50 else if (mode == HImode)
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51 val &= 0xffff;
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52 else
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53 gcc_unreachable();
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54
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55 if (val != 0)
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56 return (val & (val - 1)) == 0; /* true if only one bit is set. */
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57 else
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58 return 0;
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59 })
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60
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61 ;; Operand is a constant integer where
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62 ;; only one bit is set to 0.
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63 (define_predicate "rev_one_bit_operand"
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64 (match_code "const_int")
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65 {
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66 unsigned int val;
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67
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68 val = ~INTVAL (op); /* Invert and use. */
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69 if (mode == QImode)
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70 val &= 0xff;
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71 else if (mode == HImode)
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72 val &= 0xffff;
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73 else
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74 gcc_unreachable();
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75
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76 if (val != 0)
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77 return (val & (val - 1)) == 0; /* true if only one bit is set. */
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78 else
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79 return 0;
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80 })
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81
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82 ;; Predicates for shift instructions
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83 ;; Immediate operand predicate for count in shift operations.
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84 ;; Immediate shall be 3-bits in case operand to be operated on
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85 ;; is a qi mode operand.
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86 (define_predicate "shift_qi_imm_operand"
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87 (match_code "const_int")
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88 {
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89 return (UNSIGNED_INT_FITS_N_BITS(INTVAL (op), 3)) ? 1 : 0;
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90 })
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91
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92 ;; Immediate shall be 4-bits in case operand to be operated on
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93 ;; is a hi mode operand.
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94 (define_predicate "shift_hi_imm_operand"
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95 (match_code "const_int")
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96 {
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97 return (UNSIGNED_INT_FITS_N_BITS(INTVAL (op), 4)) ? 1 : 0;
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98 })
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99
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100 ;; Immediate shall be 3-bits in case operand to be operated on
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101 ;; is a si mode operand.
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102 (define_predicate "shift_si_imm_operand"
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103 (match_code "const_int")
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104 {
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105 return (UNSIGNED_INT_FITS_N_BITS(INTVAL (op), 5)) ? 1 : 0;
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106 })
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107
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108 ;; Predicates for jump/call instructions
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109 ;; Jump immediate cannot be more than 24-bits
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110 (define_predicate "jump_imm_operand"
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111 (match_code "const_int")
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112 {
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113 return (UNSIGNED_INT_FITS_N_BITS(INTVAL (op), 24)) ? 1 : 0;
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114 })
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115
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116 ;; Call immediate cannot be more than 24-bits
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117 (define_predicate "call_imm_operand"
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118 (match_operand 0 "immediate_operand")
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119 {
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120 if (GET_CODE (op) != CONST_INT) return 1;
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121 return (UNSIGNED_INT_FITS_N_BITS(INTVAL (op), 24)) ? 1 : 0;
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122 })
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123
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124 ;; Operand is register or 4-bit immediate operand
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125 (define_predicate "reg_or_u4bits_operand"
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126 (ior (match_operand 0 "u4bits_operand")
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127 (match_operand 0 "register_operand")))
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128
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129 ;; Operand is a register or symbol reference
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130 (define_predicate "reg_or_sym_operand"
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131 (ior (match_code "symbol_ref")
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132 (match_operand 0 "register_operand")))
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133
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134 ;; Operand is a non stack pointer register
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135 (define_predicate "nosp_reg_operand"
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136 (and (match_operand 0 "register_operand")
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137 (match_test "REGNO (op) != SP_REGNUM")))
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138
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139 (define_predicate "hard_reg_operand"
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140 (and (match_operand 0 "register_operand")
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141 (match_test "REGNO (op) <= 15")))
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142
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143 ;; Operand is a memory reference and
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144 ;; not a push operand.
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145 (define_predicate "store_operand"
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146 (and (match_operand 0 "memory_operand")
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147 (not (match_operand 0 "push_operand"))))
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148
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149 ;; Helper predicate
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150 (define_predicate "reg_or_int_operand"
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151 (ior (match_code "const_int")
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152 (match_operand 0 "register_operand")))
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153
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154 ;;
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155 ;;
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156 ;; Atithmetic/logical predicates
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157
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158 ;; QI Helper
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159 (define_predicate "arith_qi_operand"
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160 (match_code "const_int")
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161 {
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162 return (IN_RAN(INTVAL (op), 0, 15) && ((INTVAL (op) != 9)
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163 || (INTVAL (op) != 11))) ? 1 : 0 ;
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164 })
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165
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166 ;;QI Reg, subreg(reg) or const_int.
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167 (define_predicate "reg_qi_int_operand"
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168 (ior (match_operand 0 "arith_qi_operand")
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169 (match_operand 0 "register_operand")))
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170
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171 ;; HI Helper
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172 (define_predicate "arith_hi_operand"
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173 (match_code "const_int")
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174 {
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175 return (IN_RAN(INTVAL (op), -32768, 32768) ) ? 1 : 0 ;
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176 })
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177
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178 ;;HI Reg, subreg(reg) or const_int.
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179 (define_predicate "reg_hi_int_operand"
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180 (ior (match_operand 0 "arith_hi_operand")
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181 (match_operand 0 "register_operand")))
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182
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183 ;;SI Reg, subreg(reg) or const_int.
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184 (define_predicate "reg_si_int_operand"
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185 (ior (match_operand 0 "const_int_operand")
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186 (match_operand 0 "register_operand")))
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187
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188 ;;
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189 ;; Shift predicates
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190
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191 ;; QI Helper
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192 (define_predicate "shift_qi_operand"
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193 (match_code "const_int")
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194 {
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195 return (IN_RAN(INTVAL (op), 0, 7) ) ? 1 : 0;
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196 })
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197
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198 ;;QI Reg, subreg(reg) or const_int.
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199 (define_predicate "shift_reg_qi_int_operand"
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200 (ior (match_operand 0 "shift_qi_operand")
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201 (match_operand 0 "register_operand")))
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202
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203 ;; HI Helper
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204 (define_predicate "shift_hi_operand"
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205 (match_code "const_int")
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206 {
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207 return (IN_RAN(INTVAL (op), 0, 15) ) ? 1 : 0 ;
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208 })
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209
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210 ;;HI Reg, subreg(reg) or const_int.
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211 (define_predicate "shift_reg_hi_int_operand"
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212 (ior (match_operand 0 "shift_hi_operand")
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213 (match_operand 0 "register_operand")))
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214
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215 ;; SI Helper
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216 (define_predicate "shift_si_operand"
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217 (match_code "const_int")
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218 {
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219 return (IN_RAN(INTVAL (op), 0, 31) ) ? 1 : 0;
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220 })
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221
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222 ;;SI Reg, subreg(reg) or const_int.
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223 (define_predicate "shift_reg_si_int_operand"
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224 (ior (match_operand 0 "shift_si_operand")
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225 (match_operand 0 "register_operand")))
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