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1 ;; Constraint definitions for Adaptiva epiphany
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2 ;; Copyright (C) 2007-2018 Free Software Foundation, Inc.
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3 ;; Contributed by Embecosm on behalf of Adapteva, Inc.
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4
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5 ;; This file is part of GCC.
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6
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7 ;; GCC is free software; you can redistribute it and/or modify
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8 ;; it under the terms of the GNU General Public License as published by
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9 ;; the Free Software Foundation; either version 3, or (at your option)
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10 ;; any later version.
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11
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12 ;; GCC is distributed in the hope that it will be useful,
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13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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15 ;; GNU General Public License for more details.
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16
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17 ;; You should have received a copy of the GNU General Public License
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18 ;; along with GCC; see the file COPYING3. If not see
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19 ;; <http://www.gnu.org/licenses/>.
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20
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21 ;; Integer constraints
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22
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23 (define_constraint "U16"
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24 "An unsigned 16-bit constant."
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25 (ior (and (match_code "const_int")
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26 (match_test "IMM16 (ival)"))
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27 (and (match_code "symbol_ref,label_ref,const")
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28 (match_test "epiphany_small16 (op)"))))
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29
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30 (define_constraint "K"
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31 "An unsigned 5-bit constant."
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32 (and (match_code "const_int")
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33 (match_test "IMM5 (ival)")))
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34
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35 ;; This could also accept symbol_ref, label_ref or const if we introduce
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36 ;; a small area and/or attribute that satisfies the 11-bit signed range.
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37 (define_constraint "L"
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38 "A signed 11-bit constant."
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39 (and (match_code "const_int")
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40 (match_test "SIMM11 (ival)")))
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41
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42 (define_constraint "CnL"
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43 "A negated signed 11-bit constant."
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44 (and (match_code "const_int")
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45 (match_test "SIMM11 (-ival)")))
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46
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47 (define_constraint "Cm1"
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48 "A signed 11-bit constant added to -1"
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49 (and (match_code "const_int")
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50 (match_test "SIMM11 (ival+1)")
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51 (match_test "epiphany_m1reg >= 0")))
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52
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53 (define_constraint "Cl1"
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54 "Left-shift of -1"
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55 (and (match_code "const_int")
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56 (match_test "ival == (ival | ~(ival-1))")
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57 (match_test "epiphany_m1reg >= 0")))
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58
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59 (define_constraint "Cr1"
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60 "Right-shift of -1"
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61 (and (match_code "const_int")
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62 (match_test "ival == (ival & ~(ival+1))")
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63 (match_test "epiphany_m1reg >= 0")))
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64
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65 (define_constraint "Cal"
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66 "Constant for arithmetic/logical operations"
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67 (match_test "(flag_pic
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68 ? nonsymbolic_immediate_operand (op, VOIDmode)
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69 : immediate_operand (op, VOIDmode))"))
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70
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71 (define_constraint "Csy"
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72 "Symbolic constant for call/jump instruction"
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73 (match_test "symbolic_operand (op, VOIDmode)"))
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74
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75 ;; Register constraints
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76 ;; proper register constraints define a register class and can thus
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77 ;; drive register allocation and reload. OTOH sometimes we want to
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78 ;; avoid just that.
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79
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80 ;; The register class usable in short insns.
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81 ;; Subject to TARGET_PREFER_SHORT_INSN_REGS.
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82 (define_register_constraint "Rcs" "SHORT_INSN_REGS"
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83 "short insn register class.")
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84
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85 ; The registers that can be used to hold a sibcall call address.
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86 ; This must not conflict with any callee-saved registers.
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87 (define_register_constraint "Rsc" "SIBCALL_REGS"
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88 "sibcall register class")
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89
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90 ; The registers that can be used to hold a status value
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91 (define_register_constraint "Rct" "CORE_CONTROL_REGS"
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92 "Core control register class")
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93
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94 ;; The register group usable in short insns.
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95 (define_constraint "Rgs"
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96 "short insn register group."
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97 (and (match_code "reg")
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98 (match_test "REGNO (op) >= FIRST_PSEUDO_REGISTER || REGNO (op) <= 7")))
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99
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100 ;; Constant suitable for the addsi3_r pattern.
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101 (define_constraint "Car"
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102 "addsi3_r constant."
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103 (and (match_code "const_int")
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104 (ior (match_test "RTX_OK_FOR_OFFSET_P (SImode, op)")
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105 (match_test "RTX_OK_FOR_OFFSET_P (HImode, op)")
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106 (match_test "RTX_OK_FOR_OFFSET_P (QImode, op)"))))
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107
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108 ;; The return address if it can be replaced with GPR_LR.
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109 (define_constraint "Rra"
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110 "return address constraint - register variant"
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111 (and (match_code "unspec")
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112 (match_test "XINT (op, 1) == UNSPEC_RETURN_ADDR")
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113 (match_test "!MACHINE_FUNCTION (cfun)->lr_clobbered")))
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114
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115 (define_constraint "Rcc"
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116 "integer condition code"
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117 (and (match_code "reg")
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118 (match_test "REGNO (op) == CC_REGNUM")))
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119
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120 ;; The return address, which might be a stack slot. */
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121 (define_constraint "Sra"
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122 "return address constraint - memory variant"
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123 (and (match_code "unspec")
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124 (match_test "XINT (op, 1) == UNSPEC_RETURN_ADDR")))
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125
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126 (define_constraint "Cfm"
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127 "control register values to switch fp mode"
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128 (and (match_code "const")
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129 (match_test "GET_CODE (XEXP (op, 0)) == UNSPEC")
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130 (match_test "XINT (XEXP (op, 0), 1) == UNSPEC_FP_MODE")))
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