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111
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1 ;; Predicate definitions for code generation on the EPIPHANY cpu.
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131
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2 ;; Copyright (C) 1994-2018 Free Software Foundation, Inc.
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111
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3 ;; Contributed by Embecosm on behalf of Adapteva, Inc.
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4 ;;
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5 ;; This file is part of GCC.
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6
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7 ;; GCC is free software; you can redistribute it and/or modify
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8 ;; it under the terms of the GNU General Public License as published by
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9 ;; the Free Software Foundation; either version 3, or (at your option)
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10 ;; any later version.
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11
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12 ;; GCC is distributed in the hope that it will be useful,
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13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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15 ;; GNU General Public License for more details.
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16
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17 ;; You should have received a copy of the GNU General Public License
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18 ;; along with GCC; see the file COPYING3. If not see
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19 ;; <http://www.gnu.org/licenses/>.
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20
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21 ;; Returns true iff OP is a symbol reference that is a valid operand
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22 ;; in a jump or call instruction.
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23
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24 (define_predicate "symbolic_operand"
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25 (match_code "symbol_ref,label_ref,const")
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26 {
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27 if (GET_CODE (op) == SYMBOL_REF)
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28 return (!epiphany_is_long_call_p (op)
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29 && (!flag_pic || SYMBOL_REF_LOCAL_P (op)));
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30 if (GET_CODE (op) == LABEL_REF)
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31 return true;
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32 if (GET_CODE (op) == CONST)
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33 {
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34 op = XEXP (op, 0);
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35 if (GET_CODE (op) != PLUS || !symbolic_operand (XEXP (op, 0), mode))
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36 return false;
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37 /* The idea here is that a 'small' constant offset should be OK.
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38 What exactly is considered 'small' is a bit arbitrary. */
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39 return satisfies_constraint_L (XEXP (op, 1));
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40 }
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41 gcc_unreachable ();
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42 })
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43
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44 ;; Acceptable arguments to the call insn.
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45
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46 (define_predicate "call_address_operand"
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47 (ior (match_code "reg")
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48 (match_operand 0 "symbolic_operand")))
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49
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50 (define_predicate "call_operand"
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51 (match_code "mem")
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52 {
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53 op = XEXP (op, 0);
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54 return call_address_operand (op, mode);
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55 })
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56
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57 ;; general purpose register.
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58 (define_predicate "gpr_operand"
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59 (match_code "reg,subreg")
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60 {
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61 int regno;
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62
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63 if (!register_operand (op, mode))
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64 return 0;
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65 if (GET_CODE (op) == SUBREG)
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66 op = XEXP (op, 0);
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67 regno = REGNO (op);
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68 return regno >= FIRST_PSEUDO_REGISTER || regno <= 63;
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69 })
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70
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71 (define_special_predicate "any_gpr_operand"
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72 (match_code "subreg,reg")
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73 {
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74 return gpr_operand (op, mode);
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75 })
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76
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77 ;; register suitable for integer add / sub operations; besides general purpose
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78 ;; registers we allow fake hard registers that are eliminated to a real
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79 ;; hard register via an offset.
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80 (define_predicate "add_reg_operand"
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81 (match_code "reg,subreg")
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82 {
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83 int regno;
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84
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85 if (!register_operand (op, mode))
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86 return 0;
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87 if (GET_CODE (op) == SUBREG)
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88 op = XEXP (op, 0);
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89 regno = REGNO (op);
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90 return (regno >= FIRST_PSEUDO_REGISTER || regno <= 63
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91 || regno == FRAME_POINTER_REGNUM
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92 || regno == ARG_POINTER_REGNUM);
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93 })
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94
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95 ;; Also allows suitable constants
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96 (define_predicate "add_operand"
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97 (match_code "reg,subreg,const_int,symbol_ref,label_ref,const")
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98 {
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99 if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
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100 return add_reg_operand (op, mode);
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101 return satisfies_constraint_L (op) || satisfies_constraint_CnL (op);
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102 })
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103
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104 ;; Ordinary 3rd operand for arithmetic operations
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105 (define_predicate "arith_operand"
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106 (match_code "reg,subreg,const_int,symbol_ref,label_ref,const")
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107 {
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108 if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
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109 return register_operand (op, mode);
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110 return satisfies_constraint_L (op);
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111 })
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112
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113 ;; Constant integer 3rd operand for arithmetic operations
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114 (define_predicate "arith_int_operand"
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115 (match_code "const_int,symbol_ref,label_ref,const")
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116 {
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117 return satisfies_constraint_L (op);
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118 })
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119
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120 ;; Return true if OP is an acceptable argument for a single word move source.
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121
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122 (define_predicate "move_src_operand"
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123 (match_code
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124 "symbol_ref,label_ref,const,const_int,const_double,reg,subreg,mem,unspec")
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125 {
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126 switch (GET_CODE (op))
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127 {
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128 case SYMBOL_REF :
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129 case LABEL_REF :
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130 case CONST :
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131 return 1;
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132 case CONST_INT :
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133 return immediate_operand (op, mode);
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134 case CONST_DOUBLE :
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135 /* SImode constants should always fit into a CONST_INT. Large
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136 unsigned 32-bit constants are represented as negative CONST_INTs. */
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137 gcc_assert (GET_MODE (op) != SImode);
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138 /* We can handle 32-bit floating point constants. */
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139 if (mode == SFmode)
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140 return GET_MODE (op) == SFmode;
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141 return 0;
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142 case REG :
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143 return op != frame_pointer_rtx && register_operand (op, mode);
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144 case SUBREG :
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145 /* (subreg (mem ...) ...) can occur here if the inner part was once a
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146 pseudo-reg and is now a stack slot. */
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147 if (GET_CODE (SUBREG_REG (op)) == MEM)
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148 return address_operand (XEXP (SUBREG_REG (op), 0), mode);
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149 else
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150 return register_operand (op, mode);
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151 case MEM :
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152 return address_operand (XEXP (op, 0), mode);
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153 case UNSPEC:
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154 return satisfies_constraint_Sra (op);
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155 default :
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156 return 0;
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157 }
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158 })
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159
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160 ;; Return true if OP is an acceptable argument for a double word move source.
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161
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162 (define_predicate "move_double_src_operand"
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163 (match_code "reg,subreg,mem,const_int,const_double,const_vector")
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164 {
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165 if (GET_CODE (op) == MEM && misaligned_operand (op, mode)
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166 && !address_operand (plus_constant (Pmode, XEXP (op, 0), 4), SImode))
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167 return 0;
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168 return general_operand (op, mode);
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169 })
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170
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171 ;; Return true if OP is an acceptable argument for a move destination.
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172
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173 (define_predicate "move_dest_operand"
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174 (match_code "reg,subreg,mem")
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175 {
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176 switch (GET_CODE (op))
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177 {
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178 case REG :
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179 return register_operand (op, mode);
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180 case SUBREG :
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181 /* (subreg (mem ...) ...) can occur here if the inner part was once a
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182 pseudo-reg and is now a stack slot. */
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183 if (GET_CODE (SUBREG_REG (op)) == MEM)
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184 {
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185 return address_operand (XEXP (SUBREG_REG (op), 0), mode);
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186 }
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187 else
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188 {
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189 return register_operand (op, mode);
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190 }
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191 case MEM :
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192 if (GET_MODE_SIZE (mode) == 8 && misaligned_operand (op, mode)
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193 && !address_operand (plus_constant (Pmode, XEXP (op, 0), 4), SImode))
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194 return 0;
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195 return address_operand (XEXP (op, 0), mode);
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196 default :
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197 return 0;
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198 }
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199 })
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200
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201 (define_special_predicate "stacktop_operand"
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202 (match_code "mem")
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203 {
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204 if (mode != VOIDmode && GET_MODE (op) != mode)
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205 return false;
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206 return rtx_equal_p (XEXP (op, 0), stack_pointer_rtx);
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207 })
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208
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209 ;; Return 1 if OP is a comparison operator valid for the mode of CC.
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210 ;; This allows the use of MATCH_OPERATOR to recognize all the branch insns.
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211 ;;
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212 ;; Some insns only set a few bits in the condition code. So only allow those
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213 ;; comparisons that use the bits that are valid.
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214
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215 (define_predicate "proper_comparison_operator"
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216 (match_code "eq, ne, le, lt, ge, gt, leu, ltu, geu, gtu, unordered, ordered, uneq, unge, ungt, unle, unlt, ltgt")
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217 {
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218 enum rtx_code code = GET_CODE (op);
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219 rtx cc = XEXP (op, 0);
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220
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221 /* combine can try strange things. */
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222 if (!REG_P (cc))
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223 return 0;
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224 switch (GET_MODE (cc))
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225 {
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226 case E_CC_Zmode:
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227 case E_CC_N_NEmode:
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228 case E_CC_FP_EQmode:
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229 return REGNO (cc) == CC_REGNUM && (code == EQ || code == NE);
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230 case E_CC_C_LTUmode:
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231 return REGNO (cc) == CC_REGNUM && (code == LTU || code == GEU);
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232 case E_CC_C_GTUmode:
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233 return REGNO (cc) == CC_REGNUM && (code == GTU || code == LEU);
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234 case E_CC_FPmode:
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235 return (REGNO (cc) == CCFP_REGNUM
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236 && (code == EQ || code == NE || code == LT || code == LE));
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237 case E_CC_FP_GTEmode:
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238 return (REGNO (cc) == CC_REGNUM
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239 && (code == EQ || code == NE || code == GT || code == GE
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240 || code == UNLE || code == UNLT));
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241 case E_CC_FP_ORDmode:
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242 return REGNO (cc) == CC_REGNUM && (code == ORDERED || code == UNORDERED);
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243 case E_CC_FP_UNEQmode:
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244 return REGNO (cc) == CC_REGNUM && (code == UNEQ || code == LTGT);
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245 case E_CCmode:
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246 return REGNO (cc) == CC_REGNUM;
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247 /* From combiner. */
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248 case E_QImode: case E_SImode: case E_SFmode: case E_HImode:
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249 /* From cse.c:dead_libcall_p. */
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250 case E_DFmode:
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251 return 0;
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252 default:
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253 gcc_unreachable ();
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254 }
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255 })
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256
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257 (define_predicate "addsub_operator"
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258 (match_code "plus, minus"))
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259
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260 (define_predicate "cc_operand"
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261 (and (match_code "reg")
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262 (match_test "REGNO (op) == CC_REGNUM || REGNO (op) == CCFP_REGNUM")))
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263
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264 (define_predicate "const0_operand"
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265 (match_code "const_int, const_double")
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266 {
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267 if (mode == VOIDmode)
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268 mode = GET_MODE (op);
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269 return op == CONST0_RTX (mode);
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270 })
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271
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272 (define_predicate "const_float_1_operand"
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273 (match_code "const_double")
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274 {
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275 return op == CONST1_RTX (mode);
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276 })
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277
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278 (define_predicate "cc_move_operand"
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279 (and (match_code "reg")
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280 (ior (match_test "REGNO (op) == CC_REGNUM")
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281 (match_test "gpr_operand (op, mode)"))))
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282
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283 (define_predicate "float_operation"
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284 (match_code "parallel")
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285 {
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286 /* Most patterns start out with one SET and one CLOBBER, and gain a USE
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287 or two of FP_NEAREST_REGNUM / FP_TRUNCATE_REGNUM / FP_ANYFP_REGNUM
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288 after mode switching. The longer patterns are
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289 all beyond length 4, and before mode switching, end with a
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290 CLOBBER of CCFP_REGNUM. */
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291 int count = XVECLEN (op, 0);
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292 bool inserted = MACHINE_FUNCTION (cfun)->control_use_inserted;
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293 int i;
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294
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295 if (count == 2
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296 /* Vector ashift has an extra use for the constant factor required to
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297 implement the shift as multiply. */
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298 || (count == 3 && GET_CODE (XVECEXP (op, 0, 0)) == SET
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299 && GET_CODE (XEXP (XVECEXP (op, 0, 0), 1)) == ASHIFT))
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300 return !inserted;
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301
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302 /* combine / recog will pass any old garbage here before checking the
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303 rest of the insn. */
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304 if (count <= 3)
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305 return false;
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306
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307 i = 1;
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308 if (count > 4)
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309 for (i = 2; i < count; i++)
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310 {
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311 rtx x = XVECEXP (op, 0, i);
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312
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313 if (GET_CODE (x) == CLOBBER)
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314 {
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315 if (!REG_P (XEXP (x, 0)))
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316 return false;
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317 if (REGNO (XEXP (x, 0)) == CCFP_REGNUM)
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318 {
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319 if (count == i + 1)
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320 return !inserted;
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321 break;
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322 }
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323 /* Just an ordinary clobber, keep looking. */
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324 }
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325 else if (GET_CODE (x) == USE
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326 || (GET_CODE (x) == SET && i == 2))
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327 continue;
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328 else
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329 return false;
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330 }
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331 if (count != i + 3 || !inserted)
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332 return false;
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333 for (i = i+1; i < count; i++)
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334 {
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335 rtx x = XVECEXP (op, 0, i);
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336
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337 if (GET_CODE (x) != USE && GET_CODE (x) != CLOBBER)
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338 return false;
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339 x = XEXP (x, 0);
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340 if (!REG_P (x)
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341 || (REGNO (x) != FP_NEAREST_REGNUM
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342 && REGNO (x) != FP_TRUNCATE_REGNUM
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343 && REGNO (x) != FP_ANYFP_REGNUM))
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344 return false;
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345 }
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346 return true;
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347 })
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348
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349 (define_predicate "set_fp_mode_operand"
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350 (ior (match_test "gpr_operand (op, mode)")
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351 (and (match_code "const")
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352 (match_test "satisfies_constraint_Cfm (op)"))))
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353
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354 (define_predicate "post_modify_address"
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355 (match_code "post_modify,post_inc,post_dec"))
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356
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357 (define_predicate "post_modify_operand"
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358 (and (match_code "mem")
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359 (match_test "post_modify_address (XEXP (op, 0), Pmode)")))
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360
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361 ; used in the memory clobber of stack_adjust_str, allows addresses with
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362 ; large offsets.
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363 (define_predicate "memclob_operand"
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364 (match_code "mem"))
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365
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366 (define_predicate "nonsymbolic_immediate_operand"
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367 (ior (match_test "immediate_operand (op, mode)")
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368 (match_code "const_vector"))) /* Is this specific enough? */
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369
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370 ;; Return true if OP is misaligned memory operand
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371 (define_predicate "misaligned_operand"
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372 (and (match_code "mem")
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373 (match_test "MEM_ALIGN (op) < GET_MODE_ALIGNMENT (mode)")))
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