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111
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1 ;; Machine description for FT32
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131
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2 ;; Copyright (C) 2015-2018 Free Software Foundation, Inc.
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111
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3 ;; Contributed by FTDI <support@ftdi.com>
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4
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5 ;; This file is part of GCC.
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6
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7 ;; GCC is free software; you can redistribute it and/or modify it
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8 ;; under the terms of the GNU General Public License as published
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9 ;; by the Free Software Foundation; either version 3, or (at your
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10 ;; option) any later version.
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11
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12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
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13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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15 ;; License for more details.
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16
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17 ;; You should have received a copy of the GNU General Public License
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18 ;; along with GCC; see the file COPYING3. If not see
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19 ;; <http://www.gnu.org/licenses/>.
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20
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21 ;; -------------------------------------------------------------------------
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22 ;; FT32 specific constraints, predicates and attributes
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23 ;; -------------------------------------------------------------------------
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24
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25 (include "constraints.md")
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26 (include "predicates.md")
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27
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28 (define_constants [
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29 (FP_REG 0)
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30 (SP_REG 1)
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31 (CC_REG 35)
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32 ])
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33
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34 (define_c_enum "unspec"
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35 [UNSPEC_STRLEN
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36 UNSPEC_MOVMEM
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37 UNSPEC_SETMEM
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38 UNSPEC_STPCPY
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39 UNSPEC_INDEX_JMP
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40 UNSPEC_LPM
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41 UNSPEC_FMUL
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42 UNSPEC_FMULS
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43 UNSPEC_FMULSU
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44 UNSPEC_COPYSIGN
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45 UNSPEC_IDENTITY
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46 UNSPEC_INSERT_BITS
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47 UNSPEC_JMP_EPILOG
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48 UNSPEC_JMP_EPILOG24
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49 UNSPEC_JMP_PROLOG
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50 UNSPEC_XCHG
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51 ])
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52
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53 ;; -------------------------------------------------------------------------
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54 ;; nop instruction
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55 ;; -------------------------------------------------------------------------
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56
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57 (define_insn "nop"
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58 [(const_int 0)]
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59 ""
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60 "nop")
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61
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62 ;; -------------------------------------------------------------------------
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63 ;; Arithmetic instructions
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64 ;; -------------------------------------------------------------------------
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65
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66 (define_insn "addsi3"
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67 [(set (match_operand:SI 0 "register_operand" "=r,r")
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68 (plus:SI
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69 (match_operand:SI 1 "register_operand" "r,r")
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70 (match_operand:SI 2 "ft32_rimm_operand" "KA,r")))
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71 ]
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72 ""
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73 "add.l %0,%1,%2")
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74
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75 (define_insn "subsi3"
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76 [(set (match_operand:SI 0 "register_operand" "=r,r")
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77 (minus:SI
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78 (match_operand:SI 1 "register_operand" "r,r")
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79 (match_operand:SI 2 "ft32_rimm_operand" "KA,r")))]
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80 ""
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81 "sub.l %0,%1,%2")
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82
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83 (define_insn "mulsi3"
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84 [(set (match_operand:SI 0 "register_operand" "=r,r")
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85 (mult:SI
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86 (match_operand:SI 1 "register_operand" "r,r")
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87 (match_operand:SI 2 "ft32_rimm_operand" "KA,r")))]
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88 ""
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89 "mul.l %0,%1,%2")
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90
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91 (define_insn "umulsidi3"
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92 [(set (match_operand:DI 0 "register_operand" "=r,r")
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93 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r,r"))
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94 (zero_extend:DI (match_operand:SI 2 "ft32_rimm_operand" "r,KA"))))
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95 (clobber (reg:CC CC_REG))]
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96 ""
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97 "mul.l $cc,%1,%2\;muluh.l %h0,%1,%2\;move.l %0,$cc")
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98
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99 (define_insn "divsi3"
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100 [(set (match_operand:SI 0 "register_operand" "=r,r")
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101 (div:SI
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102 (match_operand:SI 1 "register_operand" "r,r")
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103 (match_operand:SI 2 "ft32_rimm_operand" "r,KA")))]
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104 "!TARGET_NODIV"
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105 "div.l %0,%1,%2")
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106
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107 (define_insn "modsi3"
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108 [(set (match_operand:SI 0 "register_operand" "=r,r")
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109 (mod:SI
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110 (match_operand:SI 1 "register_operand" "r,r")
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111 (match_operand:SI 2 "ft32_rimm_operand" "r,KA")))]
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112 "!TARGET_NODIV"
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113 "mod.l %0,%1,%2")
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114
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115 (define_insn "udivsi3"
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116 [(set (match_operand:SI 0 "register_operand" "=r,r")
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117 (udiv:SI
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118 (match_operand:SI 1 "register_operand" "r,r")
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119 (match_operand:SI 2 "ft32_rimm_operand" "r,KA")))]
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120 "!TARGET_NODIV"
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121 "udiv.l %0,%1,%2")
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122
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123 (define_insn "umodsi3"
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124 [(set (match_operand:SI 0 "register_operand" "=r,r")
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125 (umod:SI
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126 (match_operand:SI 1 "register_operand" "r,r")
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127 (match_operand:SI 2 "register_operand" "r,KA")))]
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128 "!TARGET_NODIV"
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129 "umod.l %0,%1,%2")
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130
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131 (define_insn "extvsi"
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132 [(set (match_operand:SI 0 "register_operand" "=r")
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133 (sign_extract:SI (match_operand:SI 1 "register_operand" "r")
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134 (match_operand:SI 2 "ft32_bwidth_operand" "b")
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135 (match_operand:SI 3 "const_int_operand" "i")))]
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136 ""
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137 "bexts.l %0,%1,((15 & %2) << 5) | (%3)")
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138
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139 (define_insn "extzvsi"
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140 [(set (match_operand:SI 0 "register_operand" "=r")
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141 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
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142 (match_operand:SI 2 "ft32_bwidth_operand" "b")
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143 (match_operand:SI 3 "const_int_operand" "i")))]
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144 ""
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145 "bextu.l %0,%1,((15 & %2) << 5) | (%3)")
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146
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147 (define_insn "insvsi"
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148 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r,r")
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149 (match_operand:SI 1 "ft32_bwidth_operand" "b,b")
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150 (match_operand:SI 2 "const_int_operand" "i,i"))
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151 (match_operand:SI 3 "general_operand" "r,O"))
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152 (clobber (match_scratch:SI 4 "=&r,r"))]
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153 ""
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154 {
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155 if (which_alternative == 0)
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156 {
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157 return \"ldl.l %4,%3,((%1&15)<<5)|(%2)\;bins.l %0,%0,%4\";
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158 }
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159 else
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160 {
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161 if ((INTVAL(operands[3]) == 0) || (INTVAL(operands[1]) == 1))
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162 return \"bins.l %0,%0,(%3<<9)|((%1&15)<<5)|(%2)\";
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163 else
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164 return \"ldk.l %4,(%3<<10)|((%1&15)<<5)|(%2)\;bins.l %0,%0,%4\";
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165 }
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166 })
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167
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168 ;; -------------------------------------------------------------------------
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169 ;; Unary arithmetic instructions
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170 ;; -------------------------------------------------------------------------
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171
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172 (define_insn "one_cmplsi2"
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173 [(set (match_operand:SI 0 "register_operand" "=r")
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174 (not:SI (match_operand:SI 1 "register_operand" "r")))]
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175 ""
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176 "xor.l %0,%1,-1")
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177
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178 ;; -------------------------------------------------------------------------
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179 ;; Logical operators
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180 ;; -------------------------------------------------------------------------
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181
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182 (define_insn "andsi3"
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183 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
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184 (and:SI (match_operand:SI 1 "register_operand" "r,r,r")
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185 (match_operand:SI 2 "general_operand" "r,x,KA")))]
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186 ""
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187 "@
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188 and.l %0,%1,%2
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189 bins.l %0,%1,%g2
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190 and.l %0,%1,%2")
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191
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192 (define_insn "andqi3"
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193 [(set (match_operand:QI 0 "register_operand" "=r,r,r")
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194 (and:QI (match_operand:QI 1 "register_operand" "r,r,r")
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195 (match_operand:QI 2 "general_operand" "r,x,KA")))]
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196 ""
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197 "@
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198 and.b %0,%1,%2
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199 bins.b %0,%1,%g2
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200 and.b %0,%1,%2")
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201
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202 (define_insn "xorsi3"
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203 [(set (match_operand:SI 0 "register_operand" "=r,r")
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204 (xor:SI (match_operand:SI 1 "register_operand" "r,r")
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205 (match_operand:SI 2 "ft32_rimm_operand" "r,KA")))]
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206 ""
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207 {
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208 return "xor.l %0,%1,%2";
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209 })
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210
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211 (define_insn "iorsi3"
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212 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
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213 (ior:SI (match_operand:SI 1 "register_operand" "r,r,r")
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214 (match_operand:SI 2 "general_operand" "r,w,KA")))]
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215 ""
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216 "@
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217 or.l %0,%1,%2
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218 bins.l %0,%1,%f2
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219 or.l %0,%1,%2")
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220
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221 ;; -------------------------------------------------------------------------
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222 ;; Shifters
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223 ;; -------------------------------------------------------------------------
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224
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225 (define_insn "ashlsi3"
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226 [(set (match_operand:SI 0 "register_operand" "=r,r")
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227 (ashift:SI (match_operand:SI 1 "register_operand" "r,r")
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228 (match_operand:SI 2 "ft32_rimm_operand" "r,KA")))]
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229 ""
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230 {
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231 return "ashl.l %0,%1,%2";
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232 })
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233
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234 (define_insn "ashrsi3"
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235 [(set (match_operand:SI 0 "register_operand" "=r,r")
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236 (ashiftrt:SI (match_operand:SI 1 "register_operand" "r,r")
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237 (match_operand:SI 2 "ft32_rimm_operand" "r,KA")))]
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238 ""
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239 {
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240 return "ashr.l %0,%1,%2";
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241 })
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242
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243 (define_insn "lshrsi3"
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244 [(set (match_operand:SI 0 "register_operand" "=r,r")
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245 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,r")
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246 (match_operand:SI 2 "ft32_rimm_operand" "r,KA")))]
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247 ""
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248 {
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249 return "lshr.l %0,%1,%2";
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250 })
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251
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252 ;; -------------------------------------------------------------------------
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253 ;; Move instructions
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254 ;; -------------------------------------------------------------------------
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255
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256 ;; SImode
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257
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258 (define_insn "*sne"
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259 [(set (match_operand:SI 0 "register_operand" "=r")
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260 (reg:SI CC_REG))]
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261 ""
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262 "bextu.l %0,$cc,32|0\;xor.l %0,%0,-1"
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263 )
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264
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265 ;; Push a register onto the stack
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266 (define_insn "movsi_push"
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267 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
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268 (match_operand:SI 0 "register_operand" "r"))]
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269 ""
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270 "push.l %0")
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271
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272 ;; Pop a register from the stack
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273 (define_insn "movsi_pop"
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274 [(set (match_operand:SI 0 "register_operand" "=r")
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275 (mem:SI (post_inc:SI (reg:SI SP_REG))))]
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276 ""
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277 "pop.l %0")
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278
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279 (define_expand "movsi"
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280 [(set (match_operand:SI 0 "general_operand" "")
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281 (match_operand:SI 1 "general_operand" ""))]
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282 ""
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283 {
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284 /* If this is a store, force the value into a register. */
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285 if (!(reload_in_progress || reload_completed))
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286 {
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287 if (MEM_P (operands[0]))
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288 {
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289 operands[1] = force_reg (SImode, operands[1]);
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290 if (MEM_P (XEXP (operands[0], 0)))
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291 operands[0] = gen_rtx_MEM (SImode, force_reg (SImode, XEXP (operands[0], 0)));
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292 }
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293 else
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294 {
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295 if (MEM_P (operands[1]) && MEM_P (XEXP (operands[1], 0)))
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296 operands[1] = gen_rtx_MEM (SImode, force_reg (SImode, XEXP (operands[1], 0)));
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297 }
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298 /*
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299 if (MEM_P (operands[0])) {
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300 rtx o = XEXP (operands[0], 0);
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301 if (!REG_P(o) &&
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302 !CONST_INT_P(o) &&
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303 GET_CODE(o) != SYMBOL_REF &&
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304 GET_CODE(o) != LABEL_REF) {
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305 operands[0] = gen_rtx_MEM (SImode, force_reg (SImode, XEXP (operands[0], 0)));
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306 }
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307 }
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308 */
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309 }
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310 })
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311
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312 (define_insn "*rtestsi"
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313 [(set (reg:SI CC_REG)
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314 (match_operand:SI 0 "register_operand" "r"))]
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315 ""
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316 "cmp.l %0,0"
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317 )
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318
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319 (define_insn "*rtestqi"
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320 [(set (reg:QI CC_REG)
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321 (match_operand:QI 0 "register_operand" "r"))]
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322 ""
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323 "cmp.b %0,0"
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324 )
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325
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326 (define_insn "*movsi"
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327 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,BW,r,r,r,r,A,r,r")
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328 (match_operand:SI 1 "ft32_general_movsrc_operand" "r,r,BW,A,S,i,r,e,f"))]
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329 "register_operand (operands[0], SImode) || register_operand (operands[1], SImode)"
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330 "@
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331 move.l %0,%1
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332 sti.l %0,%1
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333 ldi.l %0,%1
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334 lda.l %0,%1
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335 ldk.l %0,%1
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336 *return ft32_load_immediate(operands[0], INTVAL(operands[1]));
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337 sta.l %0,%1
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338 lpm.l %0,%1
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339 lpmi.l %0,%1"
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340 )
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341
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342 (define_expand "movqi"
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343 [(set (match_operand:QI 0 "general_operand" "")
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344 (match_operand:QI 1 "general_operand" ""))]
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345 ""
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346 {
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347 /* If this is a store, force the value into a register. */
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348 if (!(reload_in_progress || reload_completed))
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349 {
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350 if (MEM_P (operands[0]))
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351 {
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352 operands[1] = force_reg (QImode, operands[1]);
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353 if (MEM_P (XEXP (operands[0], 0)))
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354 operands[0] = gen_rtx_MEM (QImode, force_reg (SImode, XEXP (operands[0], 0)));
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355 }
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356 else
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357 {
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358 if (MEM_P (operands[1]) && MEM_P (XEXP (operands[1], 0)))
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359 operands[1] = gen_rtx_MEM (QImode, force_reg (SImode, XEXP (operands[1], 0)));
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360 }
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361 if (MEM_P (operands[0]) && !REG_P(XEXP (operands[0], 0)))
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362 {
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363 operands[0] = gen_rtx_MEM (QImode, force_reg (SImode, XEXP (operands[0], 0)));
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364 }
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365 }
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366 })
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367
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368 (define_insn "zero_extendqisi2"
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369 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r")
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370 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "BW,r,f")))]
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371 ""
|
|
|
372 "@
|
|
|
373 ldi.b %0,%1
|
|
|
374 and.l %0,%1,255
|
|
|
375 lpmi.b %0,%1"
|
|
|
376 )
|
|
|
377
|
|
|
378 (define_insn "extendqisi2"
|
|
|
379 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
|
|
|
380 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r")))]
|
|
|
381 ""
|
|
|
382 "bexts.l %0,%1,(8<<5)|0"
|
|
|
383 )
|
|
|
384
|
|
|
385 (define_insn "zero_extendhisi2"
|
|
|
386 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r")
|
|
|
387 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "BW,r,f")))]
|
|
|
388 ""
|
|
|
389 "@
|
|
|
390 ldi.s %0,%1
|
|
|
391 bextu.l %0,%1,(0<<5)|0
|
|
|
392 lpmi.s %0,%1"
|
|
|
393 )
|
|
|
394
|
|
|
395 (define_insn "extendhisi2"
|
|
|
396 [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
|
|
|
397 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r")))]
|
|
|
398 ""
|
|
|
399 "bexts.l %0,%1,(0<<5)|0"
|
|
|
400 )
|
|
|
401
|
|
|
402 (define_insn "*movqi"
|
|
|
403 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,BW,r,r,A,r,r,r")
|
|
|
404 (match_operand:QI 1 "ft32_general_movsrc_operand" "r,r,BW,A,r,I,e,f"))]
|
|
|
405 "register_operand (operands[0], QImode)
|
|
|
406 || register_operand (operands[1], QImode)"
|
|
|
407 "@
|
|
|
408 move.b %0,%1
|
|
|
409 sti.b %0,%1
|
|
|
410 ldi.b %0,%1
|
|
|
411 lda.b %0,%1
|
|
|
412 sta.b %0,%1
|
|
|
413 ldk.b %0,%1
|
|
|
414 lpm.b %0,%1
|
|
|
415 lpmi.b %0,%1"
|
|
|
416 )
|
|
|
417
|
|
|
418 (define_expand "movhi"
|
|
|
419 [(set (match_operand:HI 0 "general_operand" "")
|
|
|
420 (match_operand:HI 1 "general_operand" ""))]
|
|
|
421 ""
|
|
|
422 {
|
|
|
423 /* If this is a store, force the value into a register. */
|
|
|
424 if (!(reload_in_progress || reload_completed))
|
|
|
425 {
|
|
|
426 if (MEM_P (operands[0]))
|
|
|
427 {
|
|
|
428 operands[1] = force_reg (HImode, operands[1]);
|
|
|
429 if (MEM_P (XEXP (operands[0], 0)))
|
|
|
430 operands[0] = gen_rtx_MEM (HImode, force_reg (SImode, XEXP (operands[0], 0)));
|
|
|
431 }
|
|
|
432 else
|
|
|
433 {
|
|
|
434 if (MEM_P (operands[1]) && MEM_P (XEXP (operands[1], 0)))
|
|
|
435 operands[1] = gen_rtx_MEM (HImode, force_reg (SImode, XEXP (operands[1], 0)));
|
|
|
436 }
|
|
|
437 if (MEM_P (operands[0]))
|
|
|
438 {
|
|
|
439 rtx o = XEXP (operands[0], 0);
|
|
|
440 if (!REG_P(o) &&
|
|
|
441 !CONST_INT_P(o) &&
|
|
|
442 GET_CODE(o) != SYMBOL_REF &&
|
|
|
443 GET_CODE(o) != LABEL_REF) {
|
|
|
444 operands[0] = gen_rtx_MEM (HImode, force_reg (SImode, XEXP (operands[0], 0)));
|
|
|
445 }
|
|
|
446 }
|
|
|
447 }
|
|
|
448 })
|
|
|
449
|
|
|
450 (define_insn "*movhi"
|
|
|
451 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,BW,r,r,A,r,r,r")
|
|
|
452 (match_operand:HI 1 "ft32_general_movsrc_operand" "r,r,BW,A,r,I,e,f"))]
|
|
|
453 "(register_operand (operands[0], HImode)
|
|
|
454 || register_operand (operands[1], HImode))"
|
|
|
455 "@
|
|
|
456 move.s %0,%1
|
|
|
457 sti.s %0,%1
|
|
|
458 ldi.s %0,%1
|
|
|
459 lda.s %0,%1
|
|
|
460 sta.s %0,%1
|
|
|
461 ldk.s %0,%1
|
|
|
462 lpm.s %0,%1
|
|
|
463 lpmi.s %0,%1"
|
|
|
464 )
|
|
|
465
|
|
|
466 (define_expand "movsf"
|
|
|
467 [(set (match_operand:SF 0 "general_operand" "")
|
|
|
468 (match_operand:SF 1 "general_operand" ""))]
|
|
|
469 ""
|
|
|
470 {
|
|
|
471 /* If this is a store, force the value into a register. */
|
|
|
472 if (MEM_P (operands[0]))
|
|
|
473 operands[1] = force_reg (SFmode, operands[1]);
|
|
|
474 if (CONST_DOUBLE_P(operands[1]))
|
|
|
475 operands[1] = force_const_mem(SFmode, operands[1]);
|
|
|
476 })
|
|
|
477
|
|
|
478 (define_insn "*movsf"
|
|
|
479 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,BW,r,r,A,r,r")
|
|
|
480 (match_operand:SF 1 "ft32_general_movsrc_operand" "r,r,BW,A,r,I,f"))]
|
|
|
481 "(register_operand (operands[0], SFmode)
|
|
|
482 || register_operand (operands[1], SFmode))"
|
|
|
483 "@
|
|
|
484 move.l %0,%1
|
|
|
485 sti.l %0,%1
|
|
|
486 ldi.l %0,%1
|
|
|
487 lda.l %0,%1
|
|
|
488 sta.l %0,%1
|
|
|
489 ldk.l %0,%1
|
|
|
490 lpmi.l %0,%1"
|
|
|
491 )
|
|
|
492
|
|
|
493 ;; -------------------------------------------------------------------------
|
|
|
494 ;; Compare instructions
|
|
|
495 ;; -------------------------------------------------------------------------
|
|
|
496
|
|
|
497 (define_expand "cbranchsi4"
|
|
|
498 [(set (reg:CC CC_REG)
|
|
|
499 (compare:CC
|
|
|
500 (match_operand:SI 1 "register_operand" "")
|
|
|
501 (match_operand:SI 2 "ft32_rimm_operand" "")))
|
|
|
502 (set (pc)
|
|
|
503 (if_then_else (match_operator 0 "comparison_operator"
|
|
|
504 [(reg:CC CC_REG) (const_int 0)])
|
|
|
505 (label_ref (match_operand 3 "" ""))
|
|
|
506 (pc)))]
|
|
|
507 ""
|
|
|
508 "")
|
|
|
509
|
|
|
510 (define_insn "cmpsi"
|
|
|
511 [(set (reg:CC CC_REG)
|
|
|
512 (compare:CC
|
|
|
513 (match_operand:SI 0 "register_operand" "r,r")
|
|
|
514 (match_operand:SI 1 "ft32_rimm_operand" "r,KA")))]
|
|
|
515 ""
|
|
|
516 "cmp.l %0,%1")
|
|
|
517
|
|
|
518 (define_insn ""
|
|
|
519 [(set (pc)
|
|
|
520 (if_then_else
|
|
|
521 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
|
|
|
522 (const_int 1)
|
|
|
523 (match_operand:SI 1 "const_int_operand" "i"))
|
|
|
524 (const_int 0))
|
|
|
525 (label_ref (match_operand 2 "" ""))
|
|
|
526 (pc)))
|
|
|
527 (clobber (reg:CC CC_REG))]
|
|
|
528 ""
|
|
|
529 "btst.l %0,(1<<5)|%1\;jmpc nz,%l2")
|
|
|
530
|
|
|
531 (define_insn ""
|
|
|
532 [(set (pc)
|
|
|
533 (if_then_else
|
|
|
534 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
|
|
|
535 (const_int 1)
|
|
|
536 (match_operand:SI 1 "const_int_operand" "i"))
|
|
|
537 (const_int 0))
|
|
|
538 (label_ref (match_operand 2 "" ""))
|
|
|
539 (pc)))
|
|
|
540 (clobber (reg:CC CC_REG))]
|
|
|
541 ""
|
|
|
542 "btst.l %0,(1<<5)|%1\;jmpc z,%l2")
|
|
|
543
|
|
|
544 (define_expand "cbranchqi4"
|
|
|
545 [(set (reg:CC CC_REG)
|
|
|
546 (compare:CC
|
|
|
547 (match_operand:QI 1 "register_operand" "")
|
|
|
548 (match_operand:QI 2 "ft32_rimm_operand" "")))
|
|
|
549 (set (pc)
|
|
|
550 (if_then_else (match_operator 0 "comparison_operator"
|
|
|
551 [(reg:CC CC_REG) (const_int 0)])
|
|
|
552 (label_ref (match_operand 3 "" ""))
|
|
|
553 (pc)))]
|
|
|
554 ""
|
|
|
555 "")
|
|
|
556
|
|
|
557 (define_insn "*cmpqi"
|
|
|
558 [(set (reg:CC CC_REG)
|
|
|
559 (compare:CC
|
|
|
560 (match_operand:QI 0 "register_operand" "r,r")
|
|
|
561 (match_operand:QI 1 "ft32_rimm_operand" "r,KA")))]
|
|
|
562 ""
|
|
|
563 "cmp.b %0,%1")
|
|
|
564
|
|
|
565 ;; -------------------------------------------------------------------------
|
|
|
566 ;; Branch instructions
|
|
|
567 ;; -------------------------------------------------------------------------
|
|
|
568
|
|
|
569 (define_code_iterator cond [ne eq lt ltu gt gtu ge le geu leu])
|
|
|
570 (define_code_attr CC [(ne "nz") (eq "z") (lt "lt") (ltu "b")
|
|
|
571 (gt "gt") (gtu "a") (ge "gte") (le "lte")
|
|
|
572 (geu "ae") (leu "be") ])
|
|
|
573 (define_code_attr rCC [(ne "z") (eq "nz") (lt "gte") (ltu "ae")
|
|
|
574 (gt "lte") (gtu "be") (ge "lt") (le "gt")
|
|
|
575 (geu "b") (leu "a") ])
|
|
|
576
|
|
|
577 (define_insn "*b<cond:code>"
|
|
|
578 [(set (pc)
|
|
|
579 (if_then_else (cond (reg:CC CC_REG)
|
|
|
580 (const_int 0))
|
|
|
581 (label_ref (match_operand 0 "" ""))
|
|
|
582 (pc)))]
|
|
|
583 ""
|
|
|
584 {
|
|
|
585 return "jmpc <CC>,%l0";
|
|
|
586 }
|
|
|
587 )
|
|
|
588
|
|
|
589 (define_expand "cstoresi4"
|
|
|
590 [(set (reg:CC CC_REG)
|
|
|
591 (compare:CC (match_operand:SI 2 "register_operand" "r,r")
|
|
|
592 (match_operand:SI 3 "ft32_rimm_operand" "r,KA")))
|
|
|
593 (set (match_operand:SI 0 "register_operand")
|
|
|
594 (match_operator:SI 1 "ordered_comparison_operator"
|
|
|
595 [(reg:CC CC_REG) (const_int 0)]))]
|
|
|
596 ""
|
|
|
597 {
|
|
|
598 rtx test;
|
|
|
599
|
|
|
600 switch (GET_CODE (operands[1])) {
|
|
|
601 case NE:
|
|
|
602 case GEU:
|
|
|
603 case LT:
|
|
|
604 case LE:
|
|
|
605 case LEU:
|
|
|
606 test = gen_rtx_fmt_ee (reverse_condition (GET_CODE (operands[1])),
|
|
|
607 SImode, operands[2], operands[3]);
|
|
|
608 emit_insn(gen_cstoresi4(operands[0], test, operands[2], operands[3]));
|
|
|
609 emit_insn(gen_xorsi3(operands[0], operands[0], gen_int_mode(1, SImode)));
|
|
|
610 DONE;
|
|
|
611 default:
|
|
|
612 ;
|
|
|
613 }
|
|
|
614 })
|
|
|
615
|
|
|
616 (define_insn "*seq"
|
|
|
617 [(set (match_operand:SI 0 "register_operand" "=r")
|
|
|
618 (eq:SI (reg CC_REG) (const_int 0)))]
|
|
|
619 ""
|
|
|
620 "bextu.l %0,$cc,32|0"
|
|
|
621 )
|
|
|
622
|
|
|
623 (define_insn "*sltu"
|
|
|
624 [(set (match_operand:SI 0 "register_operand" "=r")
|
|
|
625 (ltu:SI (reg CC_REG) (const_int 0)))]
|
|
|
626 ""
|
|
|
627 "bextu.l %0,$cc,32|1"
|
|
|
628 )
|
|
|
629
|
|
|
630 (define_insn "*sge"
|
|
|
631 [(set (match_operand:SI 0 "register_operand" "=r")
|
|
|
632 (ge:SI (reg CC_REG) (const_int 0)))]
|
|
|
633 ""
|
|
|
634 "bextu.l %0,$cc,32|4"
|
|
|
635 )
|
|
|
636
|
|
|
637 (define_insn "*sgt"
|
|
|
638 [(set (match_operand:SI 0 "register_operand" "=r")
|
|
|
639 (gt:SI (reg CC_REG) (const_int 0)))]
|
|
|
640 ""
|
|
|
641 "bextu.l %0,$cc,32|5"
|
|
|
642 )
|
|
|
643
|
|
|
644 (define_insn "*sgtu"
|
|
|
645 [(set (match_operand:SI 0 "register_operand" "=r")
|
|
|
646 (gtu:SI (reg CC_REG) (const_int 0)))]
|
|
|
647 ""
|
|
|
648 "bextu.l %0,$cc,32|6"
|
|
|
649 )
|
|
|
650
|
|
|
651 ;; -------------------------------------------------------------------------
|
|
|
652 ;; Call and Jump instructions
|
|
|
653 ;; -------------------------------------------------------------------------
|
|
|
654
|
|
|
655 (define_expand "call"
|
|
|
656 [(call (match_operand:QI 0 "memory_operand" "")
|
|
|
657 (match_operand 1 "general_operand" ""))]
|
|
|
658 ""
|
|
|
659 {
|
|
|
660 gcc_assert (MEM_P (operands[0]));
|
|
|
661 })
|
|
|
662
|
|
|
663 (define_insn "*call"
|
|
|
664 [(call (mem:QI (match_operand:SI
|
|
|
665 0 "nonmemory_operand" "i,r"))
|
|
|
666 (match_operand 1 "" ""))]
|
|
|
667 ""
|
|
|
668 "@
|
|
|
669 call %0
|
|
|
670 calli %0"
|
|
|
671 )
|
|
|
672
|
|
|
673 (define_expand "call_value"
|
|
|
674 [(set (match_operand 0 "" "")
|
|
|
675 (call (match_operand:QI 1 "memory_operand" "")
|
|
|
676 (match_operand 2 "" "")))]
|
|
|
677 ""
|
|
|
678 {
|
|
|
679 gcc_assert (MEM_P (operands[1]));
|
|
|
680 })
|
|
|
681
|
|
|
682 (define_insn "*call_value"
|
|
|
683 [(set (match_operand 0 "register_operand" "=r")
|
|
|
684 (call (mem:QI (match_operand:SI
|
|
|
685 1 "immediate_operand" "i"))
|
|
|
686 (match_operand 2 "" "")))]
|
|
|
687 ""
|
|
|
688 "call %1"
|
|
|
689 )
|
|
|
690
|
|
|
691 (define_insn "*call_value_indirect"
|
|
|
692 [(set (match_operand 0 "register_operand" "=r")
|
|
|
693 (call (mem:QI (match_operand:SI
|
|
|
694 1 "register_operand" "r"))
|
|
|
695 (match_operand 2 "" "")))]
|
|
|
696 ""
|
|
|
697 "calli %1"
|
|
|
698 )
|
|
|
699
|
|
|
700 (define_insn "indirect_jump"
|
|
|
701 [(set (pc) (match_operand:SI 0 "nonimmediate_operand" "r"))]
|
|
|
702 ""
|
|
|
703 "jmpi %0")
|
|
|
704
|
|
|
705 (define_insn "jump"
|
|
|
706 [(set (pc)
|
|
|
707 (label_ref (match_operand 0 "" "")))]
|
|
|
708 ""
|
|
|
709 "jmp %l0"
|
|
|
710 )
|
|
|
711
|
|
|
712 (define_insn "call_prolog"
|
|
|
713 [(unspec:SI [(match_operand 0 "" "")]
|
|
|
714 UNSPEC_JMP_PROLOG)]
|
|
|
715 ""
|
|
|
716 "call __prolog_%0"
|
|
|
717 )
|
|
|
718
|
|
|
719 (define_insn "jump_epilog"
|
|
|
720 [(unspec:SI [(match_operand 0 "" "")]
|
|
|
721 UNSPEC_JMP_EPILOG)]
|
|
|
722 ""
|
|
|
723 "jmp __epilog_%0"
|
|
|
724 )
|
|
|
725
|
|
|
726 (define_insn "jump_epilog24"
|
|
|
727 [(unspec:SI [(match_operand 0 "" "")]
|
|
|
728 UNSPEC_JMP_EPILOG24)]
|
|
|
729 ""
|
|
|
730 "jmp __epilog24_%0"
|
|
|
731 )
|
|
|
732
|
|
|
733
|
|
|
734 ;; Subroutines of "casesi".
|
|
|
735 ;; operand 0 is index
|
|
|
736 ;; operand 1 is the minimum bound
|
|
|
737 ;; operand 2 is the maximum bound - minimum bound + 1
|
|
|
738 ;; operand 3 is CODE_LABEL for the table;
|
|
|
739 ;; operand 4 is the CODE_LABEL to go to if index out of range.
|
|
|
740
|
|
|
741 (define_expand "casesi"
|
|
|
742 [(match_operand:SI 0 "general_operand" "")
|
|
|
743 (match_operand:SI 1 "const_int_operand" "")
|
|
|
744 (match_operand:SI 2 "const_int_operand" "")
|
|
|
745 (match_operand 3 "" "")
|
|
|
746 (match_operand 4 "" "")]
|
|
|
747 ""
|
|
|
748 "
|
|
|
749 {
|
|
|
750 if (GET_CODE (operands[0]) != REG)
|
|
|
751 operands[0] = force_reg (SImode, operands[0]);
|
|
|
752
|
|
|
753 if (operands[1] != const0_rtx)
|
|
|
754 {
|
|
|
755 rtx index = gen_reg_rtx (SImode);
|
|
|
756 rtx offset = gen_reg_rtx (SImode);
|
|
|
757
|
|
|
758 emit_insn (gen_movsi (offset, operands[1]));
|
|
|
759 emit_insn (gen_subsi3 (index, operands[0], offset));
|
|
|
760 operands[0] = index;
|
|
|
761 }
|
|
|
762
|
|
|
763 {
|
|
|
764 rtx test = gen_rtx_GTU (VOIDmode, operands[0], operands[2]);
|
|
|
765 emit_jump_insn (gen_cbranchsi4 (test, operands[0], operands[2], operands[4]));
|
|
|
766 }
|
|
|
767
|
|
|
768 emit_jump_insn (gen_casesi0 (operands[0], operands[3]));
|
|
|
769 DONE;
|
|
|
770 }")
|
|
|
771
|
|
|
772 (define_insn "casesi0"
|
|
|
773 [(set (pc) (mem:SI (plus:SI
|
|
|
774 (mult:SI (match_operand:SI 0 "register_operand" "r")
|
|
|
775 (const_int 4))
|
|
|
776 (label_ref (match_operand 1 "" "")))))
|
|
|
777 (clobber (match_scratch:SI 2 "=&r"))
|
|
|
778 ]
|
|
|
779 ""
|
|
131
|
780 {
|
|
|
781 if (TARGET_NOPM)
|
|
|
782 return \"ldk.l\t$cc,%l1\;ashl.l\t%2,%0,2\;add.l\t%2,%2,$cc\;ldi.l\t%2,%2,0\;jmpi\t%2\";
|
|
|
783 else
|
|
|
784 return \"ldk.l\t$cc,%l1\;ashl.l\t%2,%0,2\;add.l\t%2,%2,$cc\;lpmi.l\t%2,%2,0\;jmpi\t%2\";
|
|
|
785 })
|
|
111
|
786
|
|
|
787 ;; -------------------------------------------------------------------------
|
|
|
788 ;; Atomic exchange instruction
|
|
|
789 ;; -------------------------------------------------------------------------
|
|
|
790
|
|
|
791 (define_insn "atomic_exchangesi"
|
|
|
792 [(set (match_operand:SI 0 "register_operand" "=&r,r") ;; output
|
|
|
793 (match_operand:SI 1 "memory_operand" "+BW,A")) ;; memory
|
|
|
794 (set (match_dup 1)
|
|
|
795 (unspec:SI
|
|
|
796 [(match_operand:SI 2 "register_operand" "0,0") ;; input
|
|
|
797 (match_operand:SI 3 "const_int_operand")] ;; model
|
|
|
798 UNSPEC_XCHG))]
|
|
|
799 ""
|
|
|
800 "@
|
|
|
801 exi.l %0,%1
|
|
|
802 exa.l %0,%1")
|
|
|
803
|
|
|
804 (define_insn "atomic_exchangehi"
|
|
|
805 [(set (match_operand:HI 0 "register_operand" "=&r,r") ;; output
|
|
|
806 (match_operand:HI 1 "memory_operand" "+BW,A")) ;; memory
|
|
|
807 (set (match_dup 1)
|
|
|
808 (unspec:HI
|
|
|
809 [(match_operand:HI 2 "register_operand" "0,0") ;; input
|
|
|
810 (match_operand:HI 3 "const_int_operand")] ;; model
|
|
|
811 UNSPEC_XCHG))]
|
|
|
812 ""
|
|
|
813 "@
|
|
|
814 exi.s %0,%1
|
|
|
815 exa.s %0,%1")
|
|
|
816
|
|
|
817 (define_insn "atomic_exchangeqi"
|
|
|
818 [(set (match_operand:QI 0 "register_operand" "=&r,r") ;; output
|
|
|
819 (match_operand:QI 1 "memory_operand" "+BW,A")) ;; memory
|
|
|
820 (set (match_dup 1)
|
|
|
821 (unspec:QI
|
|
|
822 [(match_operand:QI 2 "register_operand" "0,0") ;; input
|
|
|
823 (match_operand:QI 3 "const_int_operand")] ;; model
|
|
|
824 UNSPEC_XCHG))]
|
|
|
825 ""
|
|
|
826 "@
|
|
|
827 exi.b %0,%1
|
|
|
828 exa.b %0,%1")
|
|
|
829
|
|
|
830 ;; -------------------------------------------------------------------------
|
|
|
831 ;; String instructions
|
|
|
832 ;; -------------------------------------------------------------------------
|
|
|
833
|
|
|
834 (define_insn "cmpstrsi"
|
|
|
835 [(set (match_operand:SI 0 "register_operand" "=r,r")
|
|
|
836 (compare:SI (match_operand:BLK 1 "memory_operand" "W,BW")
|
|
|
837 (match_operand:BLK 2 "memory_operand" "W,BW")))
|
|
|
838 (clobber (match_operand:SI 3))
|
|
|
839 ]
|
|
|
840 ""
|
|
|
841 "strcmp.%d3 %0,%b1,%b2"
|
|
|
842 )
|
|
|
843
|
|
|
844 (define_insn "movstr"
|
|
|
845 [(set (match_operand:BLK 1 "memory_operand" "=W")
|
|
|
846 (match_operand:BLK 2 "memory_operand" "W"))
|
|
|
847 (use (match_operand:SI 0))
|
|
|
848 (clobber (match_dup 0))
|
|
|
849 ]
|
|
|
850 "0"
|
|
|
851 "stpcpy %b1,%b2 # %0 %b1 %b2"
|
|
|
852 )
|
|
|
853
|
|
|
854 (define_insn "movmemsi"
|
|
|
855 [(set (match_operand:BLK 0 "memory_operand" "=W,BW")
|
|
|
856 (match_operand:BLK 1 "memory_operand" "W,BW"))
|
|
|
857 (use (match_operand:SI 2 "ft32_imm_operand" "KA,KA"))
|
|
|
858 (use (match_operand:SI 3))
|
|
|
859 ]
|
|
|
860 ""
|
|
|
861 "memcpy.%d3 %b0,%b1,%2 "
|
|
|
862 )
|
|
|
863
|
|
|
864 (define_insn "setmemsi"
|
|
|
865 [(set (match_operand:BLK 0 "memory_operand" "=BW") (unspec:BLK [
|
|
|
866 (use (match_operand:QI 2 "register_operand" "r"))
|
|
|
867 (use (match_operand:SI 1 "ft32_imm_operand" "KA"))
|
|
|
868 ] UNSPEC_SETMEM))
|
|
|
869 (use (match_operand:SI 3))
|
|
|
870 ]
|
|
|
871 ""
|
|
|
872 "memset.%d3 %b0,%2,%1"
|
|
|
873 )
|
|
|
874
|
|
|
875 (define_insn "strlensi"
|
|
|
876 [(set (match_operand:SI 0 "register_operand" "=r")
|
|
|
877 (unspec:SI [(match_operand:BLK 1 "memory_operand" "W")
|
|
|
878 (match_operand:QI 2 "const_int_operand" "")
|
|
|
879 (match_operand:SI 3 "ft32_rimm_operand" "")]
|
|
|
880 UNSPEC_STRLEN))]
|
|
|
881 ""
|
|
|
882 "strlen.%d3 %0,%b1 # %2 %3"
|
|
|
883 )
|
|
|
884
|
|
|
885 ;; -------------------------------------------------------------------------
|
|
|
886 ;; Prologue & Epilogue
|
|
|
887 ;; -------------------------------------------------------------------------
|
|
|
888
|
|
|
889 (define_expand "prologue"
|
|
|
890 [(clobber (const_int 0))]
|
|
|
891 ""
|
|
|
892 {
|
|
|
893 extern void ft32_expand_prologue();
|
|
|
894 ft32_expand_prologue ();
|
|
|
895 DONE;
|
|
|
896 })
|
|
|
897
|
|
|
898
|
|
|
899 (define_expand "epilogue"
|
|
|
900 [(return)]
|
|
|
901 ""
|
|
|
902 {
|
|
|
903 extern void ft32_expand_epilogue();
|
|
|
904 ft32_expand_epilogue ();
|
|
|
905 DONE;
|
|
|
906 })
|
|
|
907
|
|
|
908 (define_insn "link"
|
|
|
909 [
|
|
|
910 ;; (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
|
|
|
911 ;; (reg:SI FP_REG))
|
|
|
912 (set (match_operand:SI 0)
|
|
|
913 (reg:SI SP_REG))
|
|
|
914 (set (reg:SI SP_REG)
|
|
|
915 (plus:SI (reg:SI SP_REG)
|
|
|
916 (match_operand:SI 1 "general_operand" "L")))]
|
|
|
917 ""
|
|
|
918 "link %0,%m1"
|
|
|
919 )
|
|
|
920
|
|
|
921 (define_insn "unlink"
|
|
|
922 [(set (reg:SI FP_REG)
|
|
|
923 (mem:SI (reg:SI FP_REG)))
|
|
|
924 (set (reg:SI SP_REG)
|
|
|
925 (plus:SI (reg:SI FP_REG)
|
|
|
926 (const_int 4)))]
|
|
|
927 ""
|
|
|
928 "unlink $r29"
|
|
|
929 )
|
|
|
930
|
|
|
931 (define_insn "returner"
|
|
|
932 [(return)]
|
|
|
933 "reload_completed"
|
|
|
934 "return")
|
|
|
935
|
|
|
936 (define_insn "pretend_returner"
|
|
|
937 [(set (reg:SI SP_REG)
|
|
|
938 (plus:SI (reg:SI SP_REG)
|
|
|
939 (match_operand:SI 0)))
|
|
|
940 (return)]
|
|
|
941 "reload_completed"
|
|
|
942 "pop.l $cc\;add.l $sp,$sp,%0\;jmpi $cc")
|
|
|
943
|
|
|
944 (define_insn "returner24"
|
|
|
945 [
|
|
|
946 (set (reg:SI SP_REG)
|
|
|
947 (plus:SI
|
|
|
948 (reg:SI SP_REG)
|
|
|
949 (const_int 24)))
|
|
|
950 (return)]
|
|
|
951 ""
|
|
|
952 "jmp __epilog24")
|
