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1 ;; Copyright (C) 2013-2018 Free Software Foundation, Inc.
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2 ;;
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3 ;; micromips.md Machine Description for the microMIPS instruction set
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4 ;; This file is part of GCC.
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5
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6 ;; GCC is free software; you can redistribute it and/or modify it
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7 ;; under the terms of the GNU General Public License as published
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8 ;; by the Free Software Foundation; either version 3, or (at your
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9 ;; option) any later version.
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10
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11 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
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12 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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13 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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14 ;; License for more details.
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15
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16 ;; You should have received a copy of the GNU General Public License
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17 ;; along with GCC; see the file COPYING3. If not see
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18 ;; <http://www.gnu.org/licenses/>.
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19
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20 (define_insn "*store_word_multiple"
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21 [(match_parallel 0 ""
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22 [(set (match_operand:SI 1 "memory_operand")
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23 (match_operand:SI 2 "register_operand"))])]
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24 "TARGET_MICROMIPS
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25 && umips_save_restore_pattern_p (true, operands[0])"
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26 { return umips_output_save_restore (true, operands[0]); }
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27 [(set_attr "type" "multimem")
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28 (set_attr "mode" "SI")
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29 (set_attr "can_delay" "no")])
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30
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31 (define_insn "*load_word_multiple"
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32 [(match_parallel 0 ""
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33 [(set (match_operand:SI 1 "register_operand")
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34 (match_operand:SI 2 "memory_operand"))])]
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35 "TARGET_MICROMIPS
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36 && umips_save_restore_pattern_p (false, operands[0])"
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37 { return umips_output_save_restore (false, operands[0]); }
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38 [(set_attr "type" "multimem")
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39 (set_attr "mode" "SI")
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40 (set_attr "can_delay" "no")])
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41
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42 ;; For LWP.
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43 (define_peephole2
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44 [(set (match_operand:SI 0 "d_operand" "")
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45 (match_operand:SI 1 "non_volatile_mem_operand" ""))
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46 (set (match_operand:SI 2 "d_operand" "")
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47 (match_operand:SI 3 "non_volatile_mem_operand" ""))]
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48 "TARGET_MICROMIPS
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49 && umips_load_store_pair_p (true, operands)"
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50 [(parallel [(set (match_dup 0) (match_dup 1))
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51 (set (match_dup 2) (match_dup 3))])])
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52
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53 ;; The behavior of the LWP insn is undefined if placed in a delay slot.
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54 (define_insn "*lwp"
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55 [(parallel [(set (match_operand:SI 0 "d_operand")
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56 (match_operand:SI 1 "non_volatile_mem_operand"))
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57 (set (match_operand:SI 2 "d_operand")
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58 (match_operand:SI 3 "non_volatile_mem_operand"))])]
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59
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60 "TARGET_MICROMIPS
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61 && umips_load_store_pair_p (true, operands)"
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62 {
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63 umips_output_load_store_pair (true, operands);
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64 return "";
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65 }
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66 [(set_attr "type" "load")
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67 (set_attr "mode" "SI")
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68 (set_attr "can_delay" "no")])
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69
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70 ;; For SWP.
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71 (define_peephole2
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72 [(set (match_operand:SI 0 "non_volatile_mem_operand" "")
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73 (match_operand:SI 1 "d_operand" ""))
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74 (set (match_operand:SI 2 "non_volatile_mem_operand" "")
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75 (match_operand:SI 3 "d_operand" ""))]
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76 "TARGET_MICROMIPS
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77 && umips_load_store_pair_p (false, operands)"
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78 [(parallel [(set (match_dup 0) (match_dup 1))
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79 (set (match_dup 2) (match_dup 3))])])
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80
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81 ;; The behavior of the SWP insn is undefined if placed in a delay slot.
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82 (define_insn "*swp"
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83 [(set (match_operand:SI 0 "non_volatile_mem_operand")
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84 (match_operand:SI 1 "d_operand"))
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85 (set (match_operand:SI 2 "non_volatile_mem_operand")
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86 (match_operand:SI 3 "d_operand"))]
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87 "TARGET_MICROMIPS
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88 && umips_load_store_pair_p (false, operands)"
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89 {
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90 umips_output_load_store_pair (false, operands);
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91 return "";
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92 }
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93 [(set_attr "type" "store")
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94 (set_attr "mode" "SI")
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95 (set_attr "can_delay" "no")])
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96
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97 ;; For JRADDIUSP.
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98 (define_insn "jraddiusp"
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99 [(return)
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100 (use (reg:SI 31))
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101 (set (reg:SI 29)
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102 (plus:SI (reg:SI 29)
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103 (match_operand 0 "uw5_operand")))]
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104 "TARGET_MICROMIPS"
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105 "jraddiusp\t%0"
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106 [(set_attr "type" "trap")
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107 (set_attr "can_delay" "no")
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108 (set_attr "mode" "SI")])
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109
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110 ;; For MOVEP.
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111 (define_peephole2
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112 [(set (match_operand:MOVEP1 0 "register_operand" "")
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113 (match_operand:MOVEP1 1 "movep_src_operand" ""))
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114 (set (match_operand:MOVEP2 2 "register_operand" "")
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115 (match_operand:MOVEP2 3 "movep_src_operand" ""))]
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116 "TARGET_MICROMIPS
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117 && umips_movep_target_p (operands[0], operands[2])"
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118 [(parallel [(set (match_dup 0) (match_dup 1))
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119 (set (match_dup 2) (match_dup 3))])])
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120
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121 ;; The behavior of the MOVEP insn is undefined if placed in a delay slot.
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122 (define_insn "*movep<MOVEP1:mode><MOVEP2:mode>"
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123 [(set (match_operand:MOVEP1 0 "register_operand")
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124 (match_operand:MOVEP1 1 "movep_src_operand"))
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125 (set (match_operand:MOVEP2 2 "register_operand")
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126 (match_operand:MOVEP2 3 "movep_src_operand"))]
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127 "TARGET_MICROMIPS
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128 && umips_movep_target_p (operands[0], operands[2])"
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129 {
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130 if (REGNO (operands[0]) < REGNO (operands[2]))
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131 return "movep\t%0,%2,%z1,%z3";
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132 else
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133 return "movep\t%2,%0,%z3,%z1";
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134 }
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135 [(set_attr "type" "move")
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136 (set_attr "mode" "<MODE>")
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137 (set_attr "can_delay" "no")])
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