Mercurial > hg > CbC > CbC_gcc

annotate gcc/config/mips/mips.opt @ 131:84e7813d76e9

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gcc-8.2
author mir3636
date Thu, 25 Oct 2018 07:37:49 +0900
parents 04ced10e8804
children 1830386684a0
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kent <kent@cr.ie.u-ryukyu.ac.jp>
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1 ; Options for the MIPS port of the compiler
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2 ;
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84e7813d76e9 gcc-8.2
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3 ; Copyright (C) 2005-2018 Free Software Foundation, Inc.
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4 ;
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5 ; This file is part of GCC.
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6 ;
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7 ; GCC is free software; you can redistribute it and/or modify it under
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8 ; the terms of the GNU General Public License as published by the Free
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9 ; Software Foundation; either version 3, or (at your option) any later
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10 ; version.
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11 ;
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12 ; GCC is distributed in the hope that it will be useful, but WITHOUT
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13 ; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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14 ; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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15 ; License for more details.
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16 ;
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17 ; You should have received a copy of the GNU General Public License
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18 ; along with GCC; see the file COPYING3. If not see
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19 ; <http://www.gnu.org/licenses/>.
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20
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21 HeaderInclude
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22 config/mips/mips-opts.h
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23
67
f6334be47118 update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
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24 EB
f6334be47118 update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
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25 Driver
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26
f6334be47118 update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
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27 EL
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28 Driver
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29
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30 mabi=
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31 Target RejectNegative Joined Enum(mips_abi) Var(mips_abi) Init(MIPS_ABI_DEFAULT)
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32 -mabi=ABI Generate code that conforms to the given ABI.
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33
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34 Enum
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35 Name(mips_abi) Type(int)
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36 Known MIPS ABIs (for use with the -mabi= option):
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37
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38 EnumValue
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39 Enum(mips_abi) String(32) Value(ABI_32)
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40
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41 EnumValue
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42 Enum(mips_abi) String(o64) Value(ABI_O64)
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43
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44 EnumValue
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45 Enum(mips_abi) String(n32) Value(ABI_N32)
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46
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47 EnumValue
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48 Enum(mips_abi) String(64) Value(ABI_64)
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49
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50 EnumValue
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51 Enum(mips_abi) String(eabi) Value(ABI_EABI)
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52
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53 mabicalls
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54 Target Report Mask(ABICALLS)
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55 Generate code that can be used in SVR4-style dynamic objects.
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56
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57 mmad
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58 Target Report Var(TARGET_MAD)
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59 Use PMC-style 'mad' instructions.
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60
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61 mimadd
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62 Target Report Mask(IMADD)
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63 Use integer madd/msub instructions.
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65 march=
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66 Target RejectNegative Joined Var(mips_arch_option) ToLower Enum(mips_arch_opt_value)
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67 -march=ISA Generate code for the given ISA.
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68
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69 mbranch-cost=
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70 Target RejectNegative Joined UInteger Var(mips_branch_cost)
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71 -mbranch-cost=COST Set the cost of branches to roughly COST instructions.
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73 mbranch-likely
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74 Target Report Mask(BRANCHLIKELY)
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75 Use Branch Likely instructions, overriding the architecture default.
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76
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77 mflip-mips16
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78 Target Report Var(TARGET_FLIP_MIPS16)
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79 Switch on/off MIPS16 ASE on alternating functions for compiler testing.
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80
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81 mcheck-zero-division
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82 Target Report Mask(CHECK_ZERO_DIV)
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83 Trap on integer divide by zero.
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84
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85 mcode-readable=
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86 Target RejectNegative Joined Enum(mips_code_readable_setting) Var(mips_code_readable) Init(CODE_READABLE_YES)
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87 -mcode-readable=SETTING Specify when instructions are allowed to access code.
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88
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89 Enum
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90 Name(mips_code_readable_setting) Type(enum mips_code_readable_setting)
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91 Valid arguments to -mcode-readable=:
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92
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93 EnumValue
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94 Enum(mips_code_readable_setting) String(yes) Value(CODE_READABLE_YES)
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95
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96 EnumValue
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97 Enum(mips_code_readable_setting) String(pcrel) Value(CODE_READABLE_PCREL)
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98
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99 EnumValue
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100 Enum(mips_code_readable_setting) String(no) Value(CODE_READABLE_NO)
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101
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102 mdivide-breaks
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103 Target Report RejectNegative Mask(DIVIDE_BREAKS)
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104 Use branch-and-break sequences to check for integer divide by zero.
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105
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106 mdivide-traps
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107 Target Report RejectNegative InverseMask(DIVIDE_BREAKS, DIVIDE_TRAPS)
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108 Use trap instructions to check for integer divide by zero.
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109
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110 mdmx
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111 Target Report RejectNegative Var(TARGET_MDMX)
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112 Allow the use of MDMX instructions.
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113
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114 mdouble-float
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115 Target Report RejectNegative InverseMask(SINGLE_FLOAT, DOUBLE_FLOAT)
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116 Allow hardware floating-point instructions to cover both 32-bit and 64-bit operations.
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117
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118 mdsp
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119 Target Report Var(TARGET_DSP)
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120 Use MIPS-DSP instructions.
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121
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122 mdspr2
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123 Target Report Var(TARGET_DSPR2)
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124 Use MIPS-DSP REV 2 instructions.
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125
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126 mdebug
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127 Target Var(TARGET_DEBUG_MODE) Undocumented
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128
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129 mdebugd
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130 Target Var(TARGET_DEBUG_D_MODE) Undocumented
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131
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132 meb
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133 Target Report RejectNegative Mask(BIG_ENDIAN)
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134 Use big-endian byte order.
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135
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136 mel
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137 Target Report RejectNegative InverseMask(BIG_ENDIAN, LITTLE_ENDIAN)
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138 Use little-endian byte order.
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139
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140 membedded-data
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141 Target Report Var(TARGET_EMBEDDED_DATA)
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142 Use ROM instead of RAM.
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143
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144 meva
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145 Target Report Var(TARGET_EVA)
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146 Use Enhanced Virtual Addressing instructions.
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147
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148 mexplicit-relocs
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149 Target Report Mask(EXPLICIT_RELOCS)
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150 Use NewABI-style %reloc() assembly operators.
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151
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152 mextern-sdata
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153 Target Report Var(TARGET_EXTERN_SDATA) Init(1)
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154 Use -G for data that is not defined by the current object.
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155
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156 mfix-24k
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157 Target Report Var(TARGET_FIX_24K)
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158 Work around certain 24K errata.
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159
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160 mfix-r4000
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161 Target Report Mask(FIX_R4000)
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162 Work around certain R4000 errata.
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163
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164 mfix-r4400
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165 Target Report Mask(FIX_R4400)
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166 Work around certain R4400 errata.
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167
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168 mfix-rm7000
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169 Target Report Var(TARGET_FIX_RM7000)
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170 Work around certain RM7000 errata.
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171
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172 mfix-r10000
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173 Target Report Mask(FIX_R10000)
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174 Work around certain R10000 errata.
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175
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176 mfix-sb1
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177 Target Report Var(TARGET_FIX_SB1)
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178 Work around errata for early SB-1 revision 2 cores.
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179
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180 mfix-vr4120
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181 Target Report Var(TARGET_FIX_VR4120)
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182 Work around certain VR4120 errata.
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183
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184 mfix-vr4130
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185 Target Report Var(TARGET_FIX_VR4130)
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186 Work around VR4130 mflo/mfhi errata.
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187
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188 mfix4300
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189 Target Report Var(TARGET_4300_MUL_FIX)
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190 Work around an early 4300 hardware bug.
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191
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192 mfp-exceptions
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193 Target Report Var(TARGET_FP_EXCEPTIONS) Init(1)
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194 FP exceptions are enabled.
0
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parents:
diff changeset
195
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
196 mfp32
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
197 Target Report RejectNegative InverseMask(FLOAT64)
111
kono
parents: 67
diff changeset
198 Use 32-bit floating-point registers.
kono
parents: 67
diff changeset
199
kono
parents: 67
diff changeset
200 mfpxx
kono
parents: 67
diff changeset
201 Target Report RejectNegative Mask(FLOATXX)
kono
parents: 67
diff changeset
202 Conform to the o32 FPXX ABI.
0
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
203
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
204 mfp64
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
205 Target Report RejectNegative Mask(FLOAT64)
111
kono
parents: 67
diff changeset
206 Use 64-bit floating-point registers.
0
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
207
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
208 mflush-func=
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
209 Target RejectNegative Joined Var(mips_cache_flush_func) Init(CACHE_FLUSH_FUNC)
111
kono
parents: 67
diff changeset
210 -mflush-func=FUNC Use FUNC to flush the cache before calling stack trampolines.
kono
parents: 67
diff changeset
211
kono
parents: 67
diff changeset
212 mabs=
kono
parents: 67
diff changeset
213 Target RejectNegative Joined Enum(mips_ieee_754_value) Var(mips_abs) Init(MIPS_IEEE_754_DEFAULT)
kono
parents: 67
diff changeset
214 -mabs=MODE Select the IEEE 754 ABS/NEG instruction execution mode.
kono
parents: 67
diff changeset
215
kono
parents: 67
diff changeset
216 mnan=
kono
parents: 67
diff changeset
217 Target RejectNegative Joined Enum(mips_ieee_754_value) Var(mips_nan) Init(MIPS_IEEE_754_DEFAULT)
kono
parents: 67
diff changeset
218 -mnan=ENCODING Select the IEEE 754 NaN data encoding.
0
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parents:
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219
111
kono
parents: 67
diff changeset
220 Enum
kono
parents: 67
diff changeset
221 Name(mips_ieee_754_value) Type(int)
kono
parents: 67
diff changeset
222 Known MIPS IEEE 754 settings (for use with the -mabs= and -mnan= options):
kono
parents: 67
diff changeset
223
kono
parents: 67
diff changeset
224 EnumValue
kono
parents: 67
diff changeset
225 Enum(mips_ieee_754_value) String(2008) Value(MIPS_IEEE_754_2008)
kono
parents: 67
diff changeset
226
kono
parents: 67
diff changeset
227 EnumValue
kono
parents: 67
diff changeset
228 Enum(mips_ieee_754_value) String(legacy) Value(MIPS_IEEE_754_LEGACY)
0
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
229
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
230 mgp32
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
231 Target Report RejectNegative InverseMask(64BIT)
111
kono
parents: 67
diff changeset
232 Use 32-bit general registers.
0
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parents:
diff changeset
233
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
234 mgp64
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
235 Target Report RejectNegative Mask(64BIT)
111
kono
parents: 67
diff changeset
236 Use 64-bit general registers.
0
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parents:
diff changeset
237
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
238 mgpopt
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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239 Target Report Var(TARGET_GPOPT) Init(1)
111
kono
parents: 67
diff changeset
240 Use GP-relative addressing to access small data.
0
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
241
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
242 mplt
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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243 Target Report Var(TARGET_PLT)
111
kono
parents: 67
diff changeset
244 When generating -mabicalls code, allow executables to use PLTs and copy relocations.
0
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
245
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
246 mhard-float
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
247 Target Report RejectNegative InverseMask(SOFT_FLOAT_ABI, HARD_FLOAT_ABI)
111
kono
parents: 67
diff changeset
248 Allow the use of hardware floating-point ABI and instructions.
kono
parents: 67
diff changeset
249
kono
parents: 67
diff changeset
250 minterlink-compressed
kono
parents: 67
diff changeset
251 Target Report Var(TARGET_INTERLINK_COMPRESSED) Init(0)
kono
parents: 67
diff changeset
252 Generate code that is link-compatible with MIPS16 and microMIPS code.
0
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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253
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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254 minterlink-mips16
111
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parents: 67
diff changeset
255 Target Report Var(TARGET_INTERLINK_COMPRESSED) Init(0)
kono
parents: 67
diff changeset
256 An alias for minterlink-compressed provided for backward-compatibility.
0
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
257
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
258 mips
111
kono
parents: 67
diff changeset
259 Target RejectNegative Joined ToLower Enum(mips_mips_opt_value) Var(mips_isa_option)
kono
parents: 67
diff changeset
260 -mipsN Generate code for ISA level N.
0
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
261
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
262 mips16
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
263 Target Report RejectNegative Mask(MIPS16)
111
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parents: 67
diff changeset
264 Generate MIPS16 code.
0
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
265
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
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266 mips3d
111
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parents: 67
diff changeset
267 Target Report RejectNegative Var(TARGET_MIPS3D)
kono
parents: 67
diff changeset
268 Use MIPS-3D instructions.
0
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
269
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
270 mllsc
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
271 Target Report Mask(LLSC)
111
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parents: 67
diff changeset
272 Use ll, sc and sync instructions.
0
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
273
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
274 mlocal-sdata
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
275 Target Report Var(TARGET_LOCAL_SDATA) Init(1)
111
kono
parents: 67
diff changeset
276 Use -G for object-local data.
0
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
277
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
278 mlong-calls
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
279 Target Report Var(TARGET_LONG_CALLS)
111
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parents: 67
diff changeset
280 Use indirect calls.
0
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
281
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
282 mlong32
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
283 Target Report RejectNegative InverseMask(LONG64, LONG32)
111
kono
parents: 67
diff changeset
284 Use a 32-bit long type.
0
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
285
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
286 mlong64
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
287 Target Report RejectNegative Mask(LONG64)
111
kono
parents: 67
diff changeset
288 Use a 64-bit long type.
0
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parents:
diff changeset
289
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
290 mmcount-ra-address
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
291 Target Report Var(TARGET_MCOUNT_RA_ADDRESS)
111
kono
parents: 67
diff changeset
292 Pass the address of the ra save location to _mcount in $12.
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
293
0
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parents:
diff changeset
294 mmemcpy
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
295 Target Report Mask(MEMCPY)
111
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parents: 67
diff changeset
296 Don't optimize block moves.
0
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parents:
diff changeset
297
111
kono
parents: 67
diff changeset
298 mmicromips
kono
parents: 67
diff changeset
299 Target Report Mask(MICROMIPS)
kono
parents: 67
diff changeset
300 Use microMIPS instructions.
kono
parents: 67
diff changeset
301
kono
parents: 67
diff changeset
302 mmsa
kono
parents: 67
diff changeset
303 Target Report Var(TARGET_MSA)
kono
parents: 67
diff changeset
304 Use MIPS MSA Extension instructions.
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parents:
diff changeset
305
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
306 mmt
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
307 Target Report Var(TARGET_MT)
111
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diff changeset
308 Allow the use of MT instructions.
0
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parents:
diff changeset
309
63
b7f97abdc517 update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 55
diff changeset
310 mno-float
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 55
diff changeset
311 Target Report RejectNegative Var(TARGET_NO_FLOAT) Condition(TARGET_SUPPORTS_NO_FLOAT)
111
kono
parents: 67
diff changeset
312 Prevent the use of all floating-point operations.
kono
parents: 67
diff changeset
313
kono
parents: 67
diff changeset
314 mmcu
kono
parents: 67
diff changeset
315 Target Report Var(TARGET_MCU)
kono
parents: 67
diff changeset
316 Use MCU instructions.
63
b7f97abdc517 update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 55
diff changeset
317
0
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parents:
diff changeset
318 mno-flush-func
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
319 Target RejectNegative
111
kono
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diff changeset
320 Do not use a cache-flushing function before calling stack trampolines.
0
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parents:
diff changeset
321
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
322 mno-mdmx
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f6334be47118 update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents: 63
diff changeset
323 Target Report RejectNegative Var(TARGET_MDMX, 0)
111
kono
parents: 67
diff changeset
324 Do not use MDMX instructions.
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parents:
diff changeset
325
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
326 mno-mips16
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parents:
diff changeset
327 Target Report RejectNegative InverseMask(MIPS16)
111
kono
parents: 67
diff changeset
328 Generate normal-mode code.
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parents:
diff changeset
329
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
330 mno-mips3d
111
kono
parents: 67
diff changeset
331 Target Report RejectNegative Var(TARGET_MIPS3D, 0)
kono
parents: 67
diff changeset
332 Do not use MIPS-3D instructions.
0
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parents:
diff changeset
333
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
334 mpaired-single
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
335 Target Report Mask(PAIRED_SINGLE_FLOAT)
111
kono
parents: 67
diff changeset
336 Use paired-single floating-point instructions.
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parents:
diff changeset
337
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
338 mr10k-cache-barrier=
111
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diff changeset
339 Target Joined RejectNegative Enum(mips_r10k_cache_barrier_setting) Var(mips_r10k_cache_barrier) Init(R10K_CACHE_BARRIER_NONE)
kono
parents: 67
diff changeset
340 -mr10k-cache-barrier=SETTING Specify when r10k cache barriers should be inserted.
kono
parents: 67
diff changeset
341
kono
parents: 67
diff changeset
342 Enum
kono
parents: 67
diff changeset
343 Name(mips_r10k_cache_barrier_setting) Type(enum mips_r10k_cache_barrier_setting)
kono
parents: 67
diff changeset
344 Valid arguments to -mr10k-cache-barrier=:
kono
parents: 67
diff changeset
345
kono
parents: 67
diff changeset
346 EnumValue
kono
parents: 67
diff changeset
347 Enum(mips_r10k_cache_barrier_setting) String(load-store) Value(R10K_CACHE_BARRIER_LOAD_STORE)
kono
parents: 67
diff changeset
348
kono
parents: 67
diff changeset
349 EnumValue
kono
parents: 67
diff changeset
350 Enum(mips_r10k_cache_barrier_setting) String(store) Value(R10K_CACHE_BARRIER_STORE)
kono
parents: 67
diff changeset
351
kono
parents: 67
diff changeset
352 EnumValue
kono
parents: 67
diff changeset
353 Enum(mips_r10k_cache_barrier_setting) String(none) Value(R10K_CACHE_BARRIER_NONE)
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parents:
diff changeset
354
55
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
355 mrelax-pic-calls
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ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
356 Target Report Mask(RELAX_PIC_CALLS)
111
kono
parents: 67
diff changeset
357 Try to allow the linker to turn PIC calls into direct calls.
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
358
0
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
359 mshared
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
360 Target Report Var(TARGET_SHARED) Init(1)
111
kono
parents: 67
diff changeset
361 When generating -mabicalls code, make the code suitable for use in shared libraries.
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
362
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
363 msingle-float
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
364 Target Report RejectNegative Mask(SINGLE_FLOAT)
111
kono
parents: 67
diff changeset
365 Restrict the use of hardware floating-point instructions to 32-bit operations.
0
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
366
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
367 msmartmips
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
368 Target Report Mask(SMARTMIPS)
111
kono
parents: 67
diff changeset
369 Use SmartMIPS instructions.
0
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
370
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
371 msoft-float
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
372 Target Report RejectNegative Mask(SOFT_FLOAT_ABI)
111
kono
parents: 67
diff changeset
373 Prevent the use of all hardware floating-point instructions.
0
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
374
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
375 msplit-addresses
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
376 Target Report Mask(SPLIT_ADDRESSES)
111
kono
parents: 67
diff changeset
377 Optimize lui/addiu address loads.
0
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parents:
diff changeset
378
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
379 msym32
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
380 Target Report Var(TARGET_SYM32)
111
kono
parents: 67
diff changeset
381 Assume all symbols have 32-bit values.
0
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kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
382
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
383 msynci
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
384 Target Report Mask(SYNCI)
111
kono
parents: 67
diff changeset
385 Use synci instruction to invalidate i-cache.
kono
parents: 67
diff changeset
386
kono
parents: 67
diff changeset
387 mlra
kono
parents: 67
diff changeset
388 Target Report Var(mips_lra_flag) Init(1) Save
kono
parents: 67
diff changeset
389 Use LRA instead of reload.
kono
parents: 67
diff changeset
390
kono
parents: 67
diff changeset
391 mlxc1-sxc1
kono
parents: 67
diff changeset
392 Target Report Var(mips_lxc1_sxc1) Init(1)
kono
parents: 67
diff changeset
393 Use lwxc1/swxc1/ldxc1/sdxc1 instructions where applicable.
kono
parents: 67
diff changeset
394
kono
parents: 67
diff changeset
395 mmadd4
kono
parents: 67
diff changeset
396 Target Report Var(mips_madd4) Init(1)
kono
parents: 67
diff changeset
397 Use 4-operand madd.s/madd.d and related instructions where applicable.
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
398
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
399 mtune=
111
kono
parents: 67
diff changeset
400 Target RejectNegative Joined Var(mips_tune_option) ToLower Enum(mips_arch_opt_value)
kono
parents: 67
diff changeset
401 -mtune=PROCESSOR Optimize the output for PROCESSOR.
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
402
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
403 muninit-const-in-rodata
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
404 Target Report Var(TARGET_UNINIT_CONST_IN_RODATA)
111
kono
parents: 67
diff changeset
405 Put uninitialized constants in ROM (needs -membedded-data).
kono
parents: 67
diff changeset
406
kono
parents: 67
diff changeset
407 mvirt
kono
parents: 67
diff changeset
408 Target Report Var(TARGET_VIRT)
kono
parents: 67
diff changeset
409 Use Virtualization (VZ) instructions.
kono
parents: 67
diff changeset
410
kono
parents: 67
diff changeset
411 mxpa
kono
parents: 67
diff changeset
412 Target Report Var(TARGET_XPA)
kono
parents: 67
diff changeset
413 Use eXtended Physical Address (XPA) instructions.
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
414
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
415 mcrc
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
416 Target Report Var(TARGET_CRC)
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
417 Use Cyclic Redundancy Check (CRC) instructions.
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
418
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
419 mginv
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
420 Target Report Var(TARGET_GINV)
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
421 Use Global INValidate (GINV) instructions.
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
422
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
423 mvr4130-align
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
424 Target Report Mask(VR4130_ALIGN)
111
kono
parents: 67
diff changeset
425 Perform VR4130-specific alignment optimizations.
0
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
426
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
427 mxgot
a06113de4d67 first commit
kent <kent@cr.ie.u-ryukyu.ac.jp>
parents:
diff changeset
428 Target Report Var(TARGET_XGOT)
111
kono
parents: 67
diff changeset
429 Lift restrictions on GOT size.
kono
parents: 67
diff changeset
430
kono
parents: 67
diff changeset
431 modd-spreg
kono
parents: 67
diff changeset
432 Target Report Mask(ODD_SPREG)
kono
parents: 67
diff changeset
433 Enable use of odd-numbered single-precision registers.
kono
parents: 67
diff changeset
434
kono
parents: 67
diff changeset
435 mframe-header-opt
kono
parents: 67
diff changeset
436 Target Report Var(flag_frame_header_optimization) Optimization
kono
parents: 67
diff changeset
437 Optimize frame header.
67
f6334be47118 update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents: 63
diff changeset
438
f6334be47118 update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents: 63
diff changeset
439 noasmopt
f6334be47118 update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents: 63
diff changeset
440 Driver
111
kono
parents: 67
diff changeset
441
kono
parents: 67
diff changeset
442 mload-store-pairs
kono
parents: 67
diff changeset
443 Target Report Var(TARGET_LOAD_STORE_PAIRS) Init(1)
kono
parents: 67
diff changeset
444 Enable load/store bonding.
kono
parents: 67
diff changeset
445
kono
parents: 67
diff changeset
446 mcompact-branches=
kono
parents: 67
diff changeset
447 Target RejectNegative JoinedOrMissing Var(mips_cb) Report Enum(mips_cb_setting) Init(MIPS_CB_OPTIMAL)
kono
parents: 67
diff changeset
448 Specify the compact branch usage policy.
kono
parents: 67
diff changeset
449
kono
parents: 67
diff changeset
450 Enum
kono
parents: 67
diff changeset
451 Name(mips_cb_setting) Type(enum mips_cb_setting)
kono
parents: 67
diff changeset
452 Policies available for use with -mcompact-branches=:
kono
parents: 67
diff changeset
453
kono
parents: 67
diff changeset
454 EnumValue
kono
parents: 67
diff changeset
455 Enum(mips_cb_setting) String(never) Value(MIPS_CB_NEVER)
kono
parents: 67
diff changeset
456
kono
parents: 67
diff changeset
457 EnumValue
kono
parents: 67
diff changeset
458 Enum(mips_cb_setting) String(optimal) Value(MIPS_CB_OPTIMAL)
kono
parents: 67
diff changeset
459
kono
parents: 67
diff changeset
460 EnumValue
kono
parents: 67
diff changeset
461 Enum(mips_cb_setting) String(always) Value(MIPS_CB_ALWAYS)