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annotate gcc/config/nds32/nds32-n13.md @ 131:84e7813d76e9

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gcc-8.2
author mir3636
date Thu, 25 Oct 2018 07:37:49 +0900
parents
children 1830386684a0
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131
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1 ;; Pipeline descriptions of Andes NDS32 cpu for GNU compiler
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2 ;; Copyright (C) 2012-2018 Free Software Foundation, Inc.
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3 ;; Contributed by Andes Technology Corporation.
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4 ;;
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5 ;; This file is part of GCC.
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6 ;;
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7 ;; GCC is free software; you can redistribute it and/or modify it
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8 ;; under the terms of the GNU General Public License as published
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9 ;; by the Free Software Foundation; either version 3, or (at your
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10 ;; option) any later version.
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11 ;;
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12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
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13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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15 ;; License for more details.
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16 ;;
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17 ;; You should have received a copy of the GNU General Public License
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18 ;; along with GCC; see the file COPYING3. If not see
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19 ;; <http://www.gnu.org/licenses/>.
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20
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21
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22 ;; ------------------------------------------------------------------------
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23 ;; Define N13 pipeline settings.
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24 ;; ------------------------------------------------------------------------
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25
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26 (define_automaton "nds32_n13_machine")
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27
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28 ;; ------------------------------------------------------------------------
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29 ;; Pipeline Stages
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30 ;; ------------------------------------------------------------------------
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31 ;; F1 - Instruction Fetch First
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32 ;; Instruction Tag/Data Arrays
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33 ;; ITLB Address Translation
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34 ;; Branch Target Buffer Prediction
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35 ;; F2 - Instruction Fetch Second
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36 ;; Instruction Cache Hit Detection
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37 ;; Cache Way Selection
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38 ;; Inustruction Alignment
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39 ;; I1 - Instruction Issue First / Instruction Decode
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40 ;; Instruction Cache Replay Triggering
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41 ;; 32/16-Bit Instruction Decode
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42 ;; Return Address Stack Prediction
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43 ;; I2 - Instruction Issue Second / Register File Access
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44 ;; Instruction Issue Logic
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45 ;; Register File Access
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46 ;; E1 - Instruction Execute First / Address Generation / MAC First
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47 ;; Data Access Address generation
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48 ;; Multiply Operation
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49 ;; E2 - Instruction Execute Second / Data Access First / MAC Second /
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50 ;; ALU Execute
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51 ;; Skewed ALU
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52 ;; Branch/Jump/Return Resolution
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53 ;; Data Tag/Data arrays
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54 ;; DTLB address translation
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55 ;; Accumulation Operation
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56 ;; E3 - Instruction Execute Third / Data Access Second
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57 ;; Data Cache Hit Detection
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58 ;; Cache Way Selection
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59 ;; Data Alignment
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60 ;; E4 - Instruction Execute Fourth / Write Back
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61 ;; Interruption Resolution
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62 ;; Instruction Retire
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63 ;; Register File Write Back
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64
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65 (define_cpu_unit "n13_i1" "nds32_n13_machine")
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66 (define_cpu_unit "n13_i2" "nds32_n13_machine")
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67 (define_cpu_unit "n13_e1" "nds32_n13_machine")
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68 (define_cpu_unit "n13_e2" "nds32_n13_machine")
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69 (define_cpu_unit "n13_e3" "nds32_n13_machine")
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70 (define_cpu_unit "n13_e4" "nds32_n13_machine")
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71
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72 (define_insn_reservation "nds_n13_unknown" 1
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73 (and (eq_attr "type" "unknown")
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74 (eq_attr "pipeline_model" "n13"))
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75 "n13_i1, n13_i2, n13_e1, n13_e2, n13_e3, n13_e4")
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76
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77 (define_insn_reservation "nds_n13_misc" 1
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78 (and (eq_attr "type" "misc")
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79 (eq_attr "pipeline_model" "n13"))
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80 "n13_i1, n13_i2, n13_e1, n13_e2, n13_e3, n13_e4")
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81
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82 (define_insn_reservation "nds_n13_mmu" 1
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83 (and (eq_attr "type" "mmu")
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84 (eq_attr "pipeline_model" "n13"))
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85 "n13_i1, n13_i2, n13_e1, n13_e2, n13_e3, n13_e4")
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86
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87 (define_insn_reservation "nds_n13_alu" 1
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88 (and (eq_attr "type" "alu")
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89 (eq_attr "pipeline_model" "n13"))
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90 "n13_i1, n13_i2, n13_e1, n13_e2, n13_e3, n13_e4")
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91
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92 (define_insn_reservation "nds_n13_alu_shift" 1
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93 (and (eq_attr "type" "alu_shift")
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94 (eq_attr "pipeline_model" "n13"))
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95 "n13_i1, n13_i1+n13_i2, n13_i2+n13_e1, n13_e1+n13_e2, n13_e2+n13_e3, n13_e3+n13_e4, n13_e4")
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96
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97 (define_insn_reservation "nds_n13_pbsad" 1
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98 (and (eq_attr "type" "pbsad")
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99 (eq_attr "pipeline_model" "n13"))
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100 "n13_i1, n13_i2, n13_e1, n13_e2*2, n13_e3, n13_e4")
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101
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102 (define_insn_reservation "nds_n13_pbsada" 1
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103 (and (eq_attr "type" "pbsada")
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104 (eq_attr "pipeline_model" "n13"))
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105 "n13_i1, n13_i2, n13_e1, n13_e2*3, n13_e3, n13_e4")
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106
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107 (define_insn_reservation "nds_n13_load" 1
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108 (and (match_test "nds32::load_single_p (insn)")
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109 (eq_attr "pipeline_model" "n13"))
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110 "n13_i1, n13_i2, n13_e1, n13_e2, n13_e3, n13_e4")
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111
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112 (define_insn_reservation "nds_n13_store" 1
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113 (and (match_test "nds32::store_single_p (insn)")
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114 (eq_attr "pipeline_model" "n13"))
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115 "n13_i1, n13_i2, n13_e1, n13_e2, n13_e3, n13_e4")
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116
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117 (define_insn_reservation "nds_n13_load_multiple_1" 1
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118 (and (and (eq_attr "type" "load_multiple")
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119 (eq_attr "combo" "1"))
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120 (eq_attr "pipeline_model" "n13"))
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121 "n13_i1, n13_i2, n13_e1, n13_e2, n13_e3, n13_e4")
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122
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123 (define_insn_reservation "nds_n13_load_multiple_2" 1
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124 (and (ior (and (eq_attr "type" "load_multiple")
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125 (eq_attr "combo" "2"))
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126 (match_test "nds32::load_double_p (insn)"))
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127 (eq_attr "pipeline_model" "n13"))
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128 "n13_i1, n13_i1+n13_i2, n13_i2+n13_e1, n13_e1+n13_e2, n13_e2+n13_e3, n13_e3+n13_e4, n13_e4")
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129
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130 (define_insn_reservation "nds_n13_load_multiple_3" 1
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131 (and (and (eq_attr "type" "load_multiple")
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132 (eq_attr "combo" "3"))
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133 (eq_attr "pipeline_model" "n13"))
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134 "n13_i1, n13_i2+n13_i2, n13_i1+n13_i2+n13_e1, n13_i2+n13_e1+n13_e2, n13_e1+n13_e2+n13_e3, n13_e2+n13_e3+n13_e4, n13_e3+n13_e4, n13_e4")
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135
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136 (define_insn_reservation "nds_n13_load_multiple_4" 1
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137 (and (and (eq_attr "type" "load_multiple")
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138 (eq_attr "combo" "4"))
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139 (eq_attr "pipeline_model" "n13"))
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140 "n13_i1, n13_i1+n13_i2, n13_i1+n13_i2+n13_e1, n13_i1+n13_i2+n13_e1+n13_e2, n13_i2+n13_e1+n13_e2+n13_e3, n13_e1+n13_e2+n13_e3+n13_e4, n13_e2+n13_e3+n13_e4, n13_e3+n13_e4, n13_e4")
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141
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142 (define_insn_reservation "nds_n13_load_multiple_5" 1
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143 (and (and (eq_attr "type" "load_multiple")
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144 (eq_attr "combo" "5"))
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145 (eq_attr "pipeline_model" "n13"))
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146 "n13_i1, n13_i1+n13_i2, n13_i1+n13_i2+n13_e1, n13_i1+n13_i2+n13_e1+n13_e2, n13_i1+n13_i2+n13_e1+n13_e2+n13_e3, n13_i2+n13_e1+n13_e2+n13_e3+n13_e4, n13_e1+n13_e2+n13_e3+n13_e4, n13_e2+n13_e3+n13_e4, n13_e3+n13_e4, n13_e4")
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147
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148 (define_insn_reservation "nds_n13_load_multiple_6" 1
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149 (and (and (eq_attr "type" "load_multiple")
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150 (eq_attr "combo" "6"))
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151 (eq_attr "pipeline_model" "n13"))
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152 "n13_i1, n13_i1+n13_i2, n13_i1+n13_i2+n13_e1, n13_i1+n13_i2+n13_e1+n13_e2, n13_i1+n13_i2+n13_e1+n13_e2+n13_e3, n13_i1+n13_i2+n13_e1+n13_e2+n13_e3+n13_e4, n13_i2+n13_e1+n13_e2+n13_e3+n13_e4, n13_e1+n13_e2+n13_e3+n13_e4, n13_e2+n13_e3+n13_e4, n13_e3+n13_e4, n13_e4")
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153
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154 (define_insn_reservation "nds_n13_load_multiple_7" 1
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155 (and (and (eq_attr "type" "load_multiple")
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156 (eq_attr "combo" "7"))
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157 (eq_attr "pipeline_model" "n13"))
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158 "n13_i1, n13_i1+n13_i2, n13_i1+n13_i2+n13_e1, n13_i1+n13_i2+n13_e1+n13_e2, n13_i1+n13_i2+n13_e1+n13_e2+n13_e3, (n13_i1+n13_i2+n13_e1+n13_e2+n13_e3+n13_e4)*2, n13_i2+n13_e1+n13_e2+n13_e3+n13_e4, n13_e1+n13_e2+n13_e3+n13_e4, n13_e2+n13_e3+n13_e4, n13_e3+n13_e4, n13_e4")
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159
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160 (define_insn_reservation "nds_n13_load_multiple_8" 1
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161 (and (and (eq_attr "type" "load_multiple")
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162 (eq_attr "combo" "8"))
84e7813d76e9 gcc-8.2
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163 (eq_attr "pipeline_model" "n13"))
84e7813d76e9 gcc-8.2
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164 "n13_i1, n13_i1+n13_i2, n13_i1+n13_i2+n13_e1, n13_i1+n13_i2+n13_e1+n13_e2, n13_i1+n13_i2+n13_e1+n13_e2+n13_e3, (n13_i1+n13_i2+n13_e1+n13_e2+n13_e3+n13_e4)*3, n13_i2+n13_e1+n13_e2+n13_e3+n13_e4, n13_e1+n13_e2+n13_e3+n13_e4, n13_e2+n13_e3+n13_e4, n13_e3+n13_e4, n13_e4")
84e7813d76e9 gcc-8.2
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165
84e7813d76e9 gcc-8.2
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166 (define_insn_reservation "nds_n13_load_multiple_12" 1
84e7813d76e9 gcc-8.2
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167 (and (and (eq_attr "type" "load_multiple")
84e7813d76e9 gcc-8.2
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168 (eq_attr "combo" "12"))
84e7813d76e9 gcc-8.2
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169 (eq_attr "pipeline_model" "n13"))
84e7813d76e9 gcc-8.2
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170 "n13_i1, n13_i1+n13_i2, n13_i1+n13_i2+n13_e1, n13_i1+n13_i2+n13_e1+n13_e2, n13_i1+n13_i2+n13_e1+n13_e2+n13_e3, (n13_i1+n13_i2+n13_e1+n13_e2+n13_e3+n13_e4)*7, n13_i2+n13_e1+n13_e2+n13_e3+n13_e4, n13_e1+n13_e2+n13_e3+n13_e4, n13_e2+n13_e3+n13_e4, n13_e3+n13_e4, n13_e4")
84e7813d76e9 gcc-8.2
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171
84e7813d76e9 gcc-8.2
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172 (define_insn_reservation "nds_n13_store_multiple_1" 1
84e7813d76e9 gcc-8.2
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173 (and (and (eq_attr "type" "store_multiple")
84e7813d76e9 gcc-8.2
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174 (eq_attr "combo" "1"))
84e7813d76e9 gcc-8.2
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175 (eq_attr "pipeline_model" "n13"))
84e7813d76e9 gcc-8.2
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176 "n13_i1, n13_i2, n13_e1, n13_e2, n13_e3, n13_e4")
84e7813d76e9 gcc-8.2
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177
84e7813d76e9 gcc-8.2
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178 (define_insn_reservation "nds_n13_store_multiple_2" 1
84e7813d76e9 gcc-8.2
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179 (and (ior (and (eq_attr "type" "store_multiple")
84e7813d76e9 gcc-8.2
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180 (eq_attr "combo" "2"))
84e7813d76e9 gcc-8.2
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181 (match_test "nds32::store_double_p (insn)"))
84e7813d76e9 gcc-8.2
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182 (eq_attr "pipeline_model" "n13"))
84e7813d76e9 gcc-8.2
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183 "n13_i1, n13_i1+n13_i2, n13_i2+n13_e1, n13_e1+n13_e2, n13_e2+n13_e3, n13_e3+n13_e4, n13_e4")
84e7813d76e9 gcc-8.2
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184
84e7813d76e9 gcc-8.2
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185 (define_insn_reservation "nds_n13_store_multiple_3" 1
84e7813d76e9 gcc-8.2
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186 (and (and (eq_attr "type" "store_multiple")
84e7813d76e9 gcc-8.2
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187 (eq_attr "combo" "3"))
84e7813d76e9 gcc-8.2
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188 (eq_attr "pipeline_model" "n13"))
84e7813d76e9 gcc-8.2
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189 "n13_i1, n13_i2+n13_i2, n13_i1+n13_i2+n13_e1, n13_i2+n13_e1+n13_e2, n13_e1+n13_e2+n13_e3, n13_e2+n13_e3+n13_e4, n13_e3+n13_e4, n13_e4")
84e7813d76e9 gcc-8.2
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190
84e7813d76e9 gcc-8.2
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191 (define_insn_reservation "nds_n13_store_multiple_4" 1
84e7813d76e9 gcc-8.2
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192 (and (and (eq_attr "type" "store_multiple")
84e7813d76e9 gcc-8.2
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193 (eq_attr "combo" "4"))
84e7813d76e9 gcc-8.2
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194 (eq_attr "pipeline_model" "n13"))
84e7813d76e9 gcc-8.2
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195 "n13_i1, n13_i1+n13_i2, n13_i1+n13_i2+n13_e1, n13_i1+n13_i2+n13_e1+n13_e2, n13_i2+n13_e1+n13_e2+n13_e3, n13_e1+n13_e2+n13_e3+n13_e4, n13_e2+n13_e3+n13_e4, n13_e3+n13_e4, n13_e4")
84e7813d76e9 gcc-8.2
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196
84e7813d76e9 gcc-8.2
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197 (define_insn_reservation "nds_n13_store_multiple_5" 1
84e7813d76e9 gcc-8.2
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198 (and (and (eq_attr "type" "store_multiple")
84e7813d76e9 gcc-8.2
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199 (eq_attr "combo" "5"))
84e7813d76e9 gcc-8.2
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200 (eq_attr "pipeline_model" "n13"))
84e7813d76e9 gcc-8.2
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201 "n13_i1, n13_i1+n13_i2, n13_i1+n13_i2+n13_e1, n13_i1+n13_i2+n13_e1+n13_e2, n13_i1+n13_i2+n13_e1+n13_e2+n13_e3, n13_i2+n13_e1+n13_e2+n13_e3+n13_e4, n13_e1+n13_e2+n13_e3+n13_e4, n13_e2+n13_e3+n13_e4, n13_e3+n13_e4, n13_e4")
84e7813d76e9 gcc-8.2
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202
84e7813d76e9 gcc-8.2
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diff changeset
203 (define_insn_reservation "nds_n13_store_multiple_6" 1
84e7813d76e9 gcc-8.2
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204 (and (and (eq_attr "type" "store_multiple")
84e7813d76e9 gcc-8.2
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205 (eq_attr "combo" "6"))
84e7813d76e9 gcc-8.2
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206 (eq_attr "pipeline_model" "n13"))
84e7813d76e9 gcc-8.2
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207 "n13_i1, n13_i1+n13_i2, n13_i1+n13_i2+n13_e1, n13_i1+n13_i2+n13_e1+n13_e2, n13_i1+n13_i2+n13_e1+n13_e2+n13_e3, n13_i1+n13_i2+n13_e1+n13_e2+n13_e3+n13_e4, n13_i2+n13_e1+n13_e2+n13_e3+n13_e4, n13_e1+n13_e2+n13_e3+n13_e4, n13_e2+n13_e3+n13_e4, n13_e3+n13_e4, n13_e4")
84e7813d76e9 gcc-8.2
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208
84e7813d76e9 gcc-8.2
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209 (define_insn_reservation "nds_n13_store_multiple_7" 1
84e7813d76e9 gcc-8.2
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210 (and (and (eq_attr "type" "store_multiple")
84e7813d76e9 gcc-8.2
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211 (eq_attr "combo" "7"))
84e7813d76e9 gcc-8.2
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212 (eq_attr "pipeline_model" "n13"))
84e7813d76e9 gcc-8.2
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213 "n13_i1, n13_i1+n13_i2, n13_i1+n13_i2+n13_e1, n13_i1+n13_i2+n13_e1+n13_e2, n13_i1+n13_i2+n13_e1+n13_e2+n13_e3, (n13_i1+n13_i2+n13_e1+n13_e2+n13_e3+n13_e4)*2, n13_i2+n13_e1+n13_e2+n13_e3+n13_e4, n13_e1+n13_e2+n13_e3+n13_e4, n13_e2+n13_e3+n13_e4, n13_e3+n13_e4, n13_e4")
84e7813d76e9 gcc-8.2
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214
84e7813d76e9 gcc-8.2
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215 (define_insn_reservation "nds_n13_store_multiple_8" 1
84e7813d76e9 gcc-8.2
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216 (and (and (eq_attr "type" "store_multiple")
84e7813d76e9 gcc-8.2
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217 (eq_attr "combo" "8"))
84e7813d76e9 gcc-8.2
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218 (eq_attr "pipeline_model" "n13"))
84e7813d76e9 gcc-8.2
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219 "n13_i1, n13_i1+n13_i2, n13_i1+n13_i2+n13_e1, n13_i1+n13_i2+n13_e1+n13_e2, n13_i1+n13_i2+n13_e1+n13_e2+n13_e3, (n13_i1+n13_i2+n13_e1+n13_e2+n13_e3+n13_e4)*3, n13_i2+n13_e1+n13_e2+n13_e3+n13_e4, n13_e1+n13_e2+n13_e3+n13_e4, n13_e2+n13_e3+n13_e4, n13_e3+n13_e4, n13_e4")
84e7813d76e9 gcc-8.2
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220
84e7813d76e9 gcc-8.2
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221 (define_insn_reservation "nds_n13_store_multiple_12" 1
84e7813d76e9 gcc-8.2
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222 (and (and (eq_attr "type" "store_multiple")
84e7813d76e9 gcc-8.2
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223 (eq_attr "combo" "12"))
84e7813d76e9 gcc-8.2
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224 (eq_attr "pipeline_model" "n13"))
84e7813d76e9 gcc-8.2
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225 "n13_i1, n13_i1+n13_i2, n13_i1+n13_i2+n13_e1, n13_i1+n13_i2+n13_e1+n13_e2, n13_i1+n13_i2+n13_e1+n13_e2+n13_e3, (n13_i1+n13_i2+n13_e1+n13_e2+n13_e3+n13_e4)*7, n13_i2+n13_e1+n13_e2+n13_e3+n13_e4, n13_e1+n13_e2+n13_e3+n13_e4, n13_e2+n13_e3+n13_e4, n13_e3+n13_e4, n13_e4")
84e7813d76e9 gcc-8.2
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226
84e7813d76e9 gcc-8.2
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227 ;; The multiplier at E1 takes two cycles.
84e7813d76e9 gcc-8.2
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228 (define_insn_reservation "nds_n13_mul" 1
84e7813d76e9 gcc-8.2
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229 (and (eq_attr "type" "mul")
84e7813d76e9 gcc-8.2
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230 (eq_attr "pipeline_model" "n13"))
84e7813d76e9 gcc-8.2
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diff changeset
231 "n13_i1, n13_i2, n13_e1*2, n13_e2, n13_e3, n13_e4")
84e7813d76e9 gcc-8.2
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232
84e7813d76e9 gcc-8.2
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233 (define_insn_reservation "nds_n13_mac" 1
84e7813d76e9 gcc-8.2
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234 (and (eq_attr "type" "mac")
84e7813d76e9 gcc-8.2
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235 (eq_attr "pipeline_model" "n13"))
84e7813d76e9 gcc-8.2
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diff changeset
236 "n13_i1, n13_i2, n13_e1*2, n13_e2, n13_e3, n13_e4")
84e7813d76e9 gcc-8.2
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237
84e7813d76e9 gcc-8.2
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238 ;; The cycles consumed at E2 are 32 - CLZ(abs(Ra)) + 2,
84e7813d76e9 gcc-8.2
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239 ;; so the worst case is 34.
84e7813d76e9 gcc-8.2
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240 (define_insn_reservation "nds_n13_div" 1
84e7813d76e9 gcc-8.2
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241 (and (eq_attr "type" "div")
84e7813d76e9 gcc-8.2
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242 (eq_attr "pipeline_model" "n13"))
84e7813d76e9 gcc-8.2
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parents:
diff changeset
243 "n13_i1, n13_i2, n13_e1, n13_e2*34, n13_e3, n13_e4")
84e7813d76e9 gcc-8.2
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244
84e7813d76e9 gcc-8.2
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245 (define_insn_reservation "nds_n13_branch" 1
84e7813d76e9 gcc-8.2
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246 (and (eq_attr "type" "branch")
84e7813d76e9 gcc-8.2
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247 (eq_attr "pipeline_model" "n13"))
84e7813d76e9 gcc-8.2
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diff changeset
248 "n13_i1, n13_i2, n13_e1, n13_e2, n13_e3, n13_e4")
84e7813d76e9 gcc-8.2
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249
84e7813d76e9 gcc-8.2
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250 ;; ------------------------------------------------------------------------
84e7813d76e9 gcc-8.2
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251 ;; Comment Notations and Bypass Rules
84e7813d76e9 gcc-8.2
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252 ;; ------------------------------------------------------------------------
84e7813d76e9 gcc-8.2
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253 ;; Producers (LHS)
84e7813d76e9 gcc-8.2
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254 ;; LD
84e7813d76e9 gcc-8.2
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255 ;; Load data from the memory and produce the loaded data. The result is
84e7813d76e9 gcc-8.2
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256 ;; ready at E3.
84e7813d76e9 gcc-8.2
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257 ;; LMW(N, M)
84e7813d76e9 gcc-8.2
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258 ;; There are N micro-operations within an instruction that loads multiple
84e7813d76e9 gcc-8.2
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259 ;; words. The result produced by the M-th micro-operation is sent to
84e7813d76e9 gcc-8.2
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260 ;; consumers. The result is ready at E3.
84e7813d76e9 gcc-8.2
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261 ;; ADDR_OUT
84e7813d76e9 gcc-8.2
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262 ;; Most load/store instructions can produce an address output if updating
84e7813d76e9 gcc-8.2
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263 ;; the base register is required. The result is ready at E2, which is
84e7813d76e9 gcc-8.2
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264 ;; produced by ALU.
84e7813d76e9 gcc-8.2
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265 ;; ALU, ALU_SHIFT, SIMD
84e7813d76e9 gcc-8.2
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266 ;; Compute data in ALU and produce the data. The result is ready at E2.
84e7813d76e9 gcc-8.2
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267 ;; MUL, MAC
84e7813d76e9 gcc-8.2
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268 ;; Compute data in the multiply-adder and produce the data. The result
84e7813d76e9 gcc-8.2
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269 ;; is ready at E2.
84e7813d76e9 gcc-8.2
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270 ;; DIV
84e7813d76e9 gcc-8.2
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271 ;; Compute data in the divider and produce the data. The result is ready
84e7813d76e9 gcc-8.2
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272 ;; at E2.
84e7813d76e9 gcc-8.2
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273 ;; BR
84e7813d76e9 gcc-8.2
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274 ;; Branch-with-link instructions produces a result containing the return
84e7813d76e9 gcc-8.2
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275 ;; address. The result is ready at E2.
84e7813d76e9 gcc-8.2
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276 ;;
84e7813d76e9 gcc-8.2
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277 ;; Consumers (RHS)
84e7813d76e9 gcc-8.2
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278 ;; ALU
84e7813d76e9 gcc-8.2
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279 ;; General ALU instructions require operands at E2.
84e7813d76e9 gcc-8.2
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280 ;; ALU_E1
84e7813d76e9 gcc-8.2
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281 ;; Some special ALU instructions, such as BSE, BSP and MOVD44, require
84e7813d76e9 gcc-8.2
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282 ;; operand at E1.
84e7813d76e9 gcc-8.2
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283 ;; MUL, DIV, PBSAD, MMU
84e7813d76e9 gcc-8.2
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284 ;; Operands are required at E1.
84e7813d76e9 gcc-8.2
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285 ;; PBSADA_Rt, PBSADA_RaRb
84e7813d76e9 gcc-8.2
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286 ;; Operands Ra and Rb are required at E1, and the operand Rt is required
84e7813d76e9 gcc-8.2
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287 ;; at E2.
84e7813d76e9 gcc-8.2
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288 ;; ALU_SHIFT_Rb
84e7813d76e9 gcc-8.2
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289 ;; An ALU-SHIFT instruction consists of a shift micro-operation followed
84e7813d76e9 gcc-8.2
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290 ;; by an arithmetic micro-operation. The operand Rb is used by the first
84e7813d76e9 gcc-8.2
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291 ;; micro-operation, and there are some latencies if data dependency occurs.
84e7813d76e9 gcc-8.2
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292 ;; MAC_RaRb
84e7813d76e9 gcc-8.2
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293 ;; A MAC instruction does multiplication at E1 and does accumulation at E2,
84e7813d76e9 gcc-8.2
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294 ;; so the operand Rt is required at E2, and operands Ra and Rb are required
84e7813d76e9 gcc-8.2
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295 ;; at E1.
84e7813d76e9 gcc-8.2
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296 ;; ADDR_IN
84e7813d76e9 gcc-8.2
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297 ;; If an instruction requires an address as its input operand, the address
84e7813d76e9 gcc-8.2
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298 ;; is required at E1.
84e7813d76e9 gcc-8.2
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299 ;; ST
84e7813d76e9 gcc-8.2
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300 ;; A store instruction requires its data at E2.
84e7813d76e9 gcc-8.2
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301 ;; SMW(N, M)
84e7813d76e9 gcc-8.2
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302 ;; There are N micro-operations within an instruction that stores multiple
84e7813d76e9 gcc-8.2
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303 ;; words. Each M-th micro-operation requires its data at E2.
84e7813d76e9 gcc-8.2
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304 ;; BR
84e7813d76e9 gcc-8.2
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305 ;; If a branch instruction is conditional, its input data is required at E2.
84e7813d76e9 gcc-8.2
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306
84e7813d76e9 gcc-8.2
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307 ;; LD -> ALU_E1, PBSAD, PBSADA_RaRb, MUL, MAC_RaRb, DIV, MMU, ADDR_IN
84e7813d76e9 gcc-8.2
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parents:
diff changeset
308 (define_bypass 3
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
309 "nds_n13_load"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
310 "nds_n13_alu, nds_n13_pbsad, nds_n13_pbsada,\
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
311 nds_n13_mul, nds_n13_mac, nds_n13_div,\
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
312 nds_n13_mmu,\
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
313 nds_n13_load, nds_n13_store,\
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
314 nds_n13_load_multiple_1,nds_n13_load_multiple_2, nds_n13_load_multiple_3,\
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
315 nds_n13_load_multiple_4,nds_n13_load_multiple_5, nds_n13_load_multiple_6,\
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
316 nds_n13_load_multiple_7,nds_n13_load_multiple_8, nds_n13_load_multiple_12,\
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
317 nds_n13_store_multiple_1,nds_n13_store_multiple_2, nds_n13_store_multiple_3,\
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
318 nds_n13_store_multiple_4,nds_n13_store_multiple_5, nds_n13_store_multiple_6,\
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
319 nds_n13_store_multiple_7,nds_n13_store_multiple_8, nds_n13_store_multiple_12"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
320 "nds32_n13_load_to_e1_p"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
321 )
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
322
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
323 ;; LD -> ALU, ALU_SHIFT_Rb, PBSADA_Rt, BR, ST, SMW(N, 1)
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
324 (define_bypass 2
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
325 "nds_n13_load"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
326 "nds_n13_alu, nds_n13_alu_shift, nds_n13_pbsada, nds_n13_branch, nds_n13_store,\
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
327 nds_n13_store_multiple_1,nds_n13_store_multiple_2, nds_n13_store_multiple_3,\
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
328 nds_n13_store_multiple_4,nds_n13_store_multiple_5, nds_n13_store_multiple_6,\
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
329 nds_n13_store_multiple_7,nds_n13_store_multiple_8, nds_n13_store_multiple_12"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
330 "nds32_n13_load_to_e2_p"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
331 )
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
332
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
333 ;; LMW(N, N) -> ALU_E1, PBSAD, PBSADA_RaRb, MUL, MAC_RaRb, DIV, MMU, ADDR_IN
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
334 (define_bypass 3
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
335 "nds_n13_load_multiple_1,nds_n13_load_multiple_2, nds_n13_load_multiple_3,\
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
336 nds_n13_load_multiple_4,nds_n13_load_multiple_5, nds_n13_load_multiple_6,\
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
337 nds_n13_load_multiple_7,nds_n13_load_multiple_8, nds_n13_load_multiple_12"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
338 "nds_n13_alu, nds_n13_pbsad, nds_n13_pbsada,\
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
339 nds_n13_mul, nds_n13_mac, nds_n13_div,\
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
340 nds_n13_mmu,\
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
341 nds_n13_load, nds_n13_store,\
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
342 nds_n13_load_multiple_1,nds_n13_load_multiple_2, nds_n13_load_multiple_3,\
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
343 nds_n13_load_multiple_4,nds_n13_load_multiple_5, nds_n13_load_multiple_6,\
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
344 nds_n13_load_multiple_7,nds_n13_load_multiple_8, nds_n13_load_multiple_12,\
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
345 nds_n13_store_multiple_1,nds_n13_store_multiple_2, nds_n13_store_multiple_3,\
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
346 nds_n13_store_multiple_4,nds_n13_store_multiple_5, nds_n13_store_multiple_6,\
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
347 nds_n13_store_multiple_7,nds_n13_store_multiple_8, nds_n13_store_multiple_12"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
348 "nds32_n13_last_load_to_e1_p")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
349
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
350 ;; LMW(N, N) -> ALU, ALU_SHIFT_Rb, PBSADA_Rt, BR, ST, SMW(N, 1)
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
351 (define_bypass 2
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
352 "nds_n13_load_multiple_1,nds_n13_load_multiple_2, nds_n13_load_multiple_3,\
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
353 nds_n13_load_multiple_4,nds_n13_load_multiple_5, nds_n13_load_multiple_6,\
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
354 nds_n13_load_multiple_7,nds_n13_load_multiple_8, nds_n13_load_multiple_12"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
355 "nds_n13_alu, nds_n13_alu_shift, nds_n13_pbsada, nds_n13_branch, nds_n13_store,\
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
356 nds_n13_store_multiple_1,nds_n13_store_multiple_2, nds_n13_store_multiple_3,\
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
357 nds_n13_store_multiple_4,nds_n13_store_multiple_5, nds_n13_store_multiple_6,\
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
358 nds_n13_store_multiple_7,nds_n13_store_multiple_8, nds_n13_store_multiple_12"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
359 "nds32_n13_last_load_to_e2_p"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
360 )
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
361
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
362 ;; LMW(N, N - 1) -> ALU_E1, PBSAD, PBSADA_RaRb, MUL, MAC_RaRb, DIV, MMU, ADDR_IN
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
363 (define_bypass 2
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
364 "nds_n13_load_multiple_1,nds_n13_load_multiple_2, nds_n13_load_multiple_3,\
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
365 nds_n13_load_multiple_4,nds_n13_load_multiple_5, nds_n13_load_multiple_6,\
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
366 nds_n13_load_multiple_7,nds_n13_load_multiple_8, nds_n13_load_multiple_12"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
367 "nds_n13_alu, nds_n13_pbsad, nds_n13_pbsada,\
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
368 nds_n13_mul, nds_n13_mac, nds_n13_div,\
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
369 nds_n13_mmu,\
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
370 nds_n13_load, nds_n13_store,\
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
371 nds_n13_load_multiple_1,nds_n13_load_multiple_2, nds_n13_load_multiple_3,\
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
372 nds_n13_load_multiple_4,nds_n13_load_multiple_5, nds_n13_load_multiple_6,\
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
373 nds_n13_load_multiple_7,nds_n13_load_multiple_8, nds_n13_load_multiple_12,\
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
374 nds_n13_store_multiple_1,nds_n13_store_multiple_2, nds_n13_store_multiple_3,\
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
375 nds_n13_store_multiple_4,nds_n13_store_multiple_5, nds_n13_store_multiple_6,\
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
376 nds_n13_store_multiple_7,nds_n13_store_multiple_8, nds_n13_store_multiple_12"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
377 "nds32_n13_last_two_load_to_e1_p")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
378
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
379 ;; ALU, ALU_SHIFT, SIMD, BR, MUL, MAC, DIV, ADDR_OUT
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
380 ;; -> ALU_E1, PBSAD, PBSADA_RaRb, MUL, MAC_RaRb, DIV, MMU, ADDR_IN
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
381 (define_bypass 2
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
382 "nds_n13_alu, nds_n13_alu_shift, nds_n13_pbsad, nds_n13_pbsada, nds_n13_branch,\
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
383 nds_n13_mul, nds_n13_mac, nds_n13_div,\
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
384 nds_n13_load, nds_n13_store,\
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
385 nds_n13_load_multiple_1,nds_n13_load_multiple_2, nds_n13_load_multiple_3,\
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
386 nds_n13_load_multiple_4,nds_n13_load_multiple_5, nds_n13_load_multiple_6,\
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
387 nds_n13_load_multiple_7,nds_n13_load_multiple_8, nds_n13_load_multiple_12,\
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
388 nds_n13_store_multiple_1,nds_n13_store_multiple_2, nds_n13_store_multiple_3,\
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
389 nds_n13_store_multiple_4,nds_n13_store_multiple_5, nds_n13_store_multiple_6,\
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
390 nds_n13_store_multiple_7,nds_n13_store_multiple_8, nds_n13_store_multiple_12"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
391 "nds_n13_alu, nds_n13_pbsad, nds_n13_pbsada,\
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
392 nds_n13_mul, nds_n13_mac, nds_n13_div,\
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
393 nds_n13_mmu,\
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
394 nds_n13_load, nds_n13_store,\
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
395 nds_n13_load_multiple_1,nds_n13_load_multiple_2, nds_n13_load_multiple_3,\
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
396 nds_n13_load_multiple_4,nds_n13_load_multiple_5, nds_n13_load_multiple_6,\
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
397 nds_n13_load_multiple_7,nds_n13_load_multiple_8, nds_n13_load_multiple_12,\
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
398 nds_n13_store_multiple_1,nds_n13_store_multiple_2, nds_n13_store_multiple_3,\
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
399 nds_n13_store_multiple_4,nds_n13_store_multiple_5, nds_n13_store_multiple_6,\
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
400 nds_n13_store_multiple_7,nds_n13_store_multiple_8, nds_n13_store_multiple_12"
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
401 "nds32_n13_e2_to_e1_p")