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annotate gcc/config/nds32/nds32-n9-2r1w.md @ 131:84e7813d76e9

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gcc-8.2
author mir3636
date Thu, 25 Oct 2018 07:37:49 +0900
parents
children 1830386684a0
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131
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1 ;; Pipeline descriptions of Andes NDS32 cpu for GNU compiler
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2 ;; Copyright (C) 2012-2018 Free Software Foundation, Inc.
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3 ;; Contributed by Andes Technology Corporation.
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4 ;;
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5 ;; This file is part of GCC.
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6 ;;
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7 ;; GCC is free software; you can redistribute it and/or modify it
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8 ;; under the terms of the GNU General Public License as published
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9 ;; by the Free Software Foundation; either version 3, or (at your
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10 ;; option) any later version.
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11 ;;
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12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
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13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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15 ;; License for more details.
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16 ;;
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17 ;; You should have received a copy of the GNU General Public License
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18 ;; along with GCC; see the file COPYING3. If not see
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19 ;; <http://www.gnu.org/licenses/>.
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20
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21
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22 ;; ------------------------------------------------------------------------
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23 ;; Define N9 2R1W pipeline settings.
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24 ;; ------------------------------------------------------------------------
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25
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26 (define_automaton "nds32_n9_2r1w_machine")
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27
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28 ;; ------------------------------------------------------------------------
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29 ;; Pipeline Stages
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30 ;; ------------------------------------------------------------------------
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31 ;; IF - Instruction Fetch
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32 ;; II - Instruction Issue / Instruction Decode
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33 ;; EX - Instruction Execution
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34 ;; MM - Memory Execution
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35 ;; WB - Instruction Retire / Result Write-Back
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36
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37 (define_cpu_unit "n9_2r1w_ii" "nds32_n9_2r1w_machine")
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38 (define_cpu_unit "n9_2r1w_ex" "nds32_n9_2r1w_machine")
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39 (define_cpu_unit "n9_2r1w_mm" "nds32_n9_2r1w_machine")
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40 (define_cpu_unit "n9_2r1w_wb" "nds32_n9_2r1w_machine")
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41
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42 (define_insn_reservation "nds_n9_2r1w_unknown" 1
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43 (and (match_test "nds32_register_ports_config == REG_PORT_2R1W")
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44 (and (eq_attr "type" "unknown")
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45 (eq_attr "pipeline_model" "n9")))
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46 "n9_2r1w_ii, n9_2r1w_ex, n9_2r1w_mm, n9_2r1w_wb")
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47
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48 (define_insn_reservation "nds_n9_2r1w_misc" 1
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49 (and (match_test "nds32_register_ports_config == REG_PORT_2R1W")
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50 (and (eq_attr "type" "misc")
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51 (eq_attr "pipeline_model" "n9")))
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52 "n9_2r1w_ii, n9_2r1w_ex, n9_2r1w_mm, n9_2r1w_wb")
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53
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54 (define_insn_reservation "nds_n9_2r1w_mmu" 1
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55 (and (match_test "nds32_register_ports_config == REG_PORT_2R1W")
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56 (and (eq_attr "type" "mmu")
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57 (eq_attr "pipeline_model" "n9")))
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58 "n9_2r1w_ii, n9_2r1w_ex, n9_2r1w_mm, n9_2r1w_wb")
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59
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60 (define_insn_reservation "nds_n9_2r1w_alu" 1
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61 (and (match_test "nds32_register_ports_config == REG_PORT_2R1W")
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62 (and (eq_attr "type" "alu")
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63 (eq_attr "pipeline_model" "n9")))
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64 "n9_2r1w_ii, n9_2r1w_ex, n9_2r1w_mm, n9_2r1w_wb")
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65
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66 (define_insn_reservation "nds_n9_2r1w_alu_shift" 1
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67 (and (match_test "nds32_register_ports_config == REG_PORT_2R1W")
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68 (and (eq_attr "type" "alu_shift")
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69 (eq_attr "pipeline_model" "n9")))
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70 "n9_2r1w_ii, n9_2r1w_ii+n9_2r1w_ex, n9_2r1w_ex+n9_2r1w_mm, n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_wb")
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71
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72 (define_insn_reservation "nds_n9_2r1w_pbsad" 1
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73 (and (match_test "nds32_register_ports_config == REG_PORT_2R1W")
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74 (and (eq_attr "type" "pbsad")
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75 (eq_attr "pipeline_model" "n9")))
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76 "n9_2r1w_ii, n9_2r1w_ex*3, n9_2r1w_mm, n9_2r1w_wb")
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77
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78 (define_insn_reservation "nds_n9_2r1w_pbsada" 1
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79 (and (match_test "nds32_register_ports_config == REG_PORT_2R1W")
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80 (and (eq_attr "type" "pbsada")
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81 (eq_attr "pipeline_model" "n9")))
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82 "n9_2r1w_ii, n9_2r1w_ex*3, n9_2r1w_mm, n9_2r1w_wb")
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83
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84 (define_insn_reservation "nds_n9_2r1w_load" 1
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85 (and (match_test "nds32_register_ports_config == REG_PORT_2R1W")
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86 (and (match_test "nds32::load_single_p (insn)")
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87 (eq_attr "pipeline_model" "n9")))
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88 "n9_2r1w_ii, n9_2r1w_ex, n9_2r1w_mm, n9_2r1w_wb")
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89
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90 (define_insn_reservation "nds_n9_2r1w_store" 1
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91 (and (match_test "nds32_register_ports_config == REG_PORT_2R1W")
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92 (and (match_test "nds32::store_single_p (insn)")
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93 (eq_attr "pipeline_model" "n9")))
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94 "n9_2r1w_ii, n9_2r1w_ex, n9_2r1w_mm, n9_2r1w_wb")
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95
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96 (define_insn_reservation "nds_n9_2r1w_load_multiple_1" 1
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97 (and (match_test "nds32_register_ports_config == REG_PORT_2R1W")
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98 (and (eq_attr "pipeline_model" "n9")
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99 (and (eq_attr "type" "load_multiple")
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100 (eq_attr "combo" "1"))))
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101 "n9_2r1w_ii, n9_2r1w_ex, n9_2r1w_mm, n9_2r1w_wb")
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102
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103 (define_insn_reservation "nds_n9_2r1w_load_multiple_2" 1
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104 (and (match_test "nds32_register_ports_config == REG_PORT_2R1W")
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105 (and (eq_attr "pipeline_model" "n9")
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106 (ior (and (eq_attr "type" "load_multiple")
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107 (eq_attr "combo" "2"))
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108 (match_test "nds32::load_double_p (insn)"))))
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109 "n9_2r1w_ii, n9_2r1w_ii+n9_2r1w_ex, n9_2r1w_ex+n9_2r1w_mm, n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_wb")
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110
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111 (define_insn_reservation "nds_n9_2r1w_load_multiple_3" 1
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112 (and (match_test "nds32_register_ports_config == REG_PORT_2R1W")
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113 (and (eq_attr "pipeline_model" "n9")
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114 (and (eq_attr "type" "load_multiple")
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115 (eq_attr "combo" "3"))))
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116 "n9_2r1w_ii, n9_2r1w_ii+n9_2r1w_ex, n9_2r1w_ii+n9_2r1w_ex+n9_2r1w_mm, n9_2r1w_ex+n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_wb")
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117
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118 (define_insn_reservation "nds_n9_2r1w_load_multiple_4" 1
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119 (and (match_test "nds32_register_ports_config == REG_PORT_2R1W")
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120 (and (eq_attr "pipeline_model" "n9")
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121 (and (eq_attr "type" "load_multiple")
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122 (eq_attr "combo" "4"))))
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123 "n9_2r1w_ii, n9_2r1w_ii+n9_2r1w_ex, n9_2r1w_ii+n9_2r1w_ex+n9_2r1w_mm, n9_2r1w_ii+n9_2r1w_ex+n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_ex+n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_wb")
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124
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125 (define_insn_reservation "nds_n9_2r1w_load_multiple_5" 1
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126 (and (match_test "nds32_register_ports_config == REG_PORT_2R1W")
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127 (and (eq_attr "pipeline_model" "n9")
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128 (and (eq_attr "type" "load_multiple")
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129 (eq_attr "combo" "5"))))
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130 "n9_2r1w_ii, n9_2r1w_ii+n9_2r1w_ex, n9_2r1w_ii+n9_2r1w_ex+n9_2r1w_mm, (n9_2r1w_ii+n9_2r1w_ex+n9_2r1w_mm+n9_2r1w_wb)*2, n9_2r1w_ex+n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_wb")
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131
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132 (define_insn_reservation "nds_n9_2r1w_load_multiple_6" 1
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133 (and (match_test "nds32_register_ports_config == REG_PORT_2R1W")
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134 (and (eq_attr "pipeline_model" "n9")
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135 (and (eq_attr "type" "load_multiple")
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136 (eq_attr "combo" "6"))))
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137 "n9_2r1w_ii, n9_2r1w_ii+n9_2r1w_ex, n9_2r1w_ii+n9_2r1w_ex+n9_2r1w_mm, (n9_2r1w_ii+n9_2r1w_ex+n9_2r1w_mm+n9_2r1w_wb)*3, n9_2r1w_ex+n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_wb")
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138
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139 (define_insn_reservation "nds_n9_2r1w_load_multiple_7" 1
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140 (and (match_test "nds32_register_ports_config == REG_PORT_2R1W")
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141 (and (eq_attr "pipeline_model" "n9")
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142 (and (eq_attr "type" "load_multiple")
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143 (eq_attr "combo" "7"))))
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144 "n9_2r1w_ii, n9_2r1w_ii+n9_2r1w_ex, n9_2r1w_ii+n9_2r1w_ex+n9_2r1w_mm, (n9_2r1w_ii+n9_2r1w_ex+n9_2r1w_mm+n9_2r1w_wb)*4, n9_2r1w_ex+n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_wb")
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145
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146 (define_insn_reservation "nds_n9_2r1w_load_multiple_8" 1
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147 (and (match_test "nds32_register_ports_config == REG_PORT_2R1W")
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148 (and (eq_attr "pipeline_model" "n9")
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149 (and (eq_attr "type" "load_multiple")
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150 (eq_attr "combo" "8"))))
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151 "n9_2r1w_ii, n9_2r1w_ii+n9_2r1w_ex, n9_2r1w_ii+n9_2r1w_ex+n9_2r1w_mm, (n9_2r1w_ii+n9_2r1w_ex+n9_2r1w_mm+n9_2r1w_wb)*5, n9_2r1w_ex+n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_wb")
84e7813d76e9 gcc-8.2
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152
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
153 (define_insn_reservation "nds_n9_2r1w_load_multiple_12" 1
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
154 (and (match_test "nds32_register_ports_config == REG_PORT_2R1W")
84e7813d76e9 gcc-8.2
mir3636
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diff changeset
155 (and (eq_attr "pipeline_model" "n9")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
156 (and (eq_attr "type" "load_multiple")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
157 (eq_attr "combo" "12"))))
84e7813d76e9 gcc-8.2
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parents:
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158 "n9_2r1w_ii, n9_2r1w_ii+n9_2r1w_ex, n9_2r1w_ii+n9_2r1w_ex+n9_2r1w_mm, (n9_2r1w_ii+n9_2r1w_ex+n9_2r1w_mm+n9_2r1w_wb)*9, n9_2r1w_ex+n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_wb")
84e7813d76e9 gcc-8.2
mir3636
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159
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
160 (define_insn_reservation "nds_n9_2r1w_store_multiple_1" 1
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
161 (and (match_test "nds32_register_ports_config == REG_PORT_2R1W")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
162 (and (eq_attr "pipeline_model" "n9")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
163 (and (eq_attr "type" "store_multiple")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
164 (eq_attr "combo" "1"))))
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
165 "n9_2r1w_ii, n9_2r1w_ex, n9_2r1w_mm, n9_2r1w_wb")
84e7813d76e9 gcc-8.2
mir3636
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166
84e7813d76e9 gcc-8.2
mir3636
parents:
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167 (define_insn_reservation "nds_n9_2r1w_store_multiple_2" 1
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
168 (and (match_test "nds32_register_ports_config == REG_PORT_2R1W")
84e7813d76e9 gcc-8.2
mir3636
parents:
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169 (and (eq_attr "pipeline_model" "n9")
84e7813d76e9 gcc-8.2
mir3636
parents:
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170 (ior (and (eq_attr "type" "store_multiple")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
171 (eq_attr "combo" "2"))
84e7813d76e9 gcc-8.2
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172 (match_test "nds32::store_double_p (insn)"))))
84e7813d76e9 gcc-8.2
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173 "n9_2r1w_ii, n9_2r1w_ii+n9_2r1w_ex, n9_2r1w_ex+n9_2r1w_mm, n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_wb")
84e7813d76e9 gcc-8.2
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174
84e7813d76e9 gcc-8.2
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diff changeset
175 (define_insn_reservation "nds_n9_2r1w_store_multiple_3" 1
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
176 (and (match_test "nds32_register_ports_config == REG_PORT_2R1W")
84e7813d76e9 gcc-8.2
mir3636
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177 (and (eq_attr "pipeline_model" "n9")
84e7813d76e9 gcc-8.2
mir3636
parents:
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178 (and (eq_attr "type" "store_multiple")
84e7813d76e9 gcc-8.2
mir3636
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179 (eq_attr "combo" "3"))))
84e7813d76e9 gcc-8.2
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180 "n9_2r1w_ii, n9_2r1w_ii+n9_2r1w_ex, n9_2r1w_ii+n9_2r1w_ex+n9_2r1w_mm, n9_2r1w_ex+n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_wb")
84e7813d76e9 gcc-8.2
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181
84e7813d76e9 gcc-8.2
mir3636
parents:
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182 (define_insn_reservation "nds_n9_2r1w_store_multiple_4" 1
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
183 (and (match_test "nds32_register_ports_config == REG_PORT_2R1W")
84e7813d76e9 gcc-8.2
mir3636
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diff changeset
184 (and (eq_attr "pipeline_model" "n9")
84e7813d76e9 gcc-8.2
mir3636
parents:
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185 (and (eq_attr "type" "store_multiple")
84e7813d76e9 gcc-8.2
mir3636
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diff changeset
186 (eq_attr "combo" "4"))))
84e7813d76e9 gcc-8.2
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187 "n9_2r1w_ii, n9_2r1w_ii+n9_2r1w_ex, n9_2r1w_ii+n9_2r1w_ex+n9_2r1w_mm, n9_2r1w_ii+n9_2r1w_ex+n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_ex+n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_wb")
84e7813d76e9 gcc-8.2
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188
84e7813d76e9 gcc-8.2
mir3636
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diff changeset
189 (define_insn_reservation "nds_n9_2r1w_store_multiple_5" 1
84e7813d76e9 gcc-8.2
mir3636
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diff changeset
190 (and (match_test "nds32_register_ports_config == REG_PORT_2R1W")
84e7813d76e9 gcc-8.2
mir3636
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191 (and (eq_attr "pipeline_model" "n9")
84e7813d76e9 gcc-8.2
mir3636
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192 (and (eq_attr "type" "store_multiple")
84e7813d76e9 gcc-8.2
mir3636
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193 (eq_attr "combo" "5"))))
84e7813d76e9 gcc-8.2
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194 "n9_2r1w_ii, n9_2r1w_ii+n9_2r1w_ex, n9_2r1w_ii+n9_2r1w_ex+n9_2r1w_mm, (n9_2r1w_ii+n9_2r1w_ex+n9_2r1w_mm+n9_2r1w_wb)*2, n9_2r1w_ex+n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_wb")
84e7813d76e9 gcc-8.2
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195
84e7813d76e9 gcc-8.2
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196 (define_insn_reservation "nds_n9_2r1w_store_multiple_6" 1
84e7813d76e9 gcc-8.2
mir3636
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diff changeset
197 (and (match_test "nds32_register_ports_config == REG_PORT_2R1W")
84e7813d76e9 gcc-8.2
mir3636
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198 (and (eq_attr "pipeline_model" "n9")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
199 (and (eq_attr "type" "store_multiple")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
200 (eq_attr "combo" "6"))))
84e7813d76e9 gcc-8.2
mir3636
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diff changeset
201 "n9_2r1w_ii, n9_2r1w_ii+n9_2r1w_ex, n9_2r1w_ii+n9_2r1w_ex+n9_2r1w_mm, (n9_2r1w_ii+n9_2r1w_ex+n9_2r1w_mm+n9_2r1w_wb)*3, n9_2r1w_ex+n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_wb")
84e7813d76e9 gcc-8.2
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202
84e7813d76e9 gcc-8.2
mir3636
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diff changeset
203 (define_insn_reservation "nds_n9_2r1w_store_multiple_7" 1
84e7813d76e9 gcc-8.2
mir3636
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diff changeset
204 (and (match_test "nds32_register_ports_config == REG_PORT_2R1W")
84e7813d76e9 gcc-8.2
mir3636
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205 (and (eq_attr "pipeline_model" "n9")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
206 (and (eq_attr "type" "store_multiple")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
207 (eq_attr "combo" "7"))))
84e7813d76e9 gcc-8.2
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208 "n9_2r1w_ii, n9_2r1w_ii+n9_2r1w_ex, n9_2r1w_ii+n9_2r1w_ex+n9_2r1w_mm, (n9_2r1w_ii+n9_2r1w_ex+n9_2r1w_mm+n9_2r1w_wb)*4, n9_2r1w_ex+n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_wb")
84e7813d76e9 gcc-8.2
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209
84e7813d76e9 gcc-8.2
mir3636
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diff changeset
210 (define_insn_reservation "nds_n9_2r1w_store_multiple_8" 1
84e7813d76e9 gcc-8.2
mir3636
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211 (and (match_test "nds32_register_ports_config == REG_PORT_2R1W")
84e7813d76e9 gcc-8.2
mir3636
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212 (and (eq_attr "pipeline_model" "n9")
84e7813d76e9 gcc-8.2
mir3636
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213 (and (eq_attr "type" "store_multiple")
84e7813d76e9 gcc-8.2
mir3636
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diff changeset
214 (eq_attr "combo" "8"))))
84e7813d76e9 gcc-8.2
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215 "n9_2r1w_ii, n9_2r1w_ii+n9_2r1w_ex, n9_2r1w_ii+n9_2r1w_ex+n9_2r1w_mm, (n9_2r1w_ii+n9_2r1w_ex+n9_2r1w_mm+n9_2r1w_wb)*5, n9_2r1w_ex+n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_wb")
84e7813d76e9 gcc-8.2
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216
84e7813d76e9 gcc-8.2
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217 (define_insn_reservation "nds_n9_2r1w_store_multiple_12" 1
84e7813d76e9 gcc-8.2
mir3636
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218 (and (match_test "nds32_register_ports_config == REG_PORT_2R1W")
84e7813d76e9 gcc-8.2
mir3636
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219 (and (eq_attr "pipeline_model" "n9")
84e7813d76e9 gcc-8.2
mir3636
parents:
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220 (and (eq_attr "type" "store_multiple")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
221 (eq_attr "combo" "12"))))
84e7813d76e9 gcc-8.2
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222 "n9_2r1w_ii, n9_2r1w_ii+n9_2r1w_ex, n9_2r1w_ii+n9_2r1w_ex+n9_2r1w_mm, (n9_2r1w_ii+n9_2r1w_ex+n9_2r1w_mm+n9_2r1w_wb)*9, n9_2r1w_ex+n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_wb")
84e7813d76e9 gcc-8.2
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223
84e7813d76e9 gcc-8.2
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224 (define_insn_reservation "nds_n9_2r1w_mul_fast" 1
84e7813d76e9 gcc-8.2
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225 (and (match_test "nds32_register_ports_config == REG_PORT_2R1W && nds32_mul_config != MUL_TYPE_SLOW")
84e7813d76e9 gcc-8.2
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226 (and (eq_attr "type" "mul")
84e7813d76e9 gcc-8.2
mir3636
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diff changeset
227 (eq_attr "pipeline_model" "n9")))
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
228 "n9_2r1w_ii, n9_2r1w_ex, n9_2r1w_mm, n9_2r1w_wb")
84e7813d76e9 gcc-8.2
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229
84e7813d76e9 gcc-8.2
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diff changeset
230 (define_insn_reservation "nds_n9_2r1w_mul_slow" 1
84e7813d76e9 gcc-8.2
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diff changeset
231 (and (match_test "nds32_register_ports_config == REG_PORT_2R1W && nds32_mul_config == MUL_TYPE_SLOW")
84e7813d76e9 gcc-8.2
mir3636
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232 (and (eq_attr "type" "mul")
84e7813d76e9 gcc-8.2
mir3636
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diff changeset
233 (eq_attr "pipeline_model" "n9")))
84e7813d76e9 gcc-8.2
mir3636
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diff changeset
234 "n9_2r1w_ii, n9_2r1w_ex*17, n9_2r1w_mm, n9_2r1w_wb")
84e7813d76e9 gcc-8.2
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235
84e7813d76e9 gcc-8.2
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236 (define_insn_reservation "nds_n9_2r1w_mac_fast" 1
84e7813d76e9 gcc-8.2
mir3636
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diff changeset
237 (and (match_test "nds32_register_ports_config == REG_PORT_2R1W && nds32_mul_config != MUL_TYPE_SLOW")
84e7813d76e9 gcc-8.2
mir3636
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diff changeset
238 (and (eq_attr "type" "mac")
84e7813d76e9 gcc-8.2
mir3636
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diff changeset
239 (eq_attr "pipeline_model" "n9")))
84e7813d76e9 gcc-8.2
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240 "n9_2r1w_ii, n9_2r1w_ii+n9_2r1w_ex, n9_2r1w_ex+n9_2r1w_mm, n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_wb")
84e7813d76e9 gcc-8.2
mir3636
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241
84e7813d76e9 gcc-8.2
mir3636
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diff changeset
242 (define_insn_reservation "nds_n9_2r1w_mac_slow" 1
84e7813d76e9 gcc-8.2
mir3636
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diff changeset
243 (and (match_test "nds32_register_ports_config == REG_PORT_2R1W && nds32_mul_config == MUL_TYPE_SLOW")
84e7813d76e9 gcc-8.2
mir3636
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244 (and (eq_attr "type" "mac")
84e7813d76e9 gcc-8.2
mir3636
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diff changeset
245 (eq_attr "pipeline_model" "n9")))
84e7813d76e9 gcc-8.2
mir3636
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246 "n9_2r1w_ii, (n9_2r1w_ii+n9_2r1w_ex)*17, n9_2r1w_ex+n9_2r1w_mm, n9_2r1w_ex+n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_wb")
84e7813d76e9 gcc-8.2
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247
84e7813d76e9 gcc-8.2
mir3636
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248 (define_insn_reservation "nds_n9_2r1w_div" 1
84e7813d76e9 gcc-8.2
mir3636
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diff changeset
249 (and (match_test "nds32_register_ports_config == REG_PORT_2R1W")
84e7813d76e9 gcc-8.2
mir3636
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diff changeset
250 (and (eq_attr "type" "div")
84e7813d76e9 gcc-8.2
mir3636
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diff changeset
251 (eq_attr "pipeline_model" "n9")))
84e7813d76e9 gcc-8.2
mir3636
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diff changeset
252 "n9_2r1w_ii, (n9_2r1w_ii+n9_2r1w_ex)*34, n9_2r1w_ex+n9_2r1w_mm, n9_2r1w_mm+n9_2r1w_wb, n9_2r1w_wb")
84e7813d76e9 gcc-8.2
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253
84e7813d76e9 gcc-8.2
mir3636
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diff changeset
254 (define_insn_reservation "nds_n9_2r1w_branch" 1
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
255 (and (match_test "nds32_register_ports_config == REG_PORT_2R1W")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
256 (and (eq_attr "type" "branch")
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
257 (eq_attr "pipeline_model" "n9")))
84e7813d76e9 gcc-8.2
mir3636
parents:
diff changeset
258 "n9_2r1w_ii, n9_2r1w_ex, n9_2r1w_mm, n9_2r1w_wb")
84e7813d76e9 gcc-8.2
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259
84e7813d76e9 gcc-8.2
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260 ;; ------------------------------------------------------------------------
84e7813d76e9 gcc-8.2
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261 ;; Comment Notations and Bypass Rules
84e7813d76e9 gcc-8.2
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262 ;; ------------------------------------------------------------------------
84e7813d76e9 gcc-8.2
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263 ;; Producers (LHS)
84e7813d76e9 gcc-8.2
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264 ;; LD_!bi
84e7813d76e9 gcc-8.2
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265 ;; Load data from the memory (without updating the base register) and
84e7813d76e9 gcc-8.2
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266 ;; produce the loaded data. The result is ready at MM. Because the register
84e7813d76e9 gcc-8.2
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267 ;; port is 2R1W, two micro-operations are required if the base register
84e7813d76e9 gcc-8.2
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268 ;; should be updated. In this case, the base register is updated by the
84e7813d76e9 gcc-8.2
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269 ;; second micro-operation, and the updated result is ready at EX.
84e7813d76e9 gcc-8.2
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270 ;; LMW(N, M)
84e7813d76e9 gcc-8.2
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271 ;; There are N micro-operations within an instruction that loads multiple
84e7813d76e9 gcc-8.2
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272 ;; words. The result produced by the M-th micro-operation is sent to
84e7813d76e9 gcc-8.2
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273 ;; consumers. The result is ready at MM. If the base register should be
84e7813d76e9 gcc-8.2
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diff changeset
274 ;; updated, an extra micro-operation is apppended to the end of the
84e7813d76e9 gcc-8.2
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275 ;; sequence, and the result is ready at EX.
84e7813d76e9 gcc-8.2
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276 ;; MUL, MAC
84e7813d76e9 gcc-8.2
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277 ;; Compute data in the multiply-adder and produce the data. The result
84e7813d76e9 gcc-8.2
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278 ;; is ready at MM.
84e7813d76e9 gcc-8.2
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279 ;; DIV
84e7813d76e9 gcc-8.2
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280 ;; Compute data in the divider and produce the data. The result is ready
84e7813d76e9 gcc-8.2
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281 ;; at MM.
84e7813d76e9 gcc-8.2
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282 ;;
84e7813d76e9 gcc-8.2
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283 ;; Consumers (RHS)
84e7813d76e9 gcc-8.2
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284 ;; ALU, PBSAD, PBSADA_RaRb, MUL, MAC, DIV, MMU
84e7813d76e9 gcc-8.2
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285 ;; Require operands at EX.
84e7813d76e9 gcc-8.2
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286 ;; ALU_SHIFT_Rb
84e7813d76e9 gcc-8.2
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287 ;; An ALU-SHIFT instruction consists of a shift micro-operation followed
84e7813d76e9 gcc-8.2
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288 ;; by an arithmetic micro-operation. The operand Rb is used by the first
84e7813d76e9 gcc-8.2
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289 ;; micro-operation, and there are some latencies if data dependency occurs.
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290 ;; MOVD44_E
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291 ;; A double-word move instruction needs two micro-operations because the
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292 ;; reigster ports is 2R1W. The first micro-operation writes an even number
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293 ;; register, and the second micro-operation writes an odd number register.
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294 ;; Each input operand is required at EX for each micro-operation. MOVD44_E
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295 ;; stands for the first micro-operation.
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296 ;; MAC_RaRb, M2R
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297 ;; MAC instructions do multiplication at EX and do accumulation at MM, but
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298 ;; MAC instructions which operate on general purpose registers always
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299 ;; require operands at EX because MM stage cannot be forwarded in 2R1W mode.
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300 ;; ADDR_IN
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301 ;; If an instruction requires an address as its input operand, the address
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302 ;; is required at EX.
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303 ;; ST_bi
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304 ;; A post-increment store instruction requires its data at EX because MM
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305 ;; cannot be forwarded in 2R1W mode.
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306 ;; ST_!bi_RI
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307 ;; A store instruction with an immediate offset requires its data at EX
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308 ;; because MM cannot be forwarded in 2R1W mode. If the offset field is a
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309 ;; register (ST_!bi_RR), the instruction will be separated into two micro-
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310 ;; operations, and the second one requires the input operand at EX in order
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311 ;; to store it to the memory.
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312 ;; SMW(N, M)
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313 ;; There are N micro-operations within an instruction that stores multiple
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314 ;; words. Each M-th micro-operation requires its data at MM.
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315 ;; BR
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316 ;; If a branch instruction is conditional, its input data is required at EX.
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317
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318 ;; LD_!bi, MUL, MAC
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319 ;; -> ALU, ALU_SHIFT_Rb, PBSAD, PBSADA_RaRb, MOVD44_E, MUL, MAC_RaRb, M2R, DIV, ADDR_IN_!bi, ADDR_IN_bi_Ra, ST_bi, ST_!bi_RI, BR, MMU
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320 (define_bypass 2
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321 "nds_n9_2r1w_load,\
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322 nds_n9_2r1w_mul_fast, nds_n9_2r1w_mul_slow,\
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323 nds_n9_2r1w_mac_fast, nds_n9_2r1w_mac_slow"
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324 "nds_n9_2r1w_alu, nds_n9_2r1w_alu_shift,\
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325 nds_n9_2r1w_pbsad, nds_n9_2r1w_pbsada,\
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326 nds_n9_2r1w_mul_fast, nds_n9_2r1w_mul_slow,\
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327 nds_n9_2r1w_mac_fast, nds_n9_2r1w_mac_slow,\
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328 nds_n9_2r1w_branch,\
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329 nds_n9_2r1w_div,\
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330 nds_n9_2r1w_load,nds_n9_2r1w_store,\
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331 nds_n9_2r1w_load_multiple_1,nds_n9_2r1w_load_multiple_2, nds_n9_2r1w_load_multiple_3,\
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332 nds_n9_2r1w_load_multiple_4,nds_n9_2r1w_load_multiple_5, nds_n9_2r1w_load_multiple_6,\
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333 nds_n9_2r1w_load_multiple_7,nds_n9_2r1w_load_multiple_8, nds_n9_2r1w_load_multiple_12,\
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334 nds_n9_2r1w_store_multiple_1,nds_n9_2r1w_store_multiple_2, nds_n9_2r1w_store_multiple_3,\
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335 nds_n9_2r1w_store_multiple_4,nds_n9_2r1w_store_multiple_5, nds_n9_2r1w_store_multiple_6,\
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336 nds_n9_2r1w_store_multiple_7,nds_n9_2r1w_store_multiple_8, nds_n9_2r1w_store_multiple_12,\
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337 nds_n9_2r1w_mmu"
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338 "nds32_n9_2r1w_mm_to_ex_p"
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339 )
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340
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341 ;; LMW(N, N)
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342 ;; -> ALU, ALU_SHIFT_Rb, PBSAD, PBSADA_RaRb, MOVD44_E, MUL, MAC_RaRb, M2R, DIV, ADDR_IN_!bi, ADDR_IN_bi_Ra, ST_bi, ST_!bi_RI, BR, MMU
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343 (define_bypass 2
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344 "nds_n9_2r1w_load_multiple_1,nds_n9_2r1w_load_multiple_2, nds_n9_2r1w_load_multiple_3,\
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345 nds_n9_2r1w_load_multiple_4,nds_n9_2r1w_load_multiple_5, nds_n9_2r1w_load_multiple_6,\
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346 nds_n9_2r1w_load_multiple_7,nds_n9_2r1w_load_multiple_8, nds_n9_2r1w_load_multiple_12"
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347 "nds_n9_2r1w_alu, nds_n9_2r1w_alu_shift,\
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348 nds_n9_2r1w_pbsad, nds_n9_2r1w_pbsada,\
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349 nds_n9_2r1w_mul_fast, nds_n9_2r1w_mul_slow,\
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350 nds_n9_2r1w_mac_fast, nds_n9_2r1w_mac_slow,\
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351 nds_n9_2r1w_branch,\
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352 nds_n9_2r1w_div,\
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353 nds_n9_2r1w_load,nds_n9_2r1w_store,\
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354 nds_n9_2r1w_load_multiple_1,nds_n9_2r1w_load_multiple_2, nds_n9_2r1w_load_multiple_3,\
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355 nds_n9_2r1w_load_multiple_4,nds_n9_2r1w_load_multiple_5, nds_n9_2r1w_load_multiple_6,\
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356 nds_n9_2r1w_load_multiple_7,nds_n9_2r1w_load_multiple_8, nds_n9_2r1w_load_multiple_12,\
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357 nds_n9_2r1w_store_multiple_1,nds_n9_2r1w_store_multiple_2, nds_n9_2r1w_store_multiple_3,\
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358 nds_n9_2r1w_store_multiple_4,nds_n9_2r1w_store_multiple_5, nds_n9_2r1w_store_multiple_6,\
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359 nds_n9_2r1w_store_multiple_7,nds_n9_2r1w_store_multiple_8, nds_n9_2r1w_store_multiple_12,\
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360 nds_n9_2r1w_mmu"
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361 "nds32_n9_last_load_to_ex_p"
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362 )