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131
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1 /* relax-opt pass of Andes NDS32 cpu for GNU compiler
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2 Copyright (C) 2012-2018 Free Software Foundation, Inc.
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3 Contributed by Andes Technology Corporation.
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4
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5 This file is part of GCC.
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6
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7 GCC is free software; you can redistribute it and/or modify it
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8 under the terms of the GNU General Public License as published
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9 by the Free Software Foundation; either version 3, or (at your
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10 option) any later version.
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11
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12 GCC is distributed in the hope that it will be useful, but WITHOUT
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13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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15 License for more details.
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16
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17 You should have received a copy of the GNU General Public License
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18 along with GCC; see the file COPYING3. If not see
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19 <http://www.gnu.org/licenses/>. */
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20
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21 /* ------------------------------------------------------------------------ */
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22
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23 #define IN_TARGET_CODE 1
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24
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25 #include "config.h"
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26 #include "system.h"
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27 #include "coretypes.h"
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28 #include "backend.h"
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29 #include "target.h"
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30 #include "rtl.h"
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31 #include "tree.h"
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32 #include "stringpool.h"
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33 #include "attribs.h"
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34 #include "df.h"
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35 #include "memmodel.h"
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36 #include "tm_p.h"
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37 #include "optabs.h" /* For GEN_FCN. */
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38 #include "regs.h"
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39 #include "emit-rtl.h"
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40 #include "recog.h"
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41 #include "diagnostic-core.h"
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42 #include "stor-layout.h"
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43 #include "varasm.h"
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44 #include "calls.h"
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45 #include "output.h"
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46 #include "explow.h"
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47 #include "expr.h"
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48 #include "tm-constrs.h"
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49 #include "builtins.h"
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50 #include "cpplib.h"
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51 #include "insn-attr.h"
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52 #include "cfgrtl.h"
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53 #include "tree-pass.h"
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54
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55 using namespace nds32;
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56
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57 /* This is used to create unique relax hint id value.
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58 The initial value is 0. */
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59 static int relax_group_id = 0;
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60
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61 /* Group the following pattern as relax candidates:
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62
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63 1. sethi $ra, hi20(sym)
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64 ori $ra, $ra, lo12(sym)
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65 ==>
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66 addi.gp $ra, sym
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67
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68 2. sethi $ra, hi20(sym)
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69 lwi $rb, [$ra + lo12(sym)]
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70 ==>
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71 lwi.gp $rb, [(sym)]
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72
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73 3. sethi $ra, hi20(sym)
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74 ori $ra, $ra, lo12(sym)
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75 lwi $rb, [$ra]
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76 swi $rc, [$ra]
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77 ==>
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78 lwi37 $rb, [(sym)]
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79 swi37 $rc, [(sym)] */
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80
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81 /* Return true if is load/store with REG addressing mode
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82 and memory mode is SImode. */
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83 static bool
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84 nds32_reg_base_load_store_p (rtx_insn *insn)
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85 {
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86 rtx mem_src = NULL_RTX;
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87
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88 switch (get_attr_type (insn))
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89 {
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90 case TYPE_LOAD:
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91 mem_src = SET_SRC (PATTERN (insn));
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92 break;
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93 case TYPE_STORE:
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94 mem_src = SET_DEST (PATTERN (insn));
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95 break;
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96 default:
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97 break;
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98 }
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99
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100 /* Find load/store insn with addressing mode is REG. */
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101 if (mem_src != NULL_RTX)
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102 {
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103 if ((GET_CODE (mem_src) == ZERO_EXTEND)
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104 || (GET_CODE (mem_src) == SIGN_EXTEND))
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105 mem_src = XEXP (mem_src, 0);
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106
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107 if (GET_CODE (XEXP (mem_src, 0)) == REG)
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108 return true;
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109 }
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110
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111 return false;
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112 }
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113
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114 /* Return true if insn is a sp/fp base or sp/fp plus load-store instruction. */
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115
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116 static bool
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117 nds32_sp_base_or_plus_load_store_p (rtx_insn *insn)
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118 {
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119 rtx mem_src = NULL_RTX;
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120
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121 switch (get_attr_type (insn))
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122 {
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123 case TYPE_LOAD:
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124 mem_src = SET_SRC (PATTERN (insn));
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125 break;
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126 case TYPE_STORE:
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127 mem_src = SET_DEST (PATTERN (insn));
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128 break;
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129 default:
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130 break;
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131 }
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132 /* Find load/store insn with addressing mode is REG. */
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133 if (mem_src != NULL_RTX)
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134 {
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135 if ((GET_CODE (mem_src) == ZERO_EXTEND)
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136 || (GET_CODE (mem_src) == SIGN_EXTEND))
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137 mem_src = XEXP (mem_src, 0);
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138
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139 if ((GET_CODE (XEXP (mem_src, 0)) == PLUS))
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140 mem_src = XEXP (mem_src, 0);
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141
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142 if (REG_P (XEXP (mem_src, 0))
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143 && ((frame_pointer_needed
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144 && REGNO (XEXP (mem_src, 0)) == FP_REGNUM)
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145 || REGNO (XEXP (mem_src, 0)) == SP_REGNUM))
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146 return true;
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147 }
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148
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149 return false;
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150 }
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151
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152 /* Return true if is load with [REG + REG/CONST_INT] addressing mode. */
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153 static bool
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154 nds32_plus_reg_load_store_p (rtx_insn *insn)
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155 {
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156 rtx mem_src = NULL_RTX;
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157
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158 switch (get_attr_type (insn))
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159 {
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160 case TYPE_LOAD:
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161 mem_src = SET_SRC (PATTERN (insn));
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162 break;
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163 case TYPE_STORE:
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164 mem_src = SET_DEST (PATTERN (insn));
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165 break;
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166 default:
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167 break;
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168 }
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169
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170 /* Find load/store insn with addressing mode is [REG + REG/CONST]. */
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171 if (mem_src != NULL_RTX)
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172 {
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173 if ((GET_CODE (mem_src) == ZERO_EXTEND)
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174 || (GET_CODE (mem_src) == SIGN_EXTEND))
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175 mem_src = XEXP (mem_src, 0);
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176
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177 if ((GET_CODE (XEXP (mem_src, 0)) == PLUS))
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178 mem_src = XEXP (mem_src, 0);
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179 else
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180 return false;
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181
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182 if (GET_CODE (XEXP (mem_src, 0)) == REG)
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183 return true;
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184
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185 }
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186
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187 return false;
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188 }
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189
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190 /* Return true if x is const and the referance is ict symbol. */
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191 static bool
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192 nds32_ict_const_p (rtx x)
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193 {
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194 if (GET_CODE (x) == CONST)
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195 {
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196 x = XEXP (x, 0);
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197 return nds32_indirect_call_referenced_p (x);
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198 }
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199 return FALSE;
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200 }
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201
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202 /* Group the following pattern as relax candidates:
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203
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204 GOT:
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205 sethi $ra, hi20(sym)
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206 ori $ra, $ra, lo12(sym)
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207 lw $rb, [$ra + $gp]
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208
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209 GOTOFF, TLSLE:
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210 sethi $ra, hi20(sym)
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211 ori $ra, $ra, lo12(sym)
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212 LS $rb, [$ra + $gp]
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213
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214 GOTOFF, TLSLE:
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215 sethi $ra, hi20(sym)
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216 ori $ra, $ra, lo12(sym)
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217 add $rb, $ra, $gp($tp)
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218
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219 Initial GOT table:
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220 sethi $gp,hi20(sym)
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221 ori $gp, $gp, lo12(sym)
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222 add5.pc $gp */
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223
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224 static auto_vec<rtx_insn *, 32> nds32_group_infos;
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225 /* Group the PIC and TLS relax candidate instructions for linker. */
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226 static bool
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227 nds32_pic_tls_group (rtx_insn *def_insn,
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228 enum nds32_relax_insn_type relax_type,
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229 int sym_type)
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230 {
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231 df_ref def_record;
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232 df_link *link;
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233 rtx_insn *use_insn = NULL;
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234 rtx pat, new_pat;
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235 def_record = DF_INSN_DEFS (def_insn);
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236 for (link = DF_REF_CHAIN (def_record); link; link = link->next)
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237 {
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238 if (!DF_REF_INSN_INFO (link->ref))
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239 continue;
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240
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241 use_insn = DF_REF_INSN (link->ref);
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242
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243 /* Skip if define insn and use insn not in the same basic block. */
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244 if (!dominated_by_p (CDI_DOMINATORS,
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245 BLOCK_FOR_INSN (use_insn),
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246 BLOCK_FOR_INSN (def_insn)))
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247 return FALSE;
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248
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249 /* Skip if use_insn not active insn. */
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250 if (!active_insn_p (use_insn))
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251 return FALSE;
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252
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253 switch (relax_type)
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254 {
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255 case RELAX_ORI:
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256
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257 /* GOTOFF, TLSLE:
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258 sethi $ra, hi20(sym)
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259 ori $ra, $ra, lo12(sym)
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260 add $rb, $ra, $gp($tp) */
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261 if ((sym_type == UNSPEC_TLSLE
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262 || sym_type == UNSPEC_GOTOFF)
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263 && (recog_memoized (use_insn) == CODE_FOR_addsi3))
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264 {
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265 pat = XEXP (PATTERN (use_insn), 1);
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266 new_pat =
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267 gen_rtx_UNSPEC (SImode,
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268 gen_rtvec (2, XEXP (pat, 0), XEXP (pat, 1)),
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269 UNSPEC_ADD32);
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270 validate_replace_rtx (pat, new_pat, use_insn);
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271 nds32_group_infos.safe_push (use_insn);
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272 }
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273 else if (nds32_plus_reg_load_store_p (use_insn)
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274 && !nds32_sp_base_or_plus_load_store_p (use_insn))
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275 nds32_group_infos.safe_push (use_insn);
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276 else
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277 return FALSE;
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278 break;
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279
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280 default:
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281 return FALSE;
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282 }
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283 }
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284 return TRUE;
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285 }
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286
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287 static int
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288 nds32_pic_tls_symbol_type (rtx x)
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289 {
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290 x = XEXP (SET_SRC (PATTERN (x)), 1);
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291
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292 if (GET_CODE (x) == CONST)
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293 {
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294 x = XEXP (x, 0);
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295
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296 if (GET_CODE (x) == PLUS)
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297 x = XEXP (x, 0);
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298
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299 return XINT (x, 1);
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300 }
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301
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302 return XINT (x, 1);
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303 }
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304
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305 /* Group the relax candidates with group id. */
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306 static void
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307 nds32_group_insns (rtx_insn *sethi)
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308 {
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309 df_ref def_record, use_record;
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310 df_link *link;
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311 rtx_insn *use_insn = NULL;
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312 rtx group_id;
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313 bool valid;
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314
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315 def_record = DF_INSN_DEFS (sethi);
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316
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317 for (link = DF_REF_CHAIN (def_record); link; link = link->next)
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318 {
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319 if (!DF_REF_INSN_INFO (link->ref))
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320 continue;
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321
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322 use_insn = DF_REF_INSN (link->ref);
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323
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324 /* Skip if define insn and use insn not in the same basic block. */
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325 if (!dominated_by_p (CDI_DOMINATORS,
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326 BLOCK_FOR_INSN (use_insn),
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327 BLOCK_FOR_INSN (sethi)))
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328 return;
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329
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330 /* Skip if the low-part used register is from different high-part
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331 instructions. */
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332 use_record = DF_INSN_USES (use_insn);
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333 if (DF_REF_CHAIN (use_record) && DF_REF_CHAIN (use_record)->next)
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334 return;
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335
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336 /* Skip if use_insn not active insn. */
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337 if (!active_insn_p (use_insn))
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338 return;
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339
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340 /* Initial use_insn_type. */
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341 if (!(recog_memoized (use_insn) == CODE_FOR_lo_sum
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342 || nds32_symbol_load_store_p (use_insn)
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343 || (nds32_reg_base_load_store_p (use_insn)
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344 &&!nds32_sp_base_or_plus_load_store_p (use_insn))))
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345 return;
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346 }
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347
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348 group_id = GEN_INT (relax_group_id);
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349 /* Insert .relax_* directive for sethi. */
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350 emit_insn_before (gen_relax_group (group_id), sethi);
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351
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352 /* Scan the use insns and insert the directive. */
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353 for (link = DF_REF_CHAIN (def_record); link; link = link->next)
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354 {
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355 if (!DF_REF_INSN_INFO (link->ref))
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356 continue;
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357
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358 use_insn = DF_REF_INSN (link->ref);
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359
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360 /* Insert .relax_* directive. */
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361 if (active_insn_p (use_insn))
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362 emit_insn_before (gen_relax_group (group_id), use_insn);
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363
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364 /* Find ori ra, ra, unspec(symbol) instruction. */
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365 if (use_insn != NULL
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366 && recog_memoized (use_insn) == CODE_FOR_lo_sum
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367 && !nds32_const_unspec_p (XEXP (SET_SRC (PATTERN (use_insn)), 1)))
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368 {
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369 int sym_type = nds32_pic_tls_symbol_type (use_insn);
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370 valid = nds32_pic_tls_group (use_insn, RELAX_ORI, sym_type);
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371
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372 /* Insert .relax_* directive. */
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373 while (!nds32_group_infos.is_empty ())
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374 {
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375 use_insn = nds32_group_infos.pop ();
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376 if (valid)
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377 emit_insn_before (gen_relax_group (group_id), use_insn);
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378 }
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379 }
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380 }
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381
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382 relax_group_id++;
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383 }
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384
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385 /* Convert relax group id in rtl. */
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386
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387 static void
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388 nds32_group_tls_insn (rtx insn)
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389 {
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390 rtx pat = PATTERN (insn);
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391 rtx unspec_relax_group = XEXP (XVECEXP (pat, 0, 1), 0);
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392
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393 while (GET_CODE (pat) != SET && GET_CODE (pat) == PARALLEL)
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394 {
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395 pat = XVECEXP (pat, 0, 0);
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396 }
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397
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398 if (GET_CODE (unspec_relax_group) == UNSPEC
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399 && XINT (unspec_relax_group, 1) == UNSPEC_VOLATILE_RELAX_GROUP)
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400 {
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401 XVECEXP (unspec_relax_group, 0, 0) = GEN_INT (relax_group_id);
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402 }
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403
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404 relax_group_id++;
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405 }
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406
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407 static bool
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408 nds32_float_reg_load_store_p (rtx_insn *insn)
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409 {
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410 rtx pat = PATTERN (insn);
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411
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412 if (get_attr_type (insn) == TYPE_FLOAD
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413 && GET_CODE (pat) == SET
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414 && (GET_MODE (XEXP (pat, 0)) == SFmode
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415 || GET_MODE (XEXP (pat, 0)) == DFmode)
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416 && MEM_P (XEXP (pat, 1)))
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417 {
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418 rtx addr = XEXP (XEXP (pat, 1), 0);
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419
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420 /* [$ra] */
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421 if (REG_P (addr))
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422 return true;
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423 /* [$ra + offset] */
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424 if (GET_CODE (addr) == PLUS
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425 && REG_P (XEXP (addr, 0))
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426 && CONST_INT_P (XEXP (addr, 1)))
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427 return true;
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428 }
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429 return false;
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430 }
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431
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432
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433 /* Group float load-store instructions:
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434 la $ra, symbol
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435 flsi $rt, [$ra + offset] */
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436
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437 static void
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|
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438 nds32_group_float_insns (rtx_insn *insn)
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439 {
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|
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440 df_ref def_record, use_record;
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441 df_link *link;
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|
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442 rtx_insn *use_insn = NULL;
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443 rtx group_id;
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444
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445 def_record = DF_INSN_DEFS (insn);
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446
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|
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447 for (link = DF_REF_CHAIN (def_record); link; link = link->next)
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448 {
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449 if (!DF_REF_INSN_INFO (link->ref))
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450 continue;
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|
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451
|
|
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452 use_insn = DF_REF_INSN (link->ref);
|
|
|
453
|
|
|
454 /* Skip if define insn and use insn not in the same basic block. */
|
|
|
455 if (!dominated_by_p (CDI_DOMINATORS,
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|
|
456 BLOCK_FOR_INSN (use_insn),
|
|
|
457 BLOCK_FOR_INSN (insn)))
|
|
|
458 return;
|
|
|
459
|
|
|
460 /* Skip if the low-part used register is from different high-part
|
|
|
461 instructions. */
|
|
|
462 use_record = DF_INSN_USES (use_insn);
|
|
|
463 if (DF_REF_CHAIN (use_record) && DF_REF_CHAIN (use_record)->next)
|
|
|
464 return;
|
|
|
465
|
|
|
466 /* Skip if use_insn not active insn. */
|
|
|
467 if (!active_insn_p (use_insn))
|
|
|
468 return;
|
|
|
469
|
|
|
470 if (!nds32_float_reg_load_store_p (use_insn)
|
|
|
471 || find_post_update_rtx (use_insn) != -1)
|
|
|
472 return;
|
|
|
473 }
|
|
|
474
|
|
|
475 group_id = GEN_INT (relax_group_id);
|
|
|
476 /* Insert .relax_* directive for insn. */
|
|
|
477 emit_insn_before (gen_relax_group (group_id), insn);
|
|
|
478
|
|
|
479 /* Scan the use insns and insert the directive. */
|
|
|
480 for (link = DF_REF_CHAIN (def_record); link; link = link->next)
|
|
|
481 {
|
|
|
482 if (!DF_REF_INSN_INFO (link->ref))
|
|
|
483 continue;
|
|
|
484
|
|
|
485 use_insn = DF_REF_INSN (link->ref);
|
|
|
486
|
|
|
487 /* Insert .relax_* directive. */
|
|
|
488 emit_insn_before (gen_relax_group (group_id), use_insn);
|
|
|
489 }
|
|
|
490
|
|
|
491 relax_group_id++;
|
|
|
492 }
|
|
|
493
|
|
|
494 /* Group the relax candidate instructions for linker. */
|
|
|
495 static void
|
|
|
496 nds32_relax_group (void)
|
|
|
497 {
|
|
|
498 rtx_insn *insn;
|
|
|
499
|
|
|
500 compute_bb_for_insn ();
|
|
|
501
|
|
|
502 df_chain_add_problem (DF_DU_CHAIN | DF_UD_CHAIN);
|
|
|
503 df_insn_rescan_all ();
|
|
|
504 df_analyze ();
|
|
|
505 df_set_flags (DF_DEFER_INSN_RESCAN);
|
|
|
506 calculate_dominance_info (CDI_DOMINATORS);
|
|
|
507
|
|
|
508 insn = get_insns ();
|
|
|
509 gcc_assert (NOTE_P (insn));
|
|
|
510
|
|
|
511 for (insn = next_active_insn (insn); insn; insn = next_active_insn (insn))
|
|
|
512 {
|
|
|
513 if (NONJUMP_INSN_P (insn))
|
|
|
514 {
|
|
|
515 /* Find sethi ra, symbol instruction. */
|
|
|
516 if (recog_memoized (insn) == CODE_FOR_sethi
|
|
|
517 && nds32_symbolic_operand (XEXP (SET_SRC (PATTERN (insn)), 0),
|
|
|
518 SImode)
|
|
|
519 && !nds32_ict_const_p (XEXP (SET_SRC (PATTERN (insn)), 0)))
|
|
|
520 nds32_group_insns (insn);
|
|
|
521 else if (recog_memoized (insn) == CODE_FOR_tls_ie)
|
|
|
522 nds32_group_tls_insn (insn);
|
|
|
523 else if (TARGET_FPU_SINGLE
|
|
|
524 && recog_memoized (insn) == CODE_FOR_move_addr
|
|
|
525 && !nds32_ict_const_p (XEXP (SET_SRC (PATTERN (insn)), 0)))
|
|
|
526 {
|
|
|
527 nds32_group_float_insns (insn);
|
|
|
528 }
|
|
|
529 }
|
|
|
530 else if (CALL_P (insn) && recog_memoized (insn) == CODE_FOR_tls_desc)
|
|
|
531 {
|
|
|
532 nds32_group_tls_insn (insn);
|
|
|
533 }
|
|
|
534 }
|
|
|
535
|
|
|
536 /* We must call df_finish_pass manually because it should be invoked before
|
|
|
537 BB information is destroyed. Hence we cannot set the TODO_df_finish flag
|
|
|
538 to the pass manager. */
|
|
|
539 df_insn_rescan_all ();
|
|
|
540 df_finish_pass (false);
|
|
|
541 free_dominance_info (CDI_DOMINATORS);
|
|
|
542 }
|
|
|
543
|
|
|
544 static unsigned int
|
|
|
545 nds32_relax_opt (void)
|
|
|
546 {
|
|
|
547 if (TARGET_RELAX_HINT)
|
|
|
548 nds32_relax_group ();
|
|
|
549 return 1;
|
|
|
550 }
|
|
|
551
|
|
|
552 const pass_data pass_data_nds32_relax_opt =
|
|
|
553 {
|
|
|
554 RTL_PASS, /* type */
|
|
|
555 "relax_opt", /* name */
|
|
|
556 OPTGROUP_NONE, /* optinfo_flags */
|
|
|
557 TV_MACH_DEP, /* tv_id */
|
|
|
558 0, /* properties_required */
|
|
|
559 0, /* properties_provided */
|
|
|
560 0, /* properties_destroyed */
|
|
|
561 0, /* todo_flags_start */
|
|
|
562 TODO_df_finish, /* todo_flags_finish */
|
|
|
563 };
|
|
|
564
|
|
|
565 class pass_nds32_relax_opt : public rtl_opt_pass
|
|
|
566 {
|
|
|
567 public:
|
|
|
568 pass_nds32_relax_opt (gcc::context *ctxt)
|
|
|
569 : rtl_opt_pass (pass_data_nds32_relax_opt, ctxt)
|
|
|
570 {}
|
|
|
571
|
|
|
572 /* opt_pass methods: */
|
|
|
573 bool gate (function *) { return TARGET_RELAX_HINT; }
|
|
|
574 unsigned int execute (function *) { return nds32_relax_opt (); }
|
|
|
575 };
|
|
|
576
|
|
|
577 rtl_opt_pass *
|
|
|
578 make_pass_nds32_relax_opt (gcc::context *ctxt)
|
|
|
579 {
|
|
|
580 return new pass_nds32_relax_opt (ctxt);
|
|
|
581 }
|
