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131
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1 /* Auxiliary functions for pipeline descriptions pattern of Andes
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2 NDS32 cpu for GNU compiler
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3 Copyright (C) 2012-2018 Free Software Foundation, Inc.
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4 Contributed by Andes Technology Corporation.
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5
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6 This file is part of GCC.
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7
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8 GCC is free software; you can redistribute it and/or modify it
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9 under the terms of the GNU General Public License as published
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10 by the Free Software Foundation; either version 3, or (at your
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11 option) any later version.
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12
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13 GCC is distributed in the hope that it will be useful, but WITHOUT
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14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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16 License for more details.
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17
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18 You should have received a copy of the GNU General Public License
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19 along with GCC; see the file COPYING3. If not see
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20 <http://www.gnu.org/licenses/>. */
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21
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22 /* ------------------------------------------------------------------------ */
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23
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24 #define IN_TARGET_CODE 1
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25
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26 #include "config.h"
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27 #include "system.h"
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28 #include "coretypes.h"
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29 #include "backend.h"
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30 #include "target.h"
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31 #include "rtl.h"
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32 #include "tree.h"
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33 #include "memmodel.h"
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34 #include "tm_p.h"
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35 #include "optabs.h" /* For GEN_FCN. */
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36 #include "recog.h"
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37 #include "tm-constrs.h"
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38 #include "insn-attr.h"
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39
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40
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41 namespace nds32 {
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42
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43 /* Get the rtx in the PATTERN field of an insn. If INSN is not an insn,
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44 the funciton doesn't change anything and returns it directly. */
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45 rtx
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46 extract_pattern_from_insn (rtx insn)
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47 {
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48 if (INSN_P (insn))
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49 return PATTERN (insn);
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50
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51 return insn;
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52 }
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53
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54 /* Get the number of elements in a parallel rtx. */
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55 size_t
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56 parallel_elements (rtx parallel_rtx)
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57 {
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58 parallel_rtx = extract_pattern_from_insn (parallel_rtx);
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59 gcc_assert (GET_CODE (parallel_rtx) == PARALLEL);
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60
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61 return XVECLEN (parallel_rtx, 0);
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62 }
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63
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64 /* Extract an rtx from a parallel rtx with index NTH. If NTH is a negative
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65 value, the function returns the last NTH rtx. */
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66 rtx
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67 parallel_element (rtx parallel_rtx, int nth)
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68 {
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69 parallel_rtx = extract_pattern_from_insn (parallel_rtx);
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70 gcc_assert (GET_CODE (parallel_rtx) == PARALLEL);
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71
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72 int len = parallel_elements (parallel_rtx);
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73
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74 if (nth >= 0)
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75 {
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76 if (nth >= len)
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77 return NULL_RTX;
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78
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79 return XVECEXP (parallel_rtx, 0, nth);
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80 }
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81 else
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82 {
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83 if (len + nth < 0)
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84 return NULL_RTX;
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85
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86 return XVECEXP (parallel_rtx, 0, len + nth);
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87 }
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88 }
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89
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90 /* Functions to determine whether INSN is single-word, double-word
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91 or partial-word load/store insn. */
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92
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93 bool
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94 load_single_p (rtx_insn *insn)
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95 {
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96 if (get_attr_type (insn) != TYPE_LOAD)
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97 return false;
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98
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99 if (INSN_CODE (insn) == CODE_FOR_move_di ||
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100 INSN_CODE (insn) == CODE_FOR_move_df)
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101 return false;
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102
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103 return true;
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104 }
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105
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106 bool
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107 store_single_p (rtx_insn *insn)
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108 {
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109 if (get_attr_type (insn) != TYPE_STORE)
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110 return false;
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111
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112 if (INSN_CODE (insn) == CODE_FOR_move_di ||
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113 INSN_CODE (insn) == CODE_FOR_move_df)
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114 return false;
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115
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116 return true;
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117 }
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118
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119 bool
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120 load_double_p (rtx_insn *insn)
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121 {
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122 if (get_attr_type (insn) != TYPE_LOAD)
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123 return false;
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124
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125 if (INSN_CODE (insn) != CODE_FOR_move_di &&
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126 INSN_CODE (insn) != CODE_FOR_move_df)
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127 return false;
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128
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129 return true;
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130 }
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131
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132 bool
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133 store_double_p (rtx_insn *insn)
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134 {
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135 if (get_attr_type (insn) != TYPE_STORE)
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136 return false;
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137
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138 if (INSN_CODE (insn) != CODE_FOR_move_di &&
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139 INSN_CODE (insn) != CODE_FOR_move_df)
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140 return false;
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141
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142 return true;
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143 }
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144
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145 bool
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146 store_offset_reg_p (rtx_insn *insn)
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147 {
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148 if (get_attr_type (insn) != TYPE_STORE)
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149 return false;
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150
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151 rtx offset_rtx = extract_offset_rtx (insn);
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152
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153 if (offset_rtx == NULL_RTX)
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154 return false;
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155
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156 if (REG_P (offset_rtx))
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157 return true;
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158
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159 return false;
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160 }
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161
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162 /* Determine if INSN is a post update insn. */
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163 bool
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164 post_update_insn_p (rtx_insn *insn)
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165 {
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166 if (find_post_update_rtx (insn) == -1)
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167 return false;
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168 else
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169 return true;
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170 }
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171
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172 /* Check if the address of MEM_RTX consists of a base register and an
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173 immediate offset. */
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174 bool
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175 immed_offset_p (rtx mem_rtx)
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176 {
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177 gcc_assert (MEM_P (mem_rtx));
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178
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179 rtx addr_rtx = XEXP (mem_rtx, 0);
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180
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181 /* (mem (reg)) is equivalent to (mem (plus (reg) (const_int 0))) */
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182 if (REG_P (addr_rtx))
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183 return true;
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184
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185 /* (mem (plus (reg) (const_int))) */
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186 if (GET_CODE (addr_rtx) == PLUS
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187 && GET_CODE (XEXP (addr_rtx, 1)) == CONST_INT)
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188 return true;
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189
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190 return false;
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191 }
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192
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193 /* Find the post update rtx in INSN. If INSN is a load/store multiple insn,
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194 the function returns the vector index of its parallel part. If INSN is a
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195 single load/store insn, the function returns 0. If INSN is not a post-
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196 update insn, the function returns -1. */
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197 int
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198 find_post_update_rtx (rtx_insn *insn)
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199 {
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200 rtx mem_rtx;
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201 int i, len;
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202
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203 switch (get_attr_type (insn))
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204 {
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205 case TYPE_LOAD_MULTIPLE:
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206 case TYPE_STORE_MULTIPLE:
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207 /* Find a pattern in a parallel rtx:
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208 (set (reg) (plus (reg) (const_int))) */
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209 len = parallel_elements (insn);
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210 for (i = 0; i < len; ++i)
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211 {
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212 rtx curr_insn = parallel_element (insn, i);
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213
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214 if (GET_CODE (curr_insn) == SET
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215 && REG_P (SET_DEST (curr_insn))
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216 && GET_CODE (SET_SRC (curr_insn)) == PLUS)
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217 return i;
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218 }
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219 return -1;
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220
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221 case TYPE_LOAD:
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222 case TYPE_FLOAD:
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223 case TYPE_STORE:
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224 case TYPE_FSTORE:
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225 mem_rtx = extract_mem_rtx (insn);
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226 /* (mem (post_inc (reg))) */
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227 switch (GET_CODE (XEXP (mem_rtx, 0)))
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228 {
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229 case POST_INC:
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230 case POST_DEC:
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231 case POST_MODIFY:
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232 return 0;
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233
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234 default:
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235 return -1;
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236 }
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237
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238 default:
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239 gcc_unreachable ();
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240 }
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241 }
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242
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243 /* Extract the MEM rtx from a load/store insn. */
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244 rtx
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245 extract_mem_rtx (rtx_insn *insn)
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246 {
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247 rtx body = PATTERN (insn);
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248
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249 switch (get_attr_type (insn))
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250 {
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251 case TYPE_LOAD:
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252 case TYPE_FLOAD:
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253 if (MEM_P (SET_SRC (body)))
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254 return SET_SRC (body);
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255
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256 /* unaligned address: (unspec [(mem)]) */
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257 if (GET_CODE (SET_SRC (body)) == UNSPEC)
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258 {
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259 gcc_assert (MEM_P (XVECEXP (SET_SRC (body), 0, 0)));
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260 return XVECEXP (SET_SRC (body), 0, 0);
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261 }
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262
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263 /* (sign_extend (mem)) */
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264 gcc_assert (MEM_P (XEXP (SET_SRC (body), 0)));
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265 return XEXP (SET_SRC (body), 0);
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266
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267 case TYPE_STORE:
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268 case TYPE_FSTORE:
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269 if (MEM_P (SET_DEST (body)))
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270 return SET_DEST (body);
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271
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272 /* unaligned address: (unspec [(mem)]) */
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273 if (GET_CODE (SET_DEST (body)) == UNSPEC)
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274 {
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275 gcc_assert (MEM_P (XVECEXP (SET_DEST (body), 0, 0)));
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276 return XVECEXP (SET_DEST (body), 0, 0);
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277 }
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278
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279 /* (sign_extend (mem)) */
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280 gcc_assert (MEM_P (XEXP (SET_DEST (body), 0)));
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281 return XEXP (SET_DEST (body), 0);
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282
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283 default:
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284 gcc_unreachable ();
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285 }
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286 }
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287
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288 /* Extract the base register from load/store insns. The function returns
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289 NULL_RTX if the address is not consist of any registers. */
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290 rtx
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291 extract_base_reg (rtx_insn *insn)
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292 {
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293 int post_update_rtx_index;
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294 rtx mem_rtx;
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295 rtx plus_rtx;
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296
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297 /* Find the MEM rtx. If we can find an insn updating the base register,
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298 the base register will be returned directly. */
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299 switch (get_attr_type (insn))
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300 {
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301 case TYPE_LOAD_MULTIPLE:
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302 post_update_rtx_index = find_post_update_rtx (insn);
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303
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304 if (post_update_rtx_index != -1)
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305 return SET_DEST (parallel_element (insn, post_update_rtx_index));
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306
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307 mem_rtx = SET_SRC (parallel_element (insn, 0));
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308 break;
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309
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310 case TYPE_STORE_MULTIPLE:
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311 post_update_rtx_index = find_post_update_rtx (insn);
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312
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313 if (post_update_rtx_index != -1)
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314 return SET_DEST (parallel_element (insn, post_update_rtx_index));
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315
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316 mem_rtx = SET_DEST (parallel_element (insn, 0));
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317 break;
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318
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319 case TYPE_LOAD:
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320 case TYPE_FLOAD:
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321 case TYPE_STORE:
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322 case TYPE_FSTORE:
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323 mem_rtx = extract_mem_rtx (insn);
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324 break;
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325
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326 default:
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327 gcc_unreachable ();
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328 }
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329
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330 gcc_assert (MEM_P (mem_rtx));
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331
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332 /* (mem (reg)) */
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333 if (REG_P (XEXP (mem_rtx, 0)))
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334 return XEXP (mem_rtx, 0);
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335
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336 /* (mem (lo_sum (reg) (symbol_ref)) */
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337 if (GET_CODE (XEXP (mem_rtx, 0)) == LO_SUM)
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338 return XEXP (XEXP (mem_rtx, 0), 0);
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339
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340 plus_rtx = XEXP (mem_rtx, 0);
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341
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342 if (GET_CODE (plus_rtx) == SYMBOL_REF
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343 || GET_CODE (plus_rtx) == CONST)
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344 return NULL_RTX;
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345
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346 /* (mem (plus (reg) (const_int))) or
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347 (mem (plus (mult (reg) (const_int 4)) (reg))) or
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348 (mem (post_inc (reg))) or
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349 (mem (post_dec (reg))) or
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350 (mem (post_modify (reg) (plus (reg) (reg)))) */
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351 gcc_assert (GET_CODE (plus_rtx) == PLUS
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352 || GET_CODE (plus_rtx) == POST_INC
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353 || GET_CODE (plus_rtx) == POST_DEC
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354 || GET_CODE (plus_rtx) == POST_MODIFY);
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355
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356 if (REG_P (XEXP (plus_rtx, 0)))
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357 return XEXP (plus_rtx, 0);
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358
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359 gcc_assert (REG_P (XEXP (plus_rtx, 1)));
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360 return XEXP (plus_rtx, 1);
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361 }
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362
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363 /* Extract the offset rtx from load/store insns. The function returns
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364 NULL_RTX if offset is absent. */
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365 rtx
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366 extract_offset_rtx (rtx_insn *insn)
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367 {
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368 rtx mem_rtx;
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369 rtx plus_rtx;
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370 rtx offset_rtx;
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371
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372 /* Find the MEM rtx. The multiple load/store insns doens't have
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373 the offset field so we can return NULL_RTX here. */
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374 switch (get_attr_type (insn))
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375 {
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376 case TYPE_LOAD_MULTIPLE:
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377 case TYPE_STORE_MULTIPLE:
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378 return NULL_RTX;
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379
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380 case TYPE_LOAD:
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381 case TYPE_FLOAD:
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382 case TYPE_STORE:
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383 case TYPE_FSTORE:
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384 mem_rtx = extract_mem_rtx (insn);
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385 break;
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386
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387 default:
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388 gcc_unreachable ();
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389 }
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390
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391 gcc_assert (MEM_P (mem_rtx));
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392
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393 /* (mem (reg)) */
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394 if (REG_P (XEXP (mem_rtx, 0)))
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395 return NULL_RTX;
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396
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397 plus_rtx = XEXP (mem_rtx, 0);
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398
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399 switch (GET_CODE (plus_rtx))
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400 {
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401 case SYMBOL_REF:
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402 case CONST:
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403 case POST_INC:
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404 case POST_DEC:
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405 return NULL_RTX;
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406
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407 case PLUS:
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408 /* (mem (plus (reg) (const_int))) or
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409 (mem (plus (mult (reg) (const_int 4)) (reg))) */
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410 if (REG_P (XEXP (plus_rtx, 0)))
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411 offset_rtx = XEXP (plus_rtx, 1);
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412 else
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413 {
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414 gcc_assert (REG_P (XEXP (plus_rtx, 1)));
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415 offset_rtx = XEXP (plus_rtx, 0);
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416 }
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417
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418 if (ARITHMETIC_P (offset_rtx))
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419 {
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420 gcc_assert (GET_CODE (offset_rtx) == MULT);
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421 gcc_assert (REG_P (XEXP (offset_rtx, 0)));
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422 offset_rtx = XEXP (offset_rtx, 0);
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423 }
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424 break;
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425
|
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426 case LO_SUM:
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427 /* (mem (lo_sum (reg) (symbol_ref)) */
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428 offset_rtx = XEXP (plus_rtx, 1);
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429 break;
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430
|
|
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431 case POST_MODIFY:
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432 /* (mem (post_modify (reg) (plus (reg) (reg / const_int)))) */
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433 gcc_assert (REG_P (XEXP (plus_rtx, 0)));
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434 plus_rtx = XEXP (plus_rtx, 1);
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435 gcc_assert (GET_CODE (plus_rtx) == PLUS);
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|
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436 offset_rtx = XEXP (plus_rtx, 0);
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|
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437 break;
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438
|
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439 default:
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440 gcc_unreachable ();
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|
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441 }
|
|
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442
|
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443 return offset_rtx;
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444 }
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|
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445
|
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446 /* Extract the register of the shift operand from an ALU_SHIFT rtx. */
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447 rtx
|
|
|
448 extract_shift_reg (rtx alu_shift_rtx)
|
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|
449 {
|
|
|
450 alu_shift_rtx = extract_pattern_from_insn (alu_shift_rtx);
|
|
|
451
|
|
|
452 rtx alu_rtx = SET_SRC (alu_shift_rtx);
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453 rtx shift_rtx;
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|
|
454
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455 /* Various forms of ALU_SHIFT can be made by the combiner.
|
|
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456 See the difference between add_slli and sub_slli in nds32.md. */
|
|
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457 if (REG_P (XEXP (alu_rtx, 0)))
|
|
|
458 shift_rtx = XEXP (alu_rtx, 1);
|
|
|
459 else
|
|
|
460 shift_rtx = XEXP (alu_rtx, 0);
|
|
|
461
|
|
|
462 return XEXP (shift_rtx, 0);
|
|
|
463 }
|
|
|
464
|
|
|
465 /* Check if INSN is a movd44 insn. */
|
|
|
466 bool
|
|
|
467 movd44_insn_p (rtx_insn *insn)
|
|
|
468 {
|
|
|
469 if (get_attr_type (insn) == TYPE_ALU
|
|
|
470 && (INSN_CODE (insn) == CODE_FOR_move_di
|
|
|
471 || INSN_CODE (insn) == CODE_FOR_move_df))
|
|
|
472 {
|
|
|
473 rtx body = PATTERN (insn);
|
|
|
474 gcc_assert (GET_CODE (body) == SET);
|
|
|
475
|
|
|
476 rtx src = SET_SRC (body);
|
|
|
477 rtx dest = SET_DEST (body);
|
|
|
478
|
|
|
479 if ((REG_P (src) || GET_CODE (src) == SUBREG)
|
|
|
480 && (REG_P (dest) || GET_CODE (dest) == SUBREG))
|
|
|
481 return true;
|
|
|
482
|
|
|
483 return false;
|
|
|
484 }
|
|
|
485
|
|
|
486 return false;
|
|
|
487 }
|
|
|
488
|
|
|
489 /* Extract the second result (odd reg) of a movd44 insn. */
|
|
|
490 rtx
|
|
|
491 extract_movd44_odd_reg (rtx_insn *insn)
|
|
|
492 {
|
|
|
493 gcc_assert (movd44_insn_p (insn));
|
|
|
494
|
|
|
495 rtx def_reg = SET_DEST (PATTERN (insn));
|
|
|
496 machine_mode mode;
|
|
|
497
|
|
|
498 gcc_assert (REG_P (def_reg) || GET_CODE (def_reg) == SUBREG);
|
|
|
499 switch (GET_MODE (def_reg))
|
|
|
500 {
|
|
|
501 case E_DImode:
|
|
|
502 mode = SImode;
|
|
|
503 break;
|
|
|
504
|
|
|
505 case E_DFmode:
|
|
|
506 mode = SFmode;
|
|
|
507 break;
|
|
|
508
|
|
|
509 default:
|
|
|
510 gcc_unreachable ();
|
|
|
511 }
|
|
|
512
|
|
|
513 return gen_highpart (mode, def_reg);
|
|
|
514 }
|
|
|
515
|
|
|
516 /* Extract the rtx representing non-accumulation operands of a MAC insn. */
|
|
|
517 rtx
|
|
|
518 extract_mac_non_acc_rtx (rtx_insn *insn)
|
|
|
519 {
|
|
|
520 rtx exp = SET_SRC (PATTERN (insn));
|
|
|
521
|
|
|
522 switch (get_attr_type (insn))
|
|
|
523 {
|
|
|
524 case TYPE_MAC:
|
|
|
525 case TYPE_DMAC:
|
|
|
526 if (REG_P (XEXP (exp, 0)))
|
|
|
527 return XEXP (exp, 1);
|
|
|
528 else
|
|
|
529 return XEXP (exp, 0);
|
|
|
530
|
|
|
531 default:
|
|
|
532 gcc_unreachable ();
|
|
|
533 }
|
|
|
534 }
|
|
|
535
|
|
|
536 /* Check if the DIV insn needs two write ports. */
|
|
|
537 bool
|
|
|
538 divmod_p (rtx_insn *insn)
|
|
|
539 {
|
|
|
540 gcc_assert (get_attr_type (insn) == TYPE_DIV);
|
|
|
541
|
|
|
542 if (INSN_CODE (insn) == CODE_FOR_divmodsi4
|
|
|
543 || INSN_CODE (insn) == CODE_FOR_udivmodsi4)
|
|
|
544 return true;
|
|
|
545
|
|
|
546 return false;
|
|
|
547 }
|
|
|
548
|
|
|
549 /* Extract the rtx representing the branch target to help recognize
|
|
|
550 data hazards. */
|
|
|
551 rtx
|
|
|
552 extract_branch_target_rtx (rtx_insn *insn)
|
|
|
553 {
|
|
|
554 gcc_assert (CALL_P (insn) || JUMP_P (insn));
|
|
|
555
|
|
|
556 rtx body = PATTERN (insn);
|
|
|
557
|
|
|
558 if (GET_CODE (body) == SET)
|
|
|
559 {
|
|
|
560 /* RTXs in IF_THEN_ELSE are branch conditions. */
|
|
|
561 if (GET_CODE (SET_SRC (body)) == IF_THEN_ELSE)
|
|
|
562 return NULL_RTX;
|
|
|
563
|
|
|
564 return SET_SRC (body);
|
|
|
565 }
|
|
|
566
|
|
|
567 if (GET_CODE (body) == CALL)
|
|
|
568 return XEXP (body, 0);
|
|
|
569
|
|
|
570 if (GET_CODE (body) == PARALLEL)
|
|
|
571 {
|
|
|
572 rtx first_rtx = parallel_element (body, 0);
|
|
|
573
|
|
|
574 if (GET_CODE (first_rtx) == SET)
|
|
|
575 return SET_SRC (first_rtx);
|
|
|
576
|
|
|
577 if (GET_CODE (first_rtx) == CALL)
|
|
|
578 return XEXP (first_rtx, 0);
|
|
|
579 }
|
|
|
580
|
|
|
581 /* Handle special cases of bltzal, bgezal and jralnez. */
|
|
|
582 if (GET_CODE (body) == COND_EXEC)
|
|
|
583 {
|
|
|
584 rtx addr_rtx = XEXP (body, 1);
|
|
|
585
|
|
|
586 if (GET_CODE (addr_rtx) == SET)
|
|
|
587 return SET_SRC (addr_rtx);
|
|
|
588
|
|
|
589 if (GET_CODE (addr_rtx) == PARALLEL)
|
|
|
590 {
|
|
|
591 rtx first_rtx = parallel_element (addr_rtx, 0);
|
|
|
592
|
|
|
593 if (GET_CODE (first_rtx) == SET)
|
|
|
594 {
|
|
|
595 rtx call_rtx = SET_SRC (first_rtx);
|
|
|
596 gcc_assert (GET_CODE (call_rtx) == CALL);
|
|
|
597
|
|
|
598 return XEXP (call_rtx, 0);
|
|
|
599 }
|
|
|
600
|
|
|
601 if (GET_CODE (first_rtx) == CALL)
|
|
|
602 return XEXP (first_rtx, 0);
|
|
|
603 }
|
|
|
604 }
|
|
|
605
|
|
|
606 gcc_unreachable ();
|
|
|
607 }
|
|
|
608
|
|
|
609 /* Extract the rtx representing the branch condition to help recognize
|
|
|
610 data hazards. */
|
|
|
611 rtx
|
|
|
612 extract_branch_condition_rtx (rtx_insn *insn)
|
|
|
613 {
|
|
|
614 gcc_assert (CALL_P (insn) || JUMP_P (insn));
|
|
|
615
|
|
|
616 rtx body = PATTERN (insn);
|
|
|
617
|
|
|
618 if (GET_CODE (body) == SET)
|
|
|
619 {
|
|
|
620 rtx if_then_else_rtx = SET_SRC (body);
|
|
|
621
|
|
|
622 if (GET_CODE (if_then_else_rtx) == IF_THEN_ELSE)
|
|
|
623 return XEXP (if_then_else_rtx, 0);
|
|
|
624
|
|
|
625 return NULL_RTX;
|
|
|
626 }
|
|
|
627
|
|
|
628 if (GET_CODE (body) == COND_EXEC)
|
|
|
629 return XEXP (body, 0);
|
|
|
630
|
|
|
631 return NULL_RTX;
|
|
|
632 }
|
|
|
633
|
|
|
634 } // namespace nds32
|
